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src/devices/cpu/m68000: add basic state viewer for Coldfire
1 parent 9a7943e commit e1b6d28

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7 files changed

+523
-107
lines changed

7 files changed

+523
-107
lines changed

‎src/devices/cpu/m68000/m68k_in.lst‎

Lines changed: 243 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -4686,6 +4686,33 @@ e3c0 ffc0 lsl w A+-DXWL 01:8 7:14 234fc:5
46864686
REG_DA()[(word2 >> 12) & 15] = m_vbr;
46874687
break;
46884688
default:
4689+
if (m_cpu_type == CPU_TYPE_COLDFIRE)
4690+
{
4691+
switch(word2 & 0xfff)
4692+
{
4693+
case 0xc00: // ROMBAR0
4694+
case 0xc01:
4695+
REG_DA()[(word2 >> 12) & 15] = m_rombar[word2 & 1];
4696+
return;
4697+
case 0xc04: // RAMBAR0
4698+
case 0xc05: // RAMBAR1
4699+
REG_DA()[(word2 >> 12) & 15] = m_rambar[word2 & 1];
4700+
return;
4701+
case 0xc0c: // MPCR
4702+
REG_DA()[(word2 >> 12) & 15] = m_mpcr;
4703+
return;
4704+
case 0xc0d: // EDRAMBAR
4705+
REG_DA()[(word2 >> 12) & 15] = m_edrambar;
4706+
return;
4707+
case 0xc0e: // SECMBAR
4708+
REG_DA()[(word2 >> 12) & 15] = m_secmbar;
4709+
return;
4710+
case 0xc0f: // MBAR
4711+
REG_DA()[(word2 >> 12) & 15] = m_mbar;
4712+
return;
4713+
}
4714+
}
4715+
46894716
m68ki_exception_illegal();
46904717
break;
46914718
}
@@ -4725,6 +4752,33 @@ e3c0 ffc0 lsl w A+-DXWL 01:8 7:14 234fc:5
47254752
REG_DA()[(word2 >> 12) & 15] = m_m_flag ? REG_ISP() : REG_SP();
47264753
break;
47274754
default:
4755+
if (m_cpu_type == CPU_TYPE_COLDFIRE)
4756+
{
4757+
switch(word2 & 0xfff)
4758+
{
4759+
case 0xc00: // ROMBAR0
4760+
case 0xc01:
4761+
REG_DA()[(word2 >> 12) & 15] = m_rombar[word2 & 1];
4762+
return;
4763+
case 0xc04: // RAMBAR0
4764+
case 0xc05: // RAMBAR1
4765+
REG_DA()[(word2 >> 12) & 15] = m_rambar[word2 & 1];
4766+
return;
4767+
case 0xc0c: // MPCR
4768+
REG_DA()[(word2 >> 12) & 15] = m_mpcr;
4769+
return;
4770+
case 0xc0d: // EDRAMBAR
4771+
REG_DA()[(word2 >> 12) & 15] = m_edrambar;
4772+
return;
4773+
case 0xc0e: // SECMBAR
4774+
REG_DA()[(word2 >> 12) & 15] = m_secmbar;
4775+
return;
4776+
case 0xc0f: // MBAR
4777+
REG_DA()[(word2 >> 12) & 15] = m_mbar;
4778+
return;
4779+
}
4780+
}
4781+
47284782
m68ki_exception_illegal();
47294783
break;
47304784
}
@@ -4788,6 +4842,33 @@ e3c0 ffc0 lsl w A+-DXWL 01:8 7:14 234fc:5
47884842
REG_DA()[(word2 >> 12) & 15] = m_mmu_srp_aptr;
47894843
break;
47904844
default:
4845+
if (m_cpu_type == CPU_TYPE_COLDFIRE)
4846+
{
4847+
switch(word2 & 0xfff)
4848+
{
4849+
case 0xc00: // ROMBAR0
4850+
case 0xc01:
4851+
REG_DA()[(word2 >> 12) & 15] = m_rombar[word2 & 1];
4852+
return;
4853+
case 0xc04: // RAMBAR0
4854+
case 0xc05: // RAMBAR1
4855+
REG_DA()[(word2 >> 12) & 15] = m_rambar[word2 & 1];
4856+
return;
4857+
case 0xc0c: // MPCR
4858+
REG_DA()[(word2 >> 12) & 15] = m_mpcr;
4859+
return;
4860+
case 0xc0d: // EDRAMBAR
4861+
REG_DA()[(word2 >> 12) & 15] = m_edrambar;
4862+
return;
4863+
case 0xc0e: // SECMBAR
4864+
REG_DA()[(word2 >> 12) & 15] = m_secmbar;
4865+
return;
4866+
case 0xc0f: // MBAR
4867+
REG_DA()[(word2 >> 12) & 15] = m_mbar;
4868+
return;
4869+
}
4870+
}
4871+
47914872
m68ki_exception_illegal();
47924873
break;
47934874
}
@@ -4838,31 +4919,34 @@ e3c0 ffc0 lsl w A+-DXWL 01:8 7:14 234fc:5
48384919
case 0x007: /* DTT1 */
48394920
REG_DA()[(word2 >> 12) & 15] = m_mmu_acr3;
48404921
break;
4841-
case 0xc00: // ROMBAR0
4842-
/* TODO */
4843-
break;
4844-
case 0xc01: // ROMBAR1
4845-
/* TODO */
4846-
break;
4847-
case 0xc04: // RAMBAR0
4848-
/* TODO */
4849-
break;
4850-
case 0xc05: // RAMBAR1
4851-
/* TODO */
4852-
break;
4853-
case 0xc0c: // MPCR
4854-
/* TODO */
4855-
break;
4856-
case 0xc0d: // EDRAMBAR
4857-
/* TODO */
4858-
break;
4859-
case 0xc0e: // SECMBAR
4860-
/* TODO */
4861-
break;
4862-
case 0xc0f: // MBAR
4863-
/* TODO */
4864-
break;
48654922
default:
4923+
if (m_cpu_type == CPU_TYPE_COLDFIRE)
4924+
{
4925+
switch(word2 & 0xfff)
4926+
{
4927+
case 0xc00: // ROMBAR0
4928+
case 0xc01:
4929+
REG_DA()[(word2 >> 12) & 15] = m_rombar[word2 & 1];
4930+
return;
4931+
case 0xc04: // RAMBAR0
4932+
case 0xc05: // RAMBAR1
4933+
REG_DA()[(word2 >> 12) & 15] = m_rambar[word2 & 1];
4934+
return;
4935+
case 0xc0c: // MPCR
4936+
REG_DA()[(word2 >> 12) & 15] = m_mpcr;
4937+
return;
4938+
case 0xc0d: // EDRAMBAR
4939+
REG_DA()[(word2 >> 12) & 15] = m_edrambar;
4940+
return;
4941+
case 0xc0e: // SECMBAR
4942+
REG_DA()[(word2 >> 12) & 15] = m_secmbar;
4943+
return;
4944+
case 0xc0f: // MBAR
4945+
REG_DA()[(word2 >> 12) & 15] = m_mbar;
4946+
return;
4947+
}
4948+
}
4949+
48664950
m68ki_exception_illegal();
48674951
break;
48684952
}
@@ -4890,6 +4974,33 @@ e3c0 ffc0 lsl w A+-DXWL 01:8 7:14 234fc:5
48904974
m_vbr = REG_DA()[(word2 >> 12) & 15];
48914975
break;
48924976
default:
4977+
if (m_cpu_type == CPU_TYPE_COLDFIRE)
4978+
{
4979+
switch(word2 & 0xfff)
4980+
{
4981+
case 0xc00: // ROMBAR0
4982+
case 0xc01:
4983+
m_rombar[word2 & 1] = REG_DA()[(word2 >> 12) & 15];
4984+
return;
4985+
case 0xc04: // RAMBAR0
4986+
case 0xc05: // RAMBAR1
4987+
m_rambar[word2 & 1] = REG_DA()[(word2 >> 12) & 15];
4988+
return;
4989+
case 0xc0c: // MPCR
4990+
m_mpcr = REG_DA()[(word2 >> 12) & 15];
4991+
return;
4992+
case 0xc0d: // EDRAMBAR
4993+
m_edrambar = REG_DA()[(word2 >> 12) & 15];
4994+
return;
4995+
case 0xc0e: // SECMBAR
4996+
m_secmbar = REG_DA()[(word2 >> 12) & 15];
4997+
return;
4998+
case 0xc0f: // MBAR
4999+
m_mbar = REG_DA()[(word2 >> 12) & 15];
5000+
return;
5001+
}
5002+
}
5003+
48935004
m68ki_exception_illegal();
48945005
break;
48955006
}
@@ -4945,6 +5056,33 @@ e3c0 ffc0 lsl w A+-DXWL 01:8 7:14 234fc:5
49455056
}
49465057
break;
49475058
default:
5059+
if (m_cpu_type == CPU_TYPE_COLDFIRE)
5060+
{
5061+
switch(word2 & 0xfff)
5062+
{
5063+
case 0xc00: // ROMBAR0
5064+
case 0xc01:
5065+
m_rombar[word2 & 1] = REG_DA()[(word2 >> 12) & 15];
5066+
return;
5067+
case 0xc04: // RAMBAR0
5068+
case 0xc05: // RAMBAR1
5069+
m_rambar[word2 & 1] = REG_DA()[(word2 >> 12) & 15];
5070+
return;
5071+
case 0xc0c: // MPCR
5072+
m_mpcr = REG_DA()[(word2 >> 12) & 15];
5073+
return;
5074+
case 0xc0d: // EDRAMBAR
5075+
m_edrambar = REG_DA()[(word2 >> 12) & 15];
5076+
return;
5077+
case 0xc0e: // SECMBAR
5078+
m_secmbar = REG_DA()[(word2 >> 12) & 15];
5079+
return;
5080+
case 0xc0f: // MBAR
5081+
m_mbar = REG_DA()[(word2 >> 12) & 15];
5082+
return;
5083+
}
5084+
}
5085+
49485086
m68ki_exception_illegal();
49495087
break;
49505088
}
@@ -5000,6 +5138,33 @@ e3c0 ffc0 lsl w A+-DXWL 01:8 7:14 234fc:5
50005138
}
50015139
break;
50025140
default:
5141+
if (m_cpu_type == CPU_TYPE_COLDFIRE)
5142+
{
5143+
switch(word2 & 0xfff)
5144+
{
5145+
case 0xc00: // ROMBAR0
5146+
case 0xc01:
5147+
m_rombar[word2 & 1] = REG_DA()[(word2 >> 12) & 15];
5148+
return;
5149+
case 0xc04: // RAMBAR0
5150+
case 0xc05: // RAMBAR1
5151+
m_rambar[word2 & 1] = REG_DA()[(word2 >> 12) & 15];
5152+
return;
5153+
case 0xc0c: // MPCR
5154+
m_mpcr = REG_DA()[(word2 >> 12) & 15];
5155+
return;
5156+
case 0xc0d: // EDRAMBAR
5157+
m_edrambar = REG_DA()[(word2 >> 12) & 15];
5158+
return;
5159+
case 0xc0e: // SECMBAR
5160+
m_secmbar = REG_DA()[(word2 >> 12) & 15];
5161+
return;
5162+
case 0xc0f: // MBAR
5163+
m_mbar = REG_DA()[(word2 >> 12) & 15];
5164+
return;
5165+
}
5166+
}
5167+
50035168
m68ki_exception_illegal();
50045169
break;
50055170
}
@@ -5087,6 +5252,33 @@ e3c0 ffc0 lsl w A+-DXWL 01:8 7:14 234fc:5
50875252
m_mmu_srp_aptr = REG_DA()[(word2 >> 12) & 15];
50885253
break;
50895254
default:
5255+
if (m_cpu_type == CPU_TYPE_COLDFIRE)
5256+
{
5257+
switch(word2 & 0xfff)
5258+
{
5259+
case 0xc00: // ROMBAR0
5260+
case 0xc01:
5261+
m_rombar[word2 & 1] = REG_DA()[(word2 >> 12) & 15];
5262+
return;
5263+
case 0xc04: // RAMBAR0
5264+
case 0xc05: // RAMBAR1
5265+
m_rambar[word2 & 1] = REG_DA()[(word2 >> 12) & 15];
5266+
return;
5267+
case 0xc0c: // MPCR
5268+
m_mpcr = REG_DA()[(word2 >> 12) & 15];
5269+
return;
5270+
case 0xc0d: // EDRAMBAR
5271+
m_edrambar = REG_DA()[(word2 >> 12) & 15];
5272+
return;
5273+
case 0xc0e: // SECMBAR
5274+
m_secmbar = REG_DA()[(word2 >> 12) & 15];
5275+
return;
5276+
case 0xc0f: // MBAR
5277+
m_mbar = REG_DA()[(word2 >> 12) & 15];
5278+
return;
5279+
}
5280+
}
5281+
50905282
m68ki_exception_illegal();
50915283
break;
50925284
}
@@ -5152,31 +5344,34 @@ e3c0 ffc0 lsl w A+-DXWL 01:8 7:14 234fc:5
51525344
case 0x007: /* DTT1 */
51535345
m_mmu_acr3 = REG_DA()[(word2 >> 12) & 15];
51545346
break;
5155-
case 0xc00: // ROMBAR0
5156-
/* TODO */
5157-
break;
5158-
case 0xc01: // ROMBAR1
5159-
/* TODO */
5160-
break;
5161-
case 0xc04: // RAMBAR0
5162-
/* TODO */
5163-
break;
5164-
case 0xc05: // RAMBAR1
5165-
/* TODO */
5166-
break;
5167-
case 0xc0c: // MPCR
5168-
/* TODO */
5169-
break;
5170-
case 0xc0d: // EDRAMBAR
5171-
/* TODO */
5172-
break;
5173-
case 0xc0e: // SECMBAR
5174-
/* TODO */
5175-
break;
5176-
case 0xc0f: // MBAR
5177-
/* TODO */
5178-
break;
51795347
default:
5348+
if (m_cpu_type == CPU_TYPE_COLDFIRE)
5349+
{
5350+
switch(word2 & 0xfff)
5351+
{
5352+
case 0xc00: // ROMBAR0
5353+
case 0xc01:
5354+
m_rombar[word2 & 1] = REG_DA()[(word2 >> 12) & 15];
5355+
return;
5356+
case 0xc04: // RAMBAR0
5357+
case 0xc05: // RAMBAR1
5358+
m_rambar[word2 & 1] = REG_DA()[(word2 >> 12) & 15];
5359+
return;
5360+
case 0xc0c: // MPCR
5361+
m_mpcr = REG_DA()[(word2 >> 12) & 15];
5362+
return;
5363+
case 0xc0d: // EDRAMBAR
5364+
m_edrambar = REG_DA()[(word2 >> 12) & 15];
5365+
return;
5366+
case 0xc0e: // SECMBAR
5367+
m_secmbar = REG_DA()[(word2 >> 12) & 15];
5368+
return;
5369+
case 0xc0f: // MBAR
5370+
m_mbar = REG_DA()[(word2 >> 12) & 15];
5371+
return;
5372+
}
5373+
}
5374+
51805375
m68ki_exception_illegal();
51815376
break;
51825377
}

‎src/devices/cpu/m68000/m68kcommon.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,9 @@ enum
3535
M68K_FP0, M68K_FP1, M68K_FP2, M68K_FP3, M68K_FP4, M68K_FP5, M68K_FP6, M68K_FP7,
3636
M68K_FPSR, M68K_FPCR, M68K_CRP_LIMIT, M68K_CRP_APTR, M68K_SRP_LIMIT, M68K_SRP_APTR,
3737
M68K_MMU_TC, M68K_TT0, M68K_TT1, M68K_MMU_SR, M68K_ITT0, M68K_ITT1,
38-
M68K_DTT0, M68K_DTT1, M68K_URP_APTR
38+
M68K_DTT0, M68K_DTT1, M68K_URP_APTR,
39+
COLDFIRE_ROMBAR0, COLDFIRE_ROMBAR1, COLDFIRE_RAMBAR0, COLDFIRE_RAMBAR1,
40+
COLDFIRE_MPCR, COLDFIRE_EDRAMBAR, COLDFIRE_SECMBAR, COLDFIRE_MBAR
3941
};
4042

4143
class m68000_base_device : public cpu_device

‎src/devices/cpu/m68000/m68kcpu.cpp‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2034,6 +2034,18 @@ void m68000_musashi_device::define_state(void)
20342034
state_add(M68K_SRP_APTR, "SRP", m_mmu_srp_aptr);
20352035
}
20362036
}
2037+
2038+
if (m_cpu_type == CPU_TYPE_COLDFIRE)
2039+
{
2040+
state_add(COLDFIRE_ROMBAR0, "ROMBAR0", m_rombar[0]);
2041+
state_add(COLDFIRE_ROMBAR1, "ROMBAR1", m_rombar[1]);
2042+
state_add(COLDFIRE_RAMBAR0, "RAMBAR0", m_rambar[0]);
2043+
state_add(COLDFIRE_RAMBAR1, "RAMBAR1", m_rambar[1]);
2044+
state_add(COLDFIRE_EDRAMBAR, "EDRAMBAR", m_edrambar);
2045+
state_add(COLDFIRE_SECMBAR, "SECMBAR", m_secmbar);
2046+
state_add(COLDFIRE_MPCR, "MPCR", m_mpcr);
2047+
state_add(COLDFIRE_MBAR, "MBAR", m_mbar);
2048+
}
20372049
}
20382050

20392051

‎src/devices/cpu/m68000/m68kmusashi.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -273,7 +273,9 @@ class m68000_musashi_device : public m68000_base_device
273273
u32 m_ic_data[M68K_IC_SIZE]; /* instruction cache content data */
274274
bool m_ic_valid[M68K_IC_SIZE]; /* instruction cache valid flags */
275275

276-
276+
// coldfire
277+
u32 m_rombar[2], m_rambar[2];
278+
u32 m_edrambar, m_secmbar, m_mbar, m_mpcr;
277279

278280
/* 68307 / 68340 internal address map */
279281
address_space *m_internal;

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