Merge pull request rustsbi#43 from YdrMaster/main

封装 aclint 定义和操作

Author: YdrMaster

CHANGELOG.md

@@ -16,6 +16,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 - Use instance based RustSBI interface, with separate functions for legacy stdio
 - Update sbi-testing to version 0.0.1
 - Use crate rcore-console version 0.0.0 in rustsbi-qemu and test-kernel for `print!` and `println!`
+- Use crate aclint version 0.0.0 in rustsbi-qemu for aclint structs
 - Use crate os-xtask-utils version 0.0.0 in xtask builder
 
 ### Fixed

Cargo.lock

@@ -26,6 +26,7 @@ uart_16550 = "0.2"
 rcore-console = "0.0.0"
 dtb-walker = "=0.2.0-alpha.3"
 qemu-exit = "3.0"
+aclint = "0.0.0"
 
 hsm-cell = { path = "../hsm-cell" }
 fast-trap = { git = "https://github.com/YdrMaster/fast-trap", rev = "ffb40e2", features = [

rustsbi-qemu/Cargo.toml

@@ -1,17 +1,26 @@
-#![allow(unused)]
-
-use crate::trap_stack::remote_hsm;
-use core::cell::UnsafeCell;
+use crate::{hart_id, trap_stack::remote_hsm};
+use aclint::SifiveClint;
+use core::{mem::MaybeUninit, ptr::NonNull};
 use rustsbi::{spec::binary::SbiRet, HartMask, Ipi, Timer};
 
 pub(crate) struct Clint;
 
+pub(crate) static mut CLINT: MaybeUninit<NonNull<SifiveClint>> = MaybeUninit::uninit();
+
+pub(crate) fn init(base: usize) {
+    unsafe {
+        CLINT
+            .as_mut_ptr()
+            .write_volatile(NonNull::new(base as _).unwrap())
+    }
+}
+
 impl Ipi for Clint {
     #[inline]
     fn send_ipi(&self, hart_mask: HartMask) -> SbiRet {
         for i in 0..crate::NUM_HART_MAX {
             if hart_mask.has_bit(i) && remote_hsm(i).map_or(false, |hsm| hsm.allow_ipi()) {
-                msip::send(i);
+                set_msip(i);
             }
         }
         SbiRet::success(0)
@@ -23,105 +32,24 @@ impl Timer for Clint {
     fn set_timer(&self, time_value: u64) {
         unsafe {
             riscv::register::mip::clear_stimer();
-            mtimecmp::set(time_value);
+            clint().write_mtimecmp(hart_id(), time_value);
         }
     }
 }
 
-static mut BASE: UnsafeCell<usize> = UnsafeCell::new(0);
-
 #[inline]
-pub(crate) fn init(base: usize) {
-    unsafe { *BASE.get() = base };
+fn clint() -> &'static SifiveClint {
+    unsafe { CLINT.as_ptr().read_volatile().as_ref() }
 }
 
-pub mod mtime {
-    #[inline]
-    pub fn read() -> u64 {
-        unsafe { ((super::BASE.get().read_volatile() + 0xbff8) as *mut u64).read_volatile() }
-    }
-}
-
-pub mod mtimecmp {
-    #[naked]
-    pub unsafe extern "C" fn set_naked(time_value: u64) {
-        core::arch::asm!(
-            // 保存必要寄存器
-            "   addi sp, sp, -16
-                sd   t0, 0(sp)
-                sd   t1, 8(sp)
-            ",
-            // 定位并设置当前核的 mtimecmp
-            "   li   t1, 0x4000
-                la   t0, {base}
-                ld   t0, 0(t0)
-                add  t0, t0, t1
-                csrr t1, mhartid
-                slli t1, t1, 3
-                add  t0, t0, t1
-                sd   a0, 0(t0)
-            ",
-            // 恢复上下文并返回
-            "   ld   t1, 8(sp)
-                ld   t0, 0(sp)
-                addi sp, sp,  16
-                ret
-            ",
-            base = sym super::BASE,
-            options(noreturn)
-        )
-    }
-
-    #[inline]
-    pub fn set(time_value: u64) {
-        unsafe { set_naked(time_value) };
-    }
-
-    #[inline]
-    pub fn clear() {
-        unsafe { set_naked(u64::MAX) };
-    }
+#[inline]
+pub fn set_msip(hart_idx: usize) {
+    clint().set_msip(hart_idx);
 }
 
-pub mod msip {
-    #[naked]
-    pub unsafe extern "C" fn clear_naked() -> usize {
-        core::arch::asm!(
-            // 保存必要寄存器
-            "   addi sp, sp, -16
-                sd   t0, 0(sp)
-                sd   t1, 8(sp)
-            ",
-            // 定位并清除当前核的 msip
-            "   la   t0, {base}
-                ld   t0, (t0)
-                csrr t1, mhartid
-                slli t1, t1, 2
-                add  t0, t0, t1
-                sw   zero, 0(t0)
-            ",
-            // 恢复上下文并返回
-            "   ld   t1, 8(sp)
-                ld   t0, 0(sp)
-                addi sp, sp,  16
-                ret
-            ",
-            base = sym super::BASE,
-            options(noreturn)
-        )
-    }
-
-    #[inline]
-    pub fn send(hart_id: usize) {
-        unsafe {
-            (super::BASE.get().read_volatile() as *mut u32)
-                .add(hart_id)
-                .write_volatile(1)
-        };
-    }
-
-    #[inline]
-    pub fn clear() {
-        unsafe { clear_naked() };
-    }
+#[inline]
+pub fn clear() {
+    let clint = clint();
+    clint.clear_msip(hart_id());
+    clint.write_mtimecmp(hart_id(), u64::MAX);
 }

rustsbi-qemu/src/clint.rs

@@ -141,8 +141,7 @@ extern "C" fn rust_main(hartid: usize, opaque: usize) {
         }
     }
     // 清理 clint
-    clint::msip::clear();
-    clint::mtimecmp::clear();
+    clint::clear();
     // 准备启动调度
     unsafe {
         asm!("csrw mcause, {}", in(reg) cause::BOOT);
@@ -259,15 +258,14 @@ extern "C" fn fast_handler(
                             return ctx.call(0);
                         }
                     }
-                    base::EID_BASE => {
-                        if a6 == base::PROBE_EXTENSION {
-                            if matches!(
+                    base::EID_BASE
+                        if a6 == base::PROBE_EXTENSION
+                            && matches!(
                                 ctx.a0(),
                                 legacy::LEGACY_CONSOLE_PUTCHAR | legacy::LEGACY_CONSOLE_GETCHAR
-                            ) {
-                                ret.value = 1;
-                            }
-                        }
+                            ) =>
+                    {
+                        ret.value = 1;
                     }
                     _ => {}
                 }
@@ -366,7 +364,7 @@ impl rustsbi::Hsm for Hsm {
         match remote_hsm(hartid) {
             Some(remote) => {
                 if remote.start(Supervisor { start_addr, opaque }) {
-                    clint::msip::send(hartid);
+                    clint::set_msip(hartid);
                     SbiRet::success(0)
                 } else {
                     SbiRet::already_started()

rustsbi-qemu/src/main.rs

@@ -1,4 +1,4 @@
-use crate::clint;
+use aclint::SifiveClint as Clint;
 use core::arch::asm;
 use fast_trap::trap_entry;
 use riscv::register::mtvec::{self, TrapMode::*};
@@ -52,23 +52,28 @@ unsafe extern "C" fn mtimer() {
         // sp      : M sp
         // mscratch: S sp
         "   csrrw sp, mscratch, sp",
-        // 需要 a0 传参，保护
-        "   addi sp, sp, -16
-            sd   ra, 0(sp)
-            sd   a0, 8(sp)
+        // 保护
+        "   sd    ra, -1*8(sp)
+            sd    a0, -2*8(sp)
+            sd    a1, -3*8(sp)
+            sd    a2, -4*8(sp)
         ",
-        // clint::mtimecmp::clear();
-        "   li   a0, {u64_max}
-            call {set_mtimecmp}
+        // 清除 mtimecmp
+        "   la    a0, {clint_ptr}
+            ld    a0, (a0)
+            csrr  a1, mhartid
+            li    a2, {u64_max}
+            call  {set_mtimecmp}
         ",
-        // mip::set_stimer();
-        "   li   a0, {mip_stip}
-           csrrs zero, mip, a0
+        // 设置 stip
+        "   li    a0, {mip_stip}
+            csrrs zero, mip, a0
         ",
-        // 恢复 a0
-        "   ld   a0, 8(sp)
-            ld   ra, 0(sp)
-            addi sp, sp,  16
+        // 恢复
+        "   ld    ra, -1*8(sp)
+            ld    a0, -2*8(sp)
+            ld    a1, -3*8(sp)
+            ld    a2, -4*8(sp)
         ",
         // 换栈：
         // sp      : S sp
@@ -78,7 +83,9 @@ unsafe extern "C" fn mtimer() {
         "   mret",
         u64_max      = const u64::MAX,
         mip_stip     = const 1 << 5,
-        set_mtimecmp =   sym clint::mtimecmp::set_naked,
+        clint_ptr    =   sym crate::clint::CLINT,
+        //                   Clint::write_mtimecmp_naked(&self, hart_idx, val)
+        set_mtimecmp =   sym Clint::write_mtimecmp_naked,
         options(noreturn)
     )
 }
@@ -95,26 +102,32 @@ unsafe extern "C" fn msoft() {
         // sp      : M sp
         // mscratch: S sp
         "   csrrw sp, mscratch, sp",
-        // 保护 ra
-        "   addi sp, sp, -8
-            sd   ra, 0(sp)
+        // 保护
+        "   sd   ra, -1*8(sp)
+            sd   a0, -2*8(sp)
+            sd   a1, -3*8(sp)
         ",
-        // clint::msip::clear();
-        // mip::set_ssoft();
-        "   call   {clear_msip}
+        // 清除 msip 设置 ssip
+        "   la   a0, {clint_ptr}
+            ld   a0, (a0)
+            csrr a1, mhartid
+            call {clear_msip}
             csrrsi zero, mip, 1 << 1
         ",
-        // 恢复 ra
-        "   ld   ra, 0(sp)
-            addi sp, sp,  8
+        // 恢复
+        "   ld   ra, -1*8(sp)
+            ld   a0, -2*8(sp)
+            ld   a1, -3*8(sp)
         ",
         // 换栈：
         // sp      : S sp
         // mscratch: M sp
         "   csrrw sp, mscratch, sp",
         // 返回
         "   mret",
-        clear_msip = sym clint::msip::clear_naked,
+        clint_ptr  = sym crate::clint::CLINT,
+        //               Clint::clear_msip_naked(&self, hart_idx)
+        clear_msip = sym Clint::clear_msip_naked,
         options(noreturn)
     )
 }

rustsbi-qemu/src/trap_vec.rs

@@ -144,7 +144,7 @@ impl QemuArgs {
             _ => panic!(),
         };
         let status = Qemu::system("riscv64")
-            .args(&["-machine", "virt"])
+            .args(["-machine", "virt"])
             .arg("-nographic")
             .arg("-bios")
             .arg(sbi)