refactor: uart16550 驱动拆分到单独的库中

Signed-off-by: YdrMaster <[email protected]>

Author: YdrMaster

Cargo.lock

@@ -27,6 +27,7 @@ rcore-console = "0.0.0"
 aclint = "0.0.0"
 sifive-test-device = "0.0.0"
 dtb-walker = "=0.2.0-alpha.3"
+uart16550 = { git = "https://github.com/YdrMaster/uart16550", rev = "68ad4d8" }
 
 hsm-cell = { path = "../hsm-cell" }
 fast-trap = { version = "=0.0.1", features = ["riscv-m"] }

rustsbi-qemu/Cargo.toml

@@ -22,14 +22,8 @@ impl Console for DBCN {
         let start = bytes.phys_addr_lo();
         let end = start + bytes.num_bytes();
         if self.0.contains(&start) && self.0.contains(&(end - 1)) {
-            let uart = uart16550::UART.lock();
-            for ptr in start..end {
-                let c = unsafe { (ptr as *const u8).read_volatile() };
-                if !uart.get().write(c) {
-                    return SbiRet::success(ptr - start);
-                }
-            }
-            SbiRet::success(bytes.num_bytes())
+            let buf = unsafe { core::slice::from_raw_parts(start as *const u8, bytes.num_bytes()) };
+            SbiRet::success(uart16550::UART.lock().get().write(buf))
         } else {
             SbiRet::invalid_param()
         }
@@ -39,15 +33,9 @@ impl Console for DBCN {
         let start = bytes.phys_addr_lo();
         let end = start + bytes.num_bytes();
         if self.0.contains(&start) && self.0.contains(&(end - 1)) {
-            let uart = uart16550::UART.lock();
-            for ptr in start..end {
-                if let Some(c) = uart.get().read() {
-                    unsafe { (ptr as *mut u8).write_volatile(c) };
-                } else {
-                    return SbiRet::success(ptr - start);
-                }
-            }
-            SbiRet::success(bytes.num_bytes())
+            let buf =
+                unsafe { core::slice::from_raw_parts_mut(start as *mut u8, bytes.num_bytes()) };
+            SbiRet::success(uart16550::UART.lock().get().read(buf))
         } else {
             SbiRet::invalid_param()
         }
@@ -57,7 +45,7 @@ impl Console for DBCN {
     fn write_byte(&self, byte: u8) -> SbiRet {
         let uart = uart16550::UART.lock();
         loop {
-            if uart.get().write(byte) {
+            if uart.get().write(&[byte]) == 1 {
                 return SbiRet::success(0);
             }
         }

rustsbi-qemu/src/dbcn.rs

@@ -262,14 +262,17 @@ extern "C" fn fast_handler(
                                 ret.error = 0;
                                 ret.value = a1;
                             }
-                            legacy::LEGACY_CONSOLE_GETCHAR => loop {
+                            legacy::LEGACY_CONSOLE_GETCHAR => {
+                                let mut c = 0u8;
                                 let uart = uart16550::UART.lock();
-                                if let Some(c) = uart.get().read() {
-                                    ret.error = c as _;
-                                    ret.value = a1;
-                                    break;
+                                loop {
+                                    if uart.get().read(core::slice::from_mut(&mut c)) == 1 {
+                                        ret.error = c as _;
+                                        ret.value = a1;
+                                        break;
+                                    }
                                 }
-                            },
+                            }
                             _ => {}
                         }
                     }
@@ -325,18 +328,18 @@ impl rcore_console::Console for Console {
     #[inline]
     fn put_char(&self, c: u8) {
         let uart = uart16550::UART.lock();
-        while !uart.get().write(c) {
+        while uart.get().write(&[c]) == 0 {
             core::hint::spin_loop();
         }
     }
 
     #[inline]
     fn put_str(&self, s: &str) {
         let uart = uart16550::UART.lock();
-        for c in s.bytes() {
-            while !uart.get().write(c) {
-                core::hint::spin_loop();
-            }
+        let mut bytes = s.as_bytes();
+        while !bytes.is_empty() {
+            let count = uart.get().write(bytes);
+            bytes = &bytes[count..];
         }
     }
 }

rustsbi-qemu/src/main.rs

@@ -1,55 +1,21 @@
-use core::{cell::UnsafeCell, ptr::null};
+use core::ptr::null;
 use spin::lock_api::Mutex;
+use uart16550::Uart16550;
 
 pub(crate) static UART: Mutex<Uart16550Map> = Mutex::new(Uart16550Map(null()));
 
 pub(crate) fn init(base: usize) {
     *UART.lock() = Uart16550Map(base as _);
 }
 
-pub struct Uart16550Map(*const Uart16550);
+pub struct Uart16550Map(*const Uart16550<u8>);
 
 unsafe impl Send for Uart16550Map {}
 unsafe impl Sync for Uart16550Map {}
 
 impl Uart16550Map {
     #[inline]
-    pub fn get(&self) -> &Uart16550 {
+    pub fn get(&self) -> &Uart16550<u8> {
         unsafe { &*self.0 }
     }
 }
-
-#[allow(unused)]
-pub struct Uart16550 {
-    data: UnsafeCell<u8>,
-    int_en: UnsafeCell<u8>,
-    fifo_ctrl: UnsafeCell<u8>,
-    line_ctrl: UnsafeCell<u8>,
-    modem_ctrl: UnsafeCell<u8>,
-    line_sts: UnsafeCell<u8>,
-}
-
-impl Uart16550 {
-    pub fn write(&self, data: u8) -> bool {
-        const OUTPUT_EMPTY: u8 = 1 << 5;
-        return unsafe {
-            if self.line_sts.get().read_volatile() & OUTPUT_EMPTY == OUTPUT_EMPTY {
-                self.data.get().write_volatile(data);
-                true
-            } else {
-                false
-            }
-        };
-    }
-
-    pub fn read(&self) -> Option<u8> {
-        const INPUT_FULL: u8 = 1;
-        return unsafe {
-            if self.line_sts.get().read_volatile() & INPUT_FULL == INPUT_FULL {
-                Some(self.data.get().read_volatile())
-            } else {
-                None
-            }
-        };
-    }
-}