Merge pull request rustsbi#41 from YdrMaster/main

增加性能测试

Author: luojia65

CHANGELOG.md

@@ -2,19 +2,20 @@
 
 All notable changes to this project will be documented in this file.
 
-The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/), and this project adheres
-to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
+The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/), and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
 ## [Unreleased]
 
 ### Added
 
 - Hint spin loop in hart state monitor module
+- Add bench-kernel crate to workspace for sbi call bench
 
 ### Modified
 
 - Use instance based RustSBI interface, with separate functions for legacy stdio
 - Update sbi-testing to version 0.0.1
+- Use crate rcore-console version 0.0.0 in rustsbi-qemu and test-kernel for `print!` and `println!`
 - Use crate os-xtask-utils version 0.0.0 in xtask builder
 
 ### Fixed

Cargo.lock

@@ -1,3 +1,3 @@
 [workspace]
-members = ["rustsbi-qemu", "test-kernel", "xtask"]
+members = ["rustsbi-qemu", "test-kernel", "bench-kernel", "xtask"]
 default-members = ["xtask"]

Cargo.toml

@@ -0,0 +1,15 @@
+[package]
+name = "bench-kernel"
+version = "0.0.1"
+edition = "2021"
+authors = ["YdrMaster <[email protected]>"]
+publish = false
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
+sbi-rt = "0.0.2"
+riscv = "0.9.0"
+r0 = "1"
+uart_16550 = "0.2"
+rcore-console = "0.0.0"

bench-kernel/Cargo.toml

@@ -0,0 +1,45 @@
+fn main() {
+    use std::{env, fs, path::PathBuf};
+
+    let ld = PathBuf::from(env::var_os("OUT_DIR").unwrap()).join("linker.ld");
+    fs::write(&ld, LINKER).unwrap();
+    println!("cargo:rerun-if-changed=build.rs");
+    println!("cargo:rustc-link-arg=-T{}", ld.display());
+}
+
+const LINKER: &[u8] = b"
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+MEMORY {
+    DRAM : ORIGIN = 0x80200000, LENGTH = 64M
+}
+SECTIONS {
+    .text : ALIGN(4) {
+        *(.text.entry)
+        *(.text .text.*)
+    } > DRAM
+    .rodata : ALIGN(8) {
+        srodata = .;
+        *(.rodata .rodata.*)
+        *(.srodata .srodata.*)
+        . = ALIGN(8);
+        erodata = .;
+    } > DRAM
+    .data : ALIGN(8) {
+        sdata = .;
+        *(.data .data.*)
+        *(.sdata .sdata.*)
+        . = ALIGN(8);
+        edata = .;
+    } > DRAM
+    .bss (NOLOAD) : ALIGN(8) {
+        *(.bss.uninit)
+        sbss = .;
+        *(.bss .bss.*)
+        *(.sbss .sbss.*)
+        ebss = .;
+    } > DRAM
+    /DISCARD/ : {
+        *(.eh_frame)
+    }
+}";

bench-kernel/build.rs

@@ -0,0 +1,101 @@
+#![no_std]
+#![no_main]
+#![feature(naked_functions, asm_const)]
+#![deny(warnings)]
+
+use core::mem::MaybeUninit;
+use rcore_console::log;
+use riscv::register::*;
+use sbi_rt::*;
+use uart_16550::MmioSerialPort;
+
+#[naked]
+#[no_mangle]
+#[link_section = ".text.entry"]
+unsafe extern "C" fn _start(hartid: usize, device_tree_paddr: usize) -> ! {
+    const STACK_SIZE: usize = 16384; // 16 KiB
+
+    #[link_section = ".bss.uninit"]
+    static mut STACK: [u8; STACK_SIZE] = [0u8; STACK_SIZE];
+
+    core::arch::asm!(
+        "la sp,  {stack} + {stack_size}",
+        "j  {main}",
+        stack_size = const STACK_SIZE,
+        stack      = sym   STACK,
+        main       = sym   rust_main,
+        options(noreturn),
+    )
+}
+
+extern "C" fn rust_main(hartid: usize, _dtb_pa: usize) -> ! {
+    extern "C" {
+        static mut sbss: u64;
+        static mut ebss: u64;
+    }
+    unsafe { r0::zero_bss(&mut sbss, &mut ebss) };
+    // 初始化打印
+    unsafe { UART = MaybeUninit::new(MmioSerialPort::new(0x1000_0000)) };
+    rcore_console::init_console(&Console);
+    rcore_console::set_log_level(option_env!("LOG"));
+    rcore_console::test_log();
+    // 打开软中断
+    unsafe {
+        sie::set_ssoft();
+        sstatus::set_sie();
+    };
+    // 测试调用延迟
+    let t0 = time::read();
+
+    for _ in 0..0xffff {
+        let _ = sbi_rt::get_marchid();
+    }
+
+    let t1 = time::read();
+    log::info!("marchid duration = {}", t1 - t0);
+    // 测试中断响应延迟
+    let t0 = time::read();
+
+    for _ in 0..0xffff {
+        unsafe {
+            core::arch::asm!(
+                "   la   {0}, 1f
+                    csrw stvec, {0}
+                    ecall
+                    wfi
+                .align 2
+                1:
+                ",
+                out(reg) _,
+                in("a7") 0x735049,
+                in("a6") 0,
+                in("a0") 1 << hartid,
+                in("a1") 0,
+                options(nomem),
+            );
+        }
+    }
+
+    let t1 = time::read();
+    log::info!("ipi duration = {}", t1 - t0);
+
+    system_reset(Shutdown, NoReason);
+    unreachable!()
+}
+
+#[panic_handler]
+fn panic(info: &core::panic::PanicInfo) -> ! {
+    log::error!("{info}");
+    system_reset(Shutdown, SystemFailure);
+    loop {}
+}
+
+struct Console;
+static mut UART: MaybeUninit<MmioSerialPort> = MaybeUninit::uninit();
+
+impl rcore_console::Console for Console {
+    #[inline]
+    fn put_char(&self, c: u8) {
+        unsafe { UART.assume_init_mut() }.send(c);
+    }
+}

bench-kernel/src/main.rs

@@ -23,5 +23,6 @@ riscv = "0.9.0"
 spin = "0.9"
 r0 = "1"
 uart_16550 = "0.2"
+rcore-console = "0.0.0"
 dtb-walker = "=0.2.0-alpha.3"
 qemu-exit = "3.0"

rustsbi-qemu/Cargo.toml

@@ -59,12 +59,11 @@ impl<'a> Environment<'a> {
         use rustsbi::spec::{binary::*, hsm::*, srst::*};
         if self.ctx.sbi_extension() == sbi_spec::legacy::LEGACY_CONSOLE_PUTCHAR {
             let ch = self.ctx.a(0);
-            crate::console::STDOUT.wait().putchar((ch & 0xFF) as u8);
+            print!("{:}", ch as u8 as char);
             self.ctx.mepc = self.ctx.mepc.wrapping_add(4);
             return None;
         } else if self.ctx.sbi_extension() == sbi_spec::legacy::LEGACY_CONSOLE_GETCHAR {
-            let ch = crate::console::STDOUT.wait().getchar();
-            *self.ctx.a_mut(0) = ch as usize;
+            *self.ctx.a_mut(0) = unsafe { crate::UART.lock().assume_init_mut().receive() } as usize;
             self.ctx.mepc = self.ctx.mepc.wrapping_add(4);
             return None;
         }