diff --git a/boards/riscv/titanium_ti60_f225/Kconfig.board b/boards/riscv/titanium_ti60_f225/Kconfig.board new file mode 100644 index 0000000000000..d6ed41ffc79d1 --- /dev/null +++ b/boards/riscv/titanium_ti60_f225/Kconfig.board @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TITANIUM_TI60_F225 + bool "Board with Efinix Sapphire riscv SoC" + depends on SOC_SERIES_EFINIX_SAPPHIRE diff --git a/boards/riscv/titanium_ti60_f225/Kconfig.defconfig b/boards/riscv/titanium_ti60_f225/Kconfig.defconfig new file mode 100644 index 0000000000000..577c21b3d1a68 --- /dev/null +++ b/boards/riscv/titanium_ti60_f225/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_TITANIUM_TI60_F225 + +config BOARD + default "titanium_ti60_f225" + +endif # BOARD_TITANIUM_TI60_F225 diff --git a/boards/riscv/titanium_ti60_f225/doc/img/Ti60-BGA225-board-block-diagram.jpg b/boards/riscv/titanium_ti60_f225/doc/img/Ti60-BGA225-board-block-diagram.jpg new file mode 100644 index 0000000000000..b6d1990a7203e Binary files /dev/null and b/boards/riscv/titanium_ti60_f225/doc/img/Ti60-BGA225-board-block-diagram.jpg differ diff --git a/boards/riscv/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg b/boards/riscv/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg new file mode 100644 index 0000000000000..0227413a6d79c Binary files /dev/null and b/boards/riscv/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg differ diff --git a/boards/riscv/titanium_ti60_f225/doc/index.rst b/boards/riscv/titanium_ti60_f225/doc/index.rst new file mode 100644 index 0000000000000..1b6430e9309f3 --- /dev/null +++ b/boards/riscv/titanium_ti60_f225/doc/index.rst @@ -0,0 +1,60 @@ +.. _titanium_ti60_f225: + +Efinix Titanium Ti60 F225 +######################### + +Overview +******** + +The Efinix Titanium Ti60 F225 development kit contains a Ti60 FPGA, which is fabricated on a 16nm process and deliver +high performance with the lowest possible power on a small physical size. In addition, Efinix offers Sapphire SoC IP, +which is a user-configurable RISC-V SoC based on the VexRiscv core with configurable feature set and extension. +Using the Efinity IP Manager, you can configure the SoC to include only the peripherals that you require. + +.. figure:: img/ti60f225-board-top.jpg + :align: center + :alt: titanium_ti60_f225_board + +Figure is the development board + +Board block diagram +******************* + +.. figure:: img/Ti60-BGA225-board-block-diagram.jpg + :align: center + :alt: titanium_ti60_f225_board-block-diagram + +More information can be found on `Ti60F225`_ website. + +Sapphire SoC setup on the FPGA guide +************************************* + +Guide to setup the SoC found at `Efinix-Zephyr`_ + +Building +******** + +Build applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: titanium_ti60_f225 + :goals: build + +Flashing +******** + +Flashing the binary into SPI NOR flash requires Efinity programmer, Please find the guide at `Efinix-Zephyr`_ + +.. note:: + + The Zephyr RTOS has been verified using the SoC bitstream generated by Efinity IDE v2022.2.322. + +References +********** + +.. target-notes:: + +.. _Ti60F225: https://www.efinixinc.com/products-devkits-titaniumti60f225.html +.. _Efinix-Zephyr: https://github.com/Efinix-Inc/zephyr-efinix diff --git a/boards/riscv/titanium_ti60_f225/titanium_ti60_f225.dts b/boards/riscv/titanium_ti60_f225/titanium_ti60_f225.dts new file mode 100644 index 0000000000000..8487efea0dac8 --- /dev/null +++ b/boards/riscv/titanium_ti60_f225/titanium_ti60_f225.dts @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2023 Efinix Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "Efinix Titanium Ti60 F225"; + compatible = "efinix,titanium-ti60-f225"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram0; + }; + + aliases { + led0 = &green_led; + }; + + leds { + compatible = "gpio-leds"; + + green_led: led_0 { + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + label = "Green LED 3"; + }; + + + red_led: led_1 { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "Red LED 2"; + }; + + blue_led: led_2 { + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + label = "Blue LED 1"; + }; + + }; + +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/boards/riscv/titanium_ti60_f225/titanium_ti60_f225.yaml b/boards/riscv/titanium_ti60_f225/titanium_ti60_f225.yaml new file mode 100644 index 0000000000000..b52f6d8660a0b --- /dev/null +++ b/boards/riscv/titanium_ti60_f225/titanium_ti60_f225.yaml @@ -0,0 +1,10 @@ +identifier: titanium_ti60_f225 +name: titanium_ti60_f225 FPGA development kit with Efinix Sapphire riscv SoC +type: mcu +arch: riscv32 +toolchain: + - zephyr +ram: 196608 +supported: + - gpio + - uart diff --git a/boards/riscv/titanium_ti60_f225/titanium_ti60_f225_defconfig b/boards/riscv/titanium_ti60_f225/titanium_ti60_f225_defconfig new file mode 100644 index 0000000000000..096980b864ecd --- /dev/null +++ b/boards/riscv/titanium_ti60_f225/titanium_ti60_f225_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_SERIES_EFINIX_SAPPHIRE=y +CONFIG_BOARD_TITANIUM_TI60_F225=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=n +CONFIG_XIP=n +CONFIG_HEAP_MEM_POOL_SIZE=16384 +CONFIG_INIT_STACKS=n diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index 810236106d378..fe0a790fd538c 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -76,6 +76,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_RT1718S gpio_rt1718s.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RT1718S gpio_rt1718s_port.c) zephyr_library_sources_ifdef(CONFIG_GPIO_NUMICRO gpio_numicro.c) zephyr_library_sources_ifdef(CONFIG_GPIO_HOGS gpio_hogs.c) +zephyr_library_sources_ifdef(CONFIG_GPIO_EFINIX_SAPPHIRE gpio_efinix_sapphire.c) if(CONFIG_GPIO_SC18IM704) zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 53688855d077a..590e7c2081d0a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -195,4 +195,6 @@ source "drivers/gpio/Kconfig.bd8lb600fs" source "drivers/gpio/Kconfig.sc18im704" +source "drivers/gpio/Kconfig.efinix_sapphire" + endif # GPIO diff --git a/drivers/gpio/Kconfig.efinix_sapphire b/drivers/gpio/Kconfig.efinix_sapphire new file mode 100644 index 0000000000000..fdbc431eb938a --- /dev/null +++ b/drivers/gpio/Kconfig.efinix_sapphire @@ -0,0 +1,9 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +config GPIO_EFINIX_SAPPHIRE + bool "Efinx sapphire GPIO driver" + default y + depends on DT_HAS_EFINIX_SAPPHIRE_GPIO_ENABLED + help + Enable Efinix sapphire GPIO driver. diff --git a/drivers/gpio/gpio_efinix_sapphire.c b/drivers/gpio/gpio_efinix_sapphire.c new file mode 100644 index 0000000000000..2302eb6737ad8 --- /dev/null +++ b/drivers/gpio/gpio_efinix_sapphire.c @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2023 Efinix Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT efinix_sapphire_gpio + +#include "gpio_efinix_sapphire_priv.h" +#include + +#include +#include + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(gpio_efinix_sapphire); + +#define SUPPORTED_FLAGS \ + (GPIO_INPUT | GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH | \ + GPIO_ACTIVE_LOW | GPIO_ACTIVE_HIGH) + +#define GPIO_LOW 0 +#define GPIO_HIGH 1 + +/* efinix sapphire specefic gpio config struct */ +struct gpio_efinix_sapphire_cfg { + uint32_t base_addr; + int n_gpios; + struct gpio_driver_config common; +}; + +/* efinix sapphire specefic gpio data struct */ +struct gpio_efinix_sapphire_data { + struct gpio_driver_data common; + const struct device *dev; + sys_slist_t cb; +}; + +/* Device access pointer helpers */ +#define DEV_GPIO_CFG(dev) ((const struct gpio_efinix_sapphire_cfg *)(dev)->config) +#define GPIO_OUTPUT_ADDR config->base_addr + BSP_GPIO_OUTPUT + +static inline void cfg_output_enable_bit(const struct gpio_efinix_sapphire_cfg *config, + gpio_pin_t pin, uint32_t type) +{ + +#define GPIO_OUTPUT_ENABLE_ADDR config->base_addr + BSP_GPIO_OUTPUT_ENABLE + uint32_t c_reg_val = sys_read32(GPIO_OUTPUT_ENABLE_ADDR); + + if (type == GPIO_INPUT) { + sys_write32(c_reg_val &= ~pin, GPIO_OUTPUT_ENABLE_ADDR); + } else if (type == GPIO_OUTPUT) { + sys_write32(c_reg_val |= pin, GPIO_OUTPUT_ENABLE_ADDR); + } +} + +static inline void cfg_output_bit(const struct gpio_efinix_sapphire_cfg *config, gpio_pin_t pin, + uint32_t value) +{ + + uint32_t c_reg_val = sys_read32(GPIO_OUTPUT_ADDR); + + if (value == GPIO_LOW) { + sys_write32(c_reg_val &= ~pin, GPIO_OUTPUT_ADDR); + } else if (value == GPIO_HIGH) { + sys_write32(c_reg_val |= pin, GPIO_OUTPUT_ADDR); + } +} + +/* To use the controller bare minimun as IO, Peripheral has to configure, */ +/* the Output enable register, b0 : Input, b1 : Output */ + +static int gpio_efinix_sapphire_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) +{ + const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev); + /* Check if the controller supports the requested GPIO configuration. */ + if (flags & ~SUPPORTED_FLAGS) { + return -ENOTSUP; + } + + if ((flags & GPIO_DIR_MASK) == GPIO_DIR_MASK) { + /* Pin cannot be configured as input and output */ + return -ENOTSUP; + } else if ((flags & GPIO_DIR_MASK) == GPIO_DISCONNECTED) { + /* Pin has to be configured as input or output */ + return -ENOTSUP; + } + + /* Configure the output register based on the direction flag */ + if (flags & GPIO_OUTPUT) { + /* Set the pin as output */ + cfg_output_enable_bit(config, BIT(pin), GPIO_OUTPUT); + if (flags & GPIO_OUTPUT_INIT_HIGH) { + /* Set the pin to high */ + cfg_output_bit(config, BIT(pin), GPIO_HIGH); + } else if (flags & GPIO_OUTPUT_INIT_LOW) { + /* Set the pin to low */ + cfg_output_bit(config, BIT(pin), GPIO_LOW); + } + } else { + /* Set the pin as input */ + cfg_output_enable_bit(config, BIT(pin), GPIO_INPUT); + } + + return 0; +} + +static inline uint32_t get_port(const struct gpio_efinix_sapphire_cfg *config) +{ + uint32_t c_reg_val = sys_read32(GPIO_OUTPUT_ADDR); + + return (c_reg_val & BIT_MASK(config->n_gpios)); +} + +static inline void set_port(const struct gpio_efinix_sapphire_cfg *config, uint32_t value) +{ + sys_write32(value, GPIO_OUTPUT_ADDR); +} + +static int gpio_efinix_sapphire_port_get_raw(const struct device *dev, gpio_port_value_t *value) +{ + const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev); + + *value = get_port(config); + return 0; +} + +static int gpio_efinix_sapphire_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, + gpio_port_value_t value) +{ + const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev); + + uint32_t c_reg_val = get_port(config); + + /* Sets ports value at one go */ + c_reg_val &= ~mask; + c_reg_val |= (value & mask); + + set_port(config, c_reg_val); + + return 0; +} + +static int gpio_efinix_sapphire_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev); + + uint32_t c_reg_val = get_port(config); + + /* Sets ports value at one go */ + c_reg_val |= pins; + + set_port(config, c_reg_val); + + return 0; +} + +static int gpio_efinix_sapphire_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev); + + uint32_t c_reg_val = get_port(config); + + /* Sets ports value at one go */ + c_reg_val &= ~pins; + + set_port(config, c_reg_val); + + return 0; +} + +static int gpio_efinix_sapphire_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) +{ + const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev); + + uint32_t c_reg_val = get_port(config); + + /* Sets ports value at one go */ + c_reg_val ^= pins; + + set_port(config, c_reg_val); + + return 0; +} + +static int gpio_efinix_sapphire_init(const struct device *dev) +{ + const struct gpio_efinix_sapphire_cfg *config = DEV_GPIO_CFG(dev); + + if (config->n_gpios > 4) { + return -EINVAL; + } + return 0; +} + +/* API map */ +static const struct gpio_driver_api gpio_efinix_sapphire_api = { + .pin_configure = gpio_efinix_sapphire_config, + .port_get_raw = gpio_efinix_sapphire_port_get_raw, + .port_set_masked_raw = gpio_efinix_sapphire_port_set_masked_raw, + .port_set_bits_raw = gpio_efinix_sapphire_port_set_bits_raw, + .port_clear_bits_raw = gpio_efinix_sapphire_port_clear_bits_raw, + .port_toggle_bits = gpio_efinix_sapphire_port_toggle_bits, +}; + +#define GPIO_EFINIX_SAPPHIRE_INIT(n) \ + static struct gpio_efinix_sapphire_cfg gpio_efinix_sapphire_cfg_##n = { \ + .base_addr = DT_INST_REG_ADDR(n), \ + .n_gpios = DT_INST_PROP(n, ngpios), \ +}; \ +static struct gpio_efinix_sapphire_data gpio_efinix_sapphire_data_##n; \ + DEVICE_DT_INST_DEFINE(n, \ + gpio_efinix_sapphire_init, \ + NULL, \ + &gpio_efinix_sapphire_data_##n, \ + &gpio_efinix_sapphire_cfg_##n, \ + POST_KERNEL, \ + CONFIG_GPIO_INIT_PRIORITY, \ + &gpio_efinix_sapphire_api \ + ); \ + +DT_INST_FOREACH_STATUS_OKAY(GPIO_EFINIX_SAPPHIRE_INIT) diff --git a/drivers/gpio/gpio_efinix_sapphire_priv.h b/drivers/gpio/gpio_efinix_sapphire_priv.h new file mode 100644 index 0000000000000..697adc63aa769 --- /dev/null +++ b/drivers/gpio/gpio_efinix_sapphire_priv.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2023 Efinix Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_GPIO_EFINIX_SAPPHIRE_PRIV_H_ +#define ZEPHYR_DRIVERS_GPIO_EFINIX_SAPPHIRE_PRIV_H_ + +#define BSP_GPIO_INPUT 0x00 +#define BSP_GPIO_OUTPUT 0x04 +#define BSP_GPIO_OUTPUT_ENABLE 0x08 +#define BSP_GPIO_INTERRUPT_RISE_ENABLE 0x20 +#define BSP_GPIO_INTERRUPT_FALL_ENABLE 0x24 +#define BSP_GPIO_INTERRUPT_HIGH_ENABLE 0x28 +#define BSP_GPIO_INTERRUPT_LOW_ENABLE 0x2c + + +#endif /* ZEPHYR_DRIVERS_GPIO_EFINIX_SAPPHIRE_PRIV_H_ */ diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index fcbfd6b079a18..4478ee47442e8 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -59,6 +59,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_CDNS uart_cdns.c) zephyr_library_sources_ifdef(CONFIG_UART_OPENTITAN uart_opentitan.c) zephyr_library_sources_ifdef(CONFIG_UART_HOSTLINK uart_hostlink.c) zephyr_library_sources_ifdef(CONFIG_UART_EMUL uart_emul.c) +zephyr_library_sources_ifdef(CONFIG_UART_EFINIX_SAPPIHIRE uart_efinix_sapphire.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 38ab4a9e41557..b3a876eb6d101 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -218,4 +218,6 @@ source "drivers/serial/Kconfig.hostlink" source "drivers/serial/Kconfig.emul" +source "drivers/serial/Kconfig.efinix_sapphire" + endif # SERIAL diff --git a/drivers/serial/Kconfig.efinix_sapphire b/drivers/serial/Kconfig.efinix_sapphire new file mode 100644 index 0000000000000..860ad80020b1c --- /dev/null +++ b/drivers/serial/Kconfig.efinix_sapphire @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +config UART_EFINIX_SAPPIHIRE + bool "EFINIX_SAPPIHIRE serial driver" + default y + depends on DT_HAS_EFINIX_SAPPHIRE_UART0_ENABLED + select SERIAL_HAS_DRIVER + help + This option enables Efinix sapphire serial driver. diff --git a/drivers/serial/uart_efinix_sapphire.c b/drivers/serial/uart_efinix_sapphire.c new file mode 100644 index 0000000000000..f3f19d2116f29 --- /dev/null +++ b/drivers/serial/uart_efinix_sapphire.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2023 Efinix Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT efinix_sapphire_uart0 + +#include "uart_efinix_sapphire_priv.h" +#include +#include +#include +#include +#include + + +#define UART_IRQ DT_INST_IRQN(0) +#define UART0_BASE_ADDR DT_INST_REG_ADDR(0) + +#define UART0_DATA_REG_ADDR UART0_BASE_ADDR + BSP_UART_DATA +#define UART0_STATUS_REG_ADDR UART0_BASE_ADDR + BSP_UART_STATUS +#define UART0_CLOCK_REG_ADDR UART0_BASE_ADDR + BSP_UART_CLOCK_DIVIDER +#define UART0_FRAME_REG_ADDR UART0_BASE_ADDR + BSP_UART_FRAME_CONFIG + +#define UART0_SAMPLE_PER_BAUD 8 +#define UART0_PARITY 0 /* Off */ +#define UART0_STOP 0 /* 1 stop bit */ + +struct uart_efinix_sapphire_config { + uint32_t baudrate; +}; + +static void uart_efinix_sapphire_poll_out(const struct device *dev, unsigned char c) +{ + /* uart_writeAvailability */ + while ((sys_read32(UART0_STATUS_REG_ADDR) & BSP_UART_WRITE_AVAILABILITY_MASK) == 0) { + } + + sys_write8(c, UART0_DATA_REG_ADDR); +} + +static int uart_efinix_sapphire_poll_in(const struct device *dev, unsigned char *c) +{ + + if ((sys_read32(UART0_STATUS_REG_ADDR) & BSP_UART_READ_OCCUPANCY_MASK) != 0) { + *c = (unsigned char)sys_read8(UART0_DATA_REG_ADDR); + return 0; + } + + return -1; +} + +static const struct uart_driver_api uart_efinix_sapphire_api = { + .poll_in = uart_efinix_sapphire_poll_in, + .poll_out = uart_efinix_sapphire_poll_out, + .err_check = NULL, +}; + +static const struct uart_efinix_sapphire_config uart_efinix_sapphire_cfg_0 = { + .baudrate = DT_INST_PROP(0, current_speed), +}; + +static int uart_efinix_sapphire_init(const struct device *dev) +{ + ARG_UNUSED(dev); + + uint32_t prescaler = ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / + (uart_efinix_sapphire_cfg_0.baudrate * UART0_SAMPLE_PER_BAUD)) - + 1) & + 0xFFFFF; + sys_write32(prescaler, UART0_CLOCK_REG_ADDR); + + /* 8 data bits, no parity, 1 stop bit */ + uint32_t frame_config = (UART0_SAMPLE_PER_BAUD - 1) | UART0_PARITY << 8 | UART0_STOP << 16; + + sys_write32(frame_config, UART0_FRAME_REG_ADDR); + + return 0; +} + +/* Device tree instance 0 init */ +DEVICE_DT_INST_DEFINE(0, uart_efinix_sapphire_init, NULL, NULL, &uart_efinix_sapphire_cfg_0, + PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, (void *)&uart_efinix_sapphire_api); diff --git a/drivers/serial/uart_efinix_sapphire_priv.h b/drivers/serial/uart_efinix_sapphire_priv.h new file mode 100644 index 0000000000000..796ec1a947759 --- /dev/null +++ b/drivers/serial/uart_efinix_sapphire_priv.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2023 Efinix Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __UART_EFINIX_SAPPHIRE_PRIV_H__ +#define __UART_EFINIX_SAPPHIRE_PRIV_H__ + +#define BSP_UART_DATA 0x00 +#define BSP_UART_STATUS 0x04 +#define BSP_UART_CLOCK_DIVIDER 0x08 +#define BSP_UART_FRAME_CONFIG 0x0C + +#define BSP_UART_WRITE_AVAILABILITY_MASK GENMASK(23, 16) +#define BSP_UART_READ_OCCUPANCY_MASK GENMASK(31, 24) + +#endif /* __UART_EFINIX_SAPPHIRE_PRIV_H__ */ diff --git a/dts/bindings/gpio/efinix,sapphire-gpio.yaml b/dts/bindings/gpio/efinix,sapphire-gpio.yaml new file mode 100644 index 0000000000000..24808c1cec882 --- /dev/null +++ b/dts/bindings/gpio/efinix,sapphire-gpio.yaml @@ -0,0 +1,19 @@ +description: Efinix Sapphire GPIO + +compatible: "efinix,sapphire-gpio" + +include: [gpio-controller.yaml, base.yaml] + +properties: + reg: + required: true + + ngpios: + required: true + + "#gpio-cells": + const: 2 + +gpio-cells: + - pin + - flags diff --git a/dts/bindings/serial/efinix,sapphire-uart0.yaml b/dts/bindings/serial/efinix,sapphire-uart0.yaml new file mode 100644 index 0000000000000..87c675dd9efc1 --- /dev/null +++ b/dts/bindings/serial/efinix,sapphire-uart0.yaml @@ -0,0 +1,9 @@ +description: Efinix Sapphire UART + +compatible: "efinix,sapphire-uart0" + +include: uart-controller.yaml + +properties: + reg: + required: true diff --git a/dts/bindings/timer/efinix-sapphire,timer0.yaml b/dts/bindings/timer/efinix-sapphire,timer0.yaml new file mode 100644 index 0000000000000..42acf89adf0f6 --- /dev/null +++ b/dts/bindings/timer/efinix-sapphire,timer0.yaml @@ -0,0 +1,12 @@ +description: Efinix Sapphire timer + +compatible: "efinix,sapphire-timer0" + +include: base.yaml + +properties: + reg: + required: true + + interrupts: + required: true diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index dd01c5b57a6e6..5ffc6bb4a9aa2 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -173,6 +173,7 @@ ebv EBV Elektronik eckelmann Eckelmann AG edt Emerging Display Technologies eeti eGalax_eMPIA Technology Inc +efinix Efinix Inc einfochips Einfochips elan Elan Microelectronic Corp. element14 Element14 (A Premier Farnell Company) diff --git a/dts/riscv/efinix/sapphire_soc.dtsi b/dts/riscv/efinix/sapphire_soc.dtsi new file mode 100644 index 0000000000000..c61eec170ed67 --- /dev/null +++ b/dts/riscv/efinix/sapphire_soc.dtsi @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2023 Efinix Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "efinix,sapphire"; + compatible = "efinix,sapphire"; + + chosen { + zephyr,sram = &ram0; + }; + + ram0: memory@F9000000 { + device_type = "memory"; + reg = <0xF9000000 DT_SIZE_K(192)>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + clock-frequency = <100000000>; + compatible = "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa = "rv32imac"; + status = "okay"; + timebase-frequency = <100000000>; + + hlic: interrupt-controller { + compatible = "riscv,cpu-intc"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "efinix,sapphire"; + ranges; + + plic0: interrupt-controller@f8c00000 { + compatible = "sifive,plic-1.0.0"; + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&hlic 11>; + reg = < 0xf8c00000 0x00001000 + 0xf8c02000 0x00000800 + 0xf8e00000 0x00010000 >; + reg-names = "prio", "irq_en", "reg"; + riscv,max-priority = <3>; + riscv,ndev = <32>; + }; + + clint: clint@f8b00000 { + compatible = "sifive,clint0"; + interrupts-extended = <&hlic 3 &hlic 7>; + reg = <0xf8b00000 0x10000>; + }; + + timer0: timer@e0002800 { + compatible = "efinix,sapphire-timer0"; + reg = <0xe0002800 0x40>; + interrupt-parent = <&plic0>; + interrupts = <19 0>; + status = "disabled"; + }; + + gpio0: gpio@f8015000 { + compatible = "efinix,sapphire-gpio"; + reg = <0xf8015000 0x100>; + reg-names = "base"; + ngpios = <4>; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + uart0: uart@f8010000 { + compatible = "efinix,sapphire-uart0"; + interrupt-parent = <&plic0>; + interrupts = <1 1>; + reg = <0xf8010000 0x40>; + reg-names = "base"; + current-speed = <115200>; + status = "disabled"; + }; + + }; +}; diff --git a/soc/riscv/riscv-privilege/efinix-sapphire/CMakeLists.txt b/soc/riscv/riscv-privilege/efinix-sapphire/CMakeLists.txt new file mode 100644 index 0000000000000..9fc8063593792 --- /dev/null +++ b/soc/riscv/riscv-privilege/efinix-sapphire/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/riscv/riscv-privilege/efinix-sapphire/Kconfig.defconfig.series b/soc/riscv/riscv-privilege/efinix-sapphire/Kconfig.defconfig.series new file mode 100644 index 0000000000000..233428931a38c --- /dev/null +++ b/soc/riscv/riscv-privilege/efinix-sapphire/Kconfig.defconfig.series @@ -0,0 +1,30 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFINIX_SAPPHIRE + +config SOC_SERIES + default "efinix-sapphire" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 100000000 + +config RISCV_HAS_CPU_IDLE + bool + +config RISCV_SOC_INTERRUPT_INIT + bool + default y + +config RISCV_HAS_PLIC + bool + default y + +config NUM_IRQS + int + default 36 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +endif # SOC_SERIES_EFINIX_SAPPHIRE diff --git a/soc/riscv/riscv-privilege/efinix-sapphire/Kconfig.series b/soc/riscv/riscv-privilege/efinix-sapphire/Kconfig.series new file mode 100644 index 0000000000000..8c8b3cbf4b130 --- /dev/null +++ b/soc/riscv/riscv-privilege/efinix-sapphire/Kconfig.series @@ -0,0 +1,9 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFINIX_SAPPHIRE + bool "Efinix Sapphire SOC implementation" + select RISCV + select SOC_FAMILY_RISCV_PRIVILEGE + help + Enable support for Efinix Sapphire SOC implementation diff --git a/soc/riscv/riscv-privilege/efinix-sapphire/Kconfig.soc b/soc/riscv/riscv-privilege/efinix-sapphire/Kconfig.soc new file mode 100644 index 0000000000000..1a6119b186969 --- /dev/null +++ b/soc/riscv/riscv-privilege/efinix-sapphire/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "Efinix SoC selection" + depends on SOC_SERIES_EFINIX_SAPPHIRE + +config SOC_RISCV32_EFINIX_SAPPHIRE + bool "Efinix Sapphire VexRiscv system implementation" + select ATOMIC_OPERATIONS_C + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + +endchoice diff --git a/soc/riscv/riscv-privilege/efinix-sapphire/linker.ld b/soc/riscv/riscv-privilege/efinix-sapphire/linker.ld new file mode 100644 index 0000000000000..4cfd67a53f500 --- /dev/null +++ b/soc/riscv/riscv-privilege/efinix-sapphire/linker.ld @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +#include diff --git a/soc/riscv/riscv-privilege/efinix-sapphire/soc.h b/soc/riscv/riscv-privilege/efinix-sapphire/soc.h new file mode 100644 index 0000000000000..e061756622639 --- /dev/null +++ b/soc/riscv/riscv-privilege/efinix-sapphire/soc.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2023 Efinix Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __RISCV32_EFINIX_SAPPHIRE_SOC_H_ +#define __RISCV32_EFINIX_SAPPHIRE_SOC_H_ + +#include "soc_common.h" +#include +#include + +#ifndef _ASMLANGUAGE + +#endif /* _ASMLANGUAGE */ + +#endif /* __RISCV32_EFINIX_SAPPHIRE_SOC_H_ */