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tcg/s390x: Implement vector shift operations
Reviewed-by: David Hildenbrand <[email protected]> Signed-off-by: Richard Henderson <[email protected]>
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3 files changed

+99
-7
lines changed

3 files changed

+99
-7
lines changed

‎tcg/s390x/tcg-target-con-set.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ C_O1_I2(r, 0, rI)
2424
C_O1_I2(r, 0, rJ)
2525
C_O1_I2(r, r, ri)
2626
C_O1_I2(r, rZ, r)
27+
C_O1_I2(v, v, r)
2728
C_O1_I2(v, v, v)
2829
C_O1_I4(r, r, ri, r, 0)
2930
C_O1_I4(r, r, ri, rI, 0)

‎tcg/s390x/tcg-target.c.inc‎

Lines changed: 92 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -277,6 +277,10 @@ typedef enum S390Opcode {
277277
VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */
278278
VRRc_VCH = 0xe7fb, /* " */
279279
VRRc_VCHL = 0xe7f9, /* " */
280+
VRRc_VERLLV = 0xe773,
281+
VRRc_VESLV = 0xe770,
282+
VRRc_VESRAV = 0xe77a,
283+
VRRc_VESRLV = 0xe778,
280284
VRRc_VML = 0xe7a2,
281285
VRRc_VN = 0xe768,
282286
VRRc_VNC = 0xe769,
@@ -287,6 +291,10 @@ typedef enum S390Opcode {
287291
VRRc_VX = 0xe76d,
288292
VRRf_VLVGP = 0xe762,
289293

294+
VRSa_VERLL = 0xe733,
295+
VRSa_VESL = 0xe730,
296+
VRSa_VESRA = 0xe73a,
297+
VRSa_VESRL = 0xe738,
290298
VRSb_VLVG = 0xe722,
291299
VRSc_VLGV = 0xe721,
292300

@@ -643,6 +651,18 @@ static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op,
643651
tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0));
644652
}
645653

654+
static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1,
655+
intptr_t d2, TCGReg b2, TCGReg v3, int m4)
656+
{
657+
tcg_debug_assert(is_vector_reg(v1));
658+
tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
659+
tcg_debug_assert(is_general_reg(b2));
660+
tcg_debug_assert(is_vector_reg(v3));
661+
tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf));
662+
tcg_out16(s, b2 << 12 | d2);
663+
tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12));
664+
}
665+
646666
static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1,
647667
intptr_t d2, TCGReg b2, TCGReg r3, int m4)
648668
{
@@ -2710,6 +2730,43 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
27102730
tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
27112731
break;
27122732

2733+
case INDEX_op_shli_vec:
2734+
tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece);
2735+
break;
2736+
case INDEX_op_shri_vec:
2737+
tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece);
2738+
break;
2739+
case INDEX_op_sari_vec:
2740+
tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece);
2741+
break;
2742+
case INDEX_op_rotli_vec:
2743+
tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece);
2744+
break;
2745+
case INDEX_op_shls_vec:
2746+
tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece);
2747+
break;
2748+
case INDEX_op_shrs_vec:
2749+
tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece);
2750+
break;
2751+
case INDEX_op_sars_vec:
2752+
tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece);
2753+
break;
2754+
case INDEX_op_rotls_vec:
2755+
tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece);
2756+
break;
2757+
case INDEX_op_shlv_vec:
2758+
tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece);
2759+
break;
2760+
case INDEX_op_shrv_vec:
2761+
tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece);
2762+
break;
2763+
case INDEX_op_sarv_vec:
2764+
tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece);
2765+
break;
2766+
case INDEX_op_rotlv_vec:
2767+
tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece);
2768+
break;
2769+
27132770
case INDEX_op_cmp_vec:
27142771
switch ((TCGCond)args[3]) {
27152772
case TCG_COND_EQ:
@@ -2744,10 +2801,23 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
27442801
case INDEX_op_not_vec:
27452802
case INDEX_op_or_vec:
27462803
case INDEX_op_orc_vec:
2804+
case INDEX_op_rotli_vec:
2805+
case INDEX_op_rotls_vec:
2806+
case INDEX_op_rotlv_vec:
2807+
case INDEX_op_sari_vec:
2808+
case INDEX_op_sars_vec:
2809+
case INDEX_op_sarv_vec:
2810+
case INDEX_op_shli_vec:
2811+
case INDEX_op_shls_vec:
2812+
case INDEX_op_shlv_vec:
2813+
case INDEX_op_shri_vec:
2814+
case INDEX_op_shrs_vec:
2815+
case INDEX_op_shrv_vec:
27472816
case INDEX_op_sub_vec:
27482817
case INDEX_op_xor_vec:
27492818
return 1;
27502819
case INDEX_op_cmp_vec:
2820+
case INDEX_op_rotrv_vec:
27512821
return -1;
27522822
case INDEX_op_mul_vec:
27532823
return vece < MO_64;
@@ -2810,7 +2880,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
28102880
TCGArg a0, ...)
28112881
{
28122882
va_list va;
2813-
TCGv_vec v0, v1, v2;
2883+
TCGv_vec v0, v1, v2, t0;
28142884

28152885
va_start(va, a0);
28162886
v0 = temp_tcgv_vec(arg_temp(a0));
@@ -2822,6 +2892,13 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
28222892
expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
28232893
break;
28242894

2895+
case INDEX_op_rotrv_vec:
2896+
t0 = tcg_temp_new_vec(type);
2897+
tcg_gen_neg_vec(vece, t0, v2);
2898+
tcg_gen_rotlv_vec(vece, v0, v1, t0);
2899+
tcg_temp_free_vec(t0);
2900+
break;
2901+
28252902
default:
28262903
g_assert_not_reached();
28272904
}
@@ -2978,6 +3055,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
29783055
case INDEX_op_abs_vec:
29793056
case INDEX_op_neg_vec:
29803057
case INDEX_op_not_vec:
3058+
case INDEX_op_rotli_vec:
3059+
case INDEX_op_sari_vec:
3060+
case INDEX_op_shli_vec:
3061+
case INDEX_op_shri_vec:
29813062
return C_O1_I1(v, v);
29823063
case INDEX_op_add_vec:
29833064
case INDEX_op_sub_vec:
@@ -2988,7 +3069,17 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
29883069
case INDEX_op_xor_vec:
29893070
case INDEX_op_cmp_vec:
29903071
case INDEX_op_mul_vec:
3072+
case INDEX_op_rotlv_vec:
3073+
case INDEX_op_rotrv_vec:
3074+
case INDEX_op_shlv_vec:
3075+
case INDEX_op_shrv_vec:
3076+
case INDEX_op_sarv_vec:
29913077
return C_O1_I2(v, v, v);
3078+
case INDEX_op_rotls_vec:
3079+
case INDEX_op_shls_vec:
3080+
case INDEX_op_shrs_vec:
3081+
case INDEX_op_sars_vec:
3082+
return C_O1_I2(v, v, r);
29923083

29933084
default:
29943085
g_assert_not_reached();

‎tcg/s390x/tcg-target.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -148,12 +148,12 @@ extern uint64_t s390_facilities[3];
148148
#define TCG_TARGET_HAS_not_vec 1
149149
#define TCG_TARGET_HAS_neg_vec 1
150150
#define TCG_TARGET_HAS_abs_vec 1
151-
#define TCG_TARGET_HAS_roti_vec 0
152-
#define TCG_TARGET_HAS_rots_vec 0
153-
#define TCG_TARGET_HAS_rotv_vec 0
154-
#define TCG_TARGET_HAS_shi_vec 0
155-
#define TCG_TARGET_HAS_shs_vec 0
156-
#define TCG_TARGET_HAS_shv_vec 0
151+
#define TCG_TARGET_HAS_roti_vec 1
152+
#define TCG_TARGET_HAS_rots_vec 1
153+
#define TCG_TARGET_HAS_rotv_vec 1
154+
#define TCG_TARGET_HAS_shi_vec 1
155+
#define TCG_TARGET_HAS_shs_vec 1
156+
#define TCG_TARGET_HAS_shv_vec 1
157157
#define TCG_TARGET_HAS_mul_vec 1
158158
#define TCG_TARGET_HAS_sat_vec 0
159159
#define TCG_TARGET_HAS_minmax_vec 0

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