@@ -141,6 +141,9 @@ typedef enum {
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INSN_CLZ = 0x016f0f10 ,
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INSN_RBIT = 0x06ff0f30 ,
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+ INSN_LDMIA = 0x08b00000 ,
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+ INSN_STMDB = 0x09200000 ,
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+
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INSN_LDR_IMM = 0x04100000 ,
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INSN_LDR_REG = 0x06100000 ,
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INSN_STR_IMM = 0x04000000 ,
@@ -593,6 +596,12 @@ static inline void tcg_out_dat_imm(TCGContext *s,
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(rn << 16 ) | (rd << 12 ) | im);
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}
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+ static void tcg_out_ldstm (TCGContext *s, int cond, int opc,
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+ TCGReg rn, uint16_t mask)
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+ {
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+ tcg_out32 (s, (cond << 28 ) | opc | (rn << 16 ) | mask);
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+ }
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+
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/* Note that this routine is used for both LDR and LDRH formats, so we do
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not wish to include an immediate shift at this point. */
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static void tcg_out_memop_r (TCGContext *s, int cond, ARMInsn opc, TCGReg rt,
@@ -3081,7 +3090,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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{
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/* Calling convention requires us to save r4-r11 and lr. */
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/* stmdb sp!, { r4 - r11, lr } */
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- tcg_out32 (s, (COND_AL << 28 ) | 0x092d4ff0 );
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+ tcg_out_ldstm (s, COND_AL, INSN_STMDB, TCG_REG_CALL_STACK,
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+ (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) |
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+ (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) |
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+ (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_R14));
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/* Reserve callee argument and tcg temp space. */
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tcg_out_dat_rI (s, COND_AL, ARITH_SUB, TCG_REG_CALL_STACK,
@@ -3109,7 +3121,10 @@ static void tcg_out_epilogue(TCGContext *s)
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TCG_REG_CALL_STACK, STACK_ADDEND, 1 );
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/* ldmia sp!, { r4 - r11, pc } */
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- tcg_out32 (s, (COND_AL << 28 ) | 0x08bd8ff0 );
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+ tcg_out_ldstm (s, COND_AL, INSN_LDMIA, TCG_REG_CALL_STACK,
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+ (1 << TCG_REG_R4) | (1 << TCG_REG_R5) | (1 << TCG_REG_R6) |
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+ (1 << TCG_REG_R7) | (1 << TCG_REG_R8) | (1 << TCG_REG_R9) |
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+ (1 << TCG_REG_R10) | (1 << TCG_REG_R11) | (1 << TCG_REG_PC));
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}
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typedef struct {
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