@@ -525,19 +525,19 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
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return 0 ;
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}
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- static inline void tcg_out_b (TCGContext *s, int cond, int32_t offset)
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+ static inline void tcg_out_b_imm (TCGContext *s, int cond, int32_t offset)
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{
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tcg_out32 (s, (cond << 28 ) | 0x0a000000 |
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(((offset - 8 ) >> 2 ) & 0x00ffffff ));
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}
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- static inline void tcg_out_bl (TCGContext *s, int cond, int32_t offset)
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+ static inline void tcg_out_bl_imm (TCGContext *s, int cond, int32_t offset)
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{
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tcg_out32 (s, (cond << 28 ) | 0x0b000000 |
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(((offset - 8 ) >> 2 ) & 0x00ffffff ));
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}
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- static inline void tcg_out_blx (TCGContext *s, int cond, int rn)
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+ static inline void tcg_out_blx_reg (TCGContext *s, int cond, int rn)
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{
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tcg_out32 (s, (cond << 28 ) | 0x012fff30 | rn);
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}
@@ -568,13 +568,19 @@ static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)
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}
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}
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- static inline void tcg_out_bx (TCGContext *s, int cond, TCGReg rn)
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+ static void tcg_out_bx_reg (TCGContext *s, int cond, TCGReg rn)
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{
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- /* Unless the C portion of QEMU is compiled as thumb, we don't
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- actually need true BX semantics; merely a branch to an address
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- held in a register. */
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+ tcg_out32 (s, (cond << 28 ) | 0x012fff10 | rn);
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+ }
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+
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+ static void tcg_out_b_reg (TCGContext *s, int cond, TCGReg rn)
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+ {
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+ /*
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+ * Unless the C portion of QEMU is compiled as thumb, we don't need
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+ * true BX semantics; merely a branch to an address held in a register.
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+ */
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if (use_armv5t_instructions) {
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- tcg_out32 (s, ( cond << 28 ) | 0x012fff10 | rn);
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+ tcg_out_bx_reg (s, cond, rn);
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} else {
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tcg_out_mov_reg (s, cond, TCG_REG_PC, rn);
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}
@@ -1215,7 +1221,7 @@ static void tcg_out_goto(TCGContext *s, int cond, const tcg_insn_unit *addr)
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ptrdiff_t disp = tcg_pcrel_diff (s, addr);
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if ((addri & 1 ) == 0 && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd ) {
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- tcg_out_b (s, cond, disp);
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+ tcg_out_b_imm (s, cond, disp);
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return ;
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}
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tcg_out_movi_pool (s, cond, TCG_REG_PC, addri);
@@ -1236,11 +1242,11 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *addr)
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}
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tcg_out_blx_imm (s, disp);
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} else {
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- tcg_out_bl (s, COND_AL, disp);
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+ tcg_out_bl_imm (s, COND_AL, disp);
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}
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} else if (use_armv7_instructions) {
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tcg_out_movi32 (s, COND_AL, TCG_REG_TMP, addri);
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- tcg_out_blx (s, COND_AL, TCG_REG_TMP);
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+ tcg_out_blx_reg (s, COND_AL, TCG_REG_TMP);
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} else {
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/* ??? Know that movi_pool emits exactly 1 insn. */
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tcg_out_dat_imm (s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0 );
@@ -1254,7 +1260,7 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l)
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tcg_out_goto (s, cond, l->u .value_ptr );
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} else {
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tcg_out_reloc (s, s->code_ptr , R_ARM_PC24, l, 0 );
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- tcg_out_b (s, cond, 0 );
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+ tcg_out_b_imm (s, cond, 0 );
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}
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}
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@@ -1823,7 +1829,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
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/* This a conditional BL only to load a pointer within this opcode into LR
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for the slow path. We will not be using the value for a tail call. */
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label_ptr = s->code_ptr ;
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- tcg_out_bl (s, COND_NE, 0 );
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+ tcg_out_bl_imm (s, COND_NE, 0 );
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tcg_out_qemu_ld_index (s, opc, datalo, datahi, addrlo, addend);
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@@ -1929,7 +1935,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
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/* The conditional call must come last, as we're going to return here. */
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label_ptr = s->code_ptr ;
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- tcg_out_bl (s, COND_NE, 0 );
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+ tcg_out_bl_imm (s, COND_NE, 0 );
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add_qemu_ldst_label (s, false , oi, datalo, datahi, addrlo, addrhi,
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s->code_ptr , label_ptr);
@@ -1982,7 +1988,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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}
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break ;
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case INDEX_op_goto_ptr:
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- tcg_out_bx (s, COND_AL, args[0 ]);
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+ tcg_out_b_reg (s, COND_AL, args[0 ]);
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break ;
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case INDEX_op_br:
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tcg_out_goto_label (s, COND_AL, arg_label (args[0 ]));
@@ -3066,7 +3072,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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tcg_out_mov (s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0 ]);
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- tcg_out_bx (s, COND_AL, tcg_target_call_iarg_regs[1 ]);
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+ tcg_out_b_reg (s, COND_AL, tcg_target_call_iarg_regs[1 ]);
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/*
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* Return path for goto_ptr. Set return value to 0, a-la exit_tb,
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