Skip to content

Commit 5acc270

Browse files
pm215pm215
committed
Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into staging
target/xtensa fixes for 5.1: - fix access to special registers missing in the core configuration; - fix simcall opcode behavior for new hardware; - drop gen_io_end call from xtensa translator. # gpg: Signature made Thu 25 Jun 2020 09:08:58 BST # gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044 # gpg: issuer "[email protected]" # gpg: Good signature from "Max Filippov <[email protected]>" [unknown] # gpg: aka "Max Filippov <[email protected]>" [full] # gpg: aka "Max Filippov <[email protected]>" [full] # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20200625-xtensa: target/xtensa: drop gen_io_end call target/xtensa: fix simcall for newer hardware target/xtensa: fetch HW version from configuration overlay target/xtensa: work around missing SR definitions Signed-off-by: Peter Maydell <[email protected]>
2 parents 63d2119 + 8a3a814 commit 5acc270

File tree

3 files changed

+46
-23
lines changed

3 files changed

+46
-23
lines changed

‎target/xtensa/cpu.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -464,6 +464,7 @@ struct XtensaConfig {
464464
XtensaMemory sysrom;
465465
XtensaMemory sysram;
466466

467+
unsigned hw_version;
467468
uint32_t configid[2];
468469

469470
void *isa_internal;

‎target/xtensa/overlay_tool.h‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -60,8 +60,9 @@
6060
#define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
6161
#endif
6262

63-
#ifndef XCHAL_HW_MIN_VERSION
64-
#define XCHAL_HW_MIN_VERSION 0
63+
#ifndef XCHAL_HW_VERSION
64+
#define XCHAL_HW_VERSION (XCHAL_HW_VERSION_MAJOR * 100 \
65+
+ XCHAL_HW_VERSION_MINOR)
6566
#endif
6667

6768
#ifndef XCHAL_LOOP_BUFFER_SIZE
@@ -100,7 +101,7 @@
100101
XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
101102
XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
102103
XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
103-
XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000) || \
104+
XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \
104105
XCHAL_HAVE_EXCLUSIVE), XTENSA_OPTION_ATOMCTL) | \
105106
XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
106107
/* Interrupts and exceptions */ \
@@ -498,6 +499,7 @@
498499
}
499500

500501
#define CONFIG_SECTION \
502+
.hw_version = XCHAL_HW_VERSION, \
501503
.configid = { \
502504
XCHAL_HW_CONFIGID0, \
503505
XCHAL_HW_CONFIGID1, \

‎target/xtensa/translate.c‎

Lines changed: 40 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -595,9 +595,6 @@ static int gen_postprocess(DisasContext *dc, int slot)
595595
gen_io_start();
596596
}
597597
gen_helper_check_interrupts(cpu_env);
598-
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
599-
gen_io_end();
600-
}
601598
}
602599
#endif
603600
if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) {
@@ -2191,7 +2188,11 @@ static void translate_rsil(DisasContext *dc, const OpcodeArg arg[],
21912188
static void translate_rsr(DisasContext *dc, const OpcodeArg arg[],
21922189
const uint32_t par[])
21932190
{
2194-
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2191+
if (sr_name[par[0]]) {
2192+
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2193+
} else {
2194+
tcg_gen_movi_i32(arg[0].out, 0);
2195+
}
21952196
}
21962197

21972198
static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[],
@@ -2363,9 +2364,10 @@ static bool test_ill_simcall(DisasContext *dc, const OpcodeArg arg[],
23632364
#ifdef CONFIG_USER_ONLY
23642365
bool ill = true;
23652366
#else
2366-
bool ill = !semihosting_enabled();
2367+
/* Between RE.2 and RE.3 simcall opcode's become nop for the hardware. */
2368+
bool ill = dc->config->hw_version <= 250002 && !semihosting_enabled();
23672369
#endif
2368-
if (ill) {
2370+
if (ill || !semihosting_enabled()) {
23692371
qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
23702372
}
23712373
return ill;
@@ -2375,7 +2377,9 @@ static void translate_simcall(DisasContext *dc, const OpcodeArg arg[],
23752377
const uint32_t par[])
23762378
{
23772379
#ifndef CONFIG_USER_ONLY
2378-
gen_helper_simcall(cpu_env);
2380+
if (semihosting_enabled()) {
2381+
gen_helper_simcall(cpu_env);
2382+
}
23792383
#endif
23802384
}
23812385

@@ -2563,13 +2567,17 @@ static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[],
25632567
static void translate_wsr(DisasContext *dc, const OpcodeArg arg[],
25642568
const uint32_t par[])
25652569
{
2566-
tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
2570+
if (sr_name[par[0]]) {
2571+
tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in);
2572+
}
25672573
}
25682574

25692575
static void translate_wsr_mask(DisasContext *dc, const OpcodeArg arg[],
25702576
const uint32_t par[])
25712577
{
2572-
tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]);
2578+
if (sr_name[par[0]]) {
2579+
tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]);
2580+
}
25732581
}
25742582

25752583
static void translate_wsr_acchi(DisasContext *dc, const OpcodeArg arg[],
@@ -2775,23 +2783,31 @@ static void translate_xor(DisasContext *dc, const OpcodeArg arg[],
27752783
static void translate_xsr(DisasContext *dc, const OpcodeArg arg[],
27762784
const uint32_t par[])
27772785
{
2778-
TCGv_i32 tmp = tcg_temp_new_i32();
2786+
if (sr_name[par[0]]) {
2787+
TCGv_i32 tmp = tcg_temp_new_i32();
27792788

2780-
tcg_gen_mov_i32(tmp, arg[0].in);
2781-
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2782-
tcg_gen_mov_i32(cpu_SR[par[0]], tmp);
2783-
tcg_temp_free(tmp);
2789+
tcg_gen_mov_i32(tmp, arg[0].in);
2790+
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2791+
tcg_gen_mov_i32(cpu_SR[par[0]], tmp);
2792+
tcg_temp_free(tmp);
2793+
} else {
2794+
tcg_gen_movi_i32(arg[0].out, 0);
2795+
}
27842796
}
27852797

27862798
static void translate_xsr_mask(DisasContext *dc, const OpcodeArg arg[],
27872799
const uint32_t par[])
27882800
{
2789-
TCGv_i32 tmp = tcg_temp_new_i32();
2801+
if (sr_name[par[0]]) {
2802+
TCGv_i32 tmp = tcg_temp_new_i32();
27902803

2791-
tcg_gen_mov_i32(tmp, arg[0].in);
2792-
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2793-
tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);
2794-
tcg_temp_free(tmp);
2804+
tcg_gen_mov_i32(tmp, arg[0].in);
2805+
tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]);
2806+
tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]);
2807+
tcg_temp_free(tmp);
2808+
} else {
2809+
tcg_gen_movi_i32(arg[0].out, 0);
2810+
}
27952811
}
27962812

27972813
static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[],
@@ -2819,7 +2835,11 @@ static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[],
28192835
{ \
28202836
TCGv_i32 tmp = tcg_temp_new_i32(); \
28212837
\
2822-
tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
2838+
if (sr_name[par[0]]) { \
2839+
tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
2840+
} else { \
2841+
tcg_gen_movi_i32(tmp, 0); \
2842+
} \
28232843
translate_wsr_##name(dc, arg, par); \
28242844
tcg_gen_mov_i32(arg[0].out, tmp); \
28252845
tcg_temp_free(tmp); \

0 commit comments

Comments
 (0)