Skip to content

Commit 5ffcb33

Browse files
rth7680rth7680
committed
target/alpha: Reorg integer memory operations
Pass in the MemOp instead of a callback. Drop the fp argument; add a locked argument. Reviewed-by: Peter Maydell <[email protected]> Signed-off-by: Richard Henderson <[email protected]>
1 parent 4526353 commit 5ffcb33

File tree

1 file changed

+40
-64
lines changed

1 file changed

+40
-64
lines changed

‎target/alpha/translate.c‎

Lines changed: 40 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -308,27 +308,10 @@ static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
308308
}
309309
}
310310

311-
static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
311+
static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
312+
MemOp op, bool clear, bool locked)
312313
{
313-
tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL);
314-
tcg_gen_mov_i64(cpu_lock_addr, t1);
315-
tcg_gen_mov_i64(cpu_lock_value, t0);
316-
}
317-
318-
static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)
319-
{
320-
tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LEQ);
321-
tcg_gen_mov_i64(cpu_lock_addr, t1);
322-
tcg_gen_mov_i64(cpu_lock_value, t0);
323-
}
324-
325-
static inline void gen_load_mem(DisasContext *ctx,
326-
void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1,
327-
int flags),
328-
int ra, int rb, int32_t disp16, bool fp,
329-
bool clear)
330-
{
331-
TCGv tmp, addr, va;
314+
TCGv addr, dest;
332315

333316
/* LDQ_U with ra $31 is UNOP. Other various loads are forms of
334317
prefetches, which we can treat as nops. No worries about
@@ -337,22 +320,20 @@ static inline void gen_load_mem(DisasContext *ctx,
337320
return;
338321
}
339322

340-
tmp = tcg_temp_new();
341-
addr = load_gpr(ctx, rb);
342-
343-
if (disp16) {
344-
tcg_gen_addi_i64(tmp, addr, disp16);
345-
addr = tmp;
346-
}
323+
addr = tcg_temp_new();
324+
tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
347325
if (clear) {
348-
tcg_gen_andi_i64(tmp, addr, ~0x7);
349-
addr = tmp;
326+
tcg_gen_andi_i64(addr, addr, ~0x7);
350327
}
351328

352-
va = (fp ? cpu_fir[ra] : ctx->ir[ra]);
353-
tcg_gen_qemu_load(va, addr, ctx->mem_idx);
329+
dest = ctx->ir[ra];
330+
tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, op);
354331

355-
tcg_temp_free(tmp);
332+
if (locked) {
333+
tcg_gen_mov_i64(cpu_lock_addr, addr);
334+
tcg_gen_mov_i64(cpu_lock_value, dest);
335+
}
336+
tcg_temp_free(addr);
356337
}
357338

358339
static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr)
@@ -393,30 +374,21 @@ static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
393374
tcg_temp_free(addr);
394375
}
395376

396-
static inline void gen_store_mem(DisasContext *ctx,
397-
void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
398-
int flags),
399-
int ra, int rb, int32_t disp16, bool fp,
400-
bool clear)
377+
static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
378+
MemOp op, bool clear)
401379
{
402-
TCGv tmp, addr, va;
403-
404-
tmp = tcg_temp_new();
405-
addr = load_gpr(ctx, rb);
380+
TCGv addr, src;
406381

407-
if (disp16) {
408-
tcg_gen_addi_i64(tmp, addr, disp16);
409-
addr = tmp;
410-
}
382+
addr = tcg_temp_new();
383+
tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
411384
if (clear) {
412-
tcg_gen_andi_i64(tmp, addr, ~0x7);
413-
addr = tmp;
385+
tcg_gen_andi_i64(addr, addr, ~0x7);
414386
}
415387

416-
va = (fp ? load_fpr(ctx, ra) : load_gpr(ctx, ra));
417-
tcg_gen_qemu_store(va, addr, ctx->mem_idx);
388+
src = load_gpr(ctx, ra);
389+
tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, op);
418390

419-
tcg_temp_free(tmp);
391+
tcg_temp_free(addr);
420392
}
421393

422394
static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,
@@ -1511,30 +1483,30 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
15111483
case 0x0A:
15121484
/* LDBU */
15131485
REQUIRE_AMASK(BWX);
1514-
gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0);
1486+
gen_load_int(ctx, ra, rb, disp16, MO_UB, 0, 0);
15151487
break;
15161488
case 0x0B:
15171489
/* LDQ_U */
1518-
gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1);
1490+
gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 1, 0);
15191491
break;
15201492
case 0x0C:
15211493
/* LDWU */
15221494
REQUIRE_AMASK(BWX);
1523-
gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0);
1495+
gen_load_int(ctx, ra, rb, disp16, MO_LEUW, 0, 0);
15241496
break;
15251497
case 0x0D:
15261498
/* STW */
15271499
REQUIRE_AMASK(BWX);
1528-
gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0);
1500+
gen_store_int(ctx, ra, rb, disp16, MO_LEUW, 0);
15291501
break;
15301502
case 0x0E:
15311503
/* STB */
15321504
REQUIRE_AMASK(BWX);
1533-
gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0);
1505+
gen_store_int(ctx, ra, rb, disp16, MO_UB, 0);
15341506
break;
15351507
case 0x0F:
15361508
/* STQ_U */
1537-
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1);
1509+
gen_store_int(ctx, ra, rb, disp16, MO_LEQ, 1);
15381510
break;
15391511

15401512
case 0x10:
@@ -2489,11 +2461,15 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
24892461
break;
24902462
case 0x2:
24912463
/* Longword physical access with lock (hw_ldl_l/p) */
2492-
gen_qemu_ldl_l(va, addr, MMU_PHYS_IDX);
2464+
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL);
2465+
tcg_gen_mov_i64(cpu_lock_addr, addr);
2466+
tcg_gen_mov_i64(cpu_lock_value, va);
24932467
break;
24942468
case 0x3:
24952469
/* Quadword physical access with lock (hw_ldq_l/p) */
2496-
gen_qemu_ldq_l(va, addr, MMU_PHYS_IDX);
2470+
tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEQ);
2471+
tcg_gen_mov_i64(cpu_lock_addr, addr);
2472+
tcg_gen_mov_i64(cpu_lock_value, va);
24972473
break;
24982474
case 0x4:
24992475
/* Longword virtual PTE fetch (hw_ldl/v) */
@@ -2846,27 +2822,27 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
28462822
break;
28472823
case 0x28:
28482824
/* LDL */
2849-
gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0);
2825+
gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 0);
28502826
break;
28512827
case 0x29:
28522828
/* LDQ */
2853-
gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0);
2829+
gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 0, 0);
28542830
break;
28552831
case 0x2A:
28562832
/* LDL_L */
2857-
gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0);
2833+
gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 1);
28582834
break;
28592835
case 0x2B:
28602836
/* LDQ_L */
2861-
gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0);
2837+
gen_load_int(ctx, ra, rb, disp16, MO_LEQ, 0, 1);
28622838
break;
28632839
case 0x2C:
28642840
/* STL */
2865-
gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0);
2841+
gen_store_int(ctx, ra, rb, disp16, MO_LEUL, 0);
28662842
break;
28672843
case 0x2D:
28682844
/* STQ */
2869-
gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0);
2845+
gen_store_int(ctx, ra, rb, disp16, MO_LEQ, 0);
28702846
break;
28712847
case 0x2E:
28722848
/* STL_C */

0 commit comments

Comments
 (0)