target/riscv: Fix the range of pmpcfg of CSR funcion table

zongbox · alistair23 · commit 8ba26b0b2b00 · 2020-07-22T09:41:36.000-07:00
The range of Physical Memory Protection should be from CSR_PMPCFG0
to CSR_PMPCFG3, not to CSR_PMPADDR9.

Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bin.meng@windriver.com&gt;
Message-Id: &lt;eae49e9252c9596e4f3bdb471772f79235141a87.1595335112.git.zong.li@sifive.com&gt;
Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
@@ -1353,7 +1353,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MTINST] =              { hmode,   read_mtinst,      write_mtinst     },
 
     /* Physical Memory Protection */
-    [CSR_PMPCFG0  ... CSR_PMPADDR9] =  { pmp,   read_pmpcfg,  write_pmpcfg   },
+    [CSR_PMPCFG0  ... CSR_PMPCFG3]   = { pmp,   read_pmpcfg,  write_pmpcfg   },
     [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp,   read_pmpaddr, write_pmpaddr  },
 
     /* Performance Counters */
