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hw/intc: GICv3 ITS Feature enablement
Added properties to enable ITS feature and define qemu system address space memory in gicv3 common,setup distributor and redistributor registers to indicate LPI support. Signed-off-by: Shashi Mallela <[email protected]> Reviewed-by: Peter Maydell <[email protected]> Tested-by: Neil Armstrong <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
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+28
-4
lines changed

5 files changed

+28
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lines changed

hw/intc/arm_gicv3_common.c

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -345,6 +345,11 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
345345
return;
346346
}
347347

348+
if (s->lpi_enable && !s->dma) {
349+
error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not set");
350+
return;
351+
}
352+
348353
s->cpu = g_new0(GICv3CPUState, s->num_cpu);
349354

350355
for (i = 0; i < s->num_cpu; i++) {
@@ -381,6 +386,10 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
381386
(1 << 24) |
382387
(i << 8) |
383388
(last << 4);
389+
390+
if (s->lpi_enable) {
391+
s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
392+
}
384393
}
385394
}
386395

@@ -494,9 +503,12 @@ static Property arm_gicv3_common_properties[] = {
494503
DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
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DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
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DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
506+
DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
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DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
498508
DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
499509
redist_region_count, qdev_prop_uint32, uint32_t),
510+
DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,
511+
MemoryRegion *),
500512
DEFINE_PROP_END_OF_LIST(),
501513
};
502514

hw/intc/arm_gicv3_dist.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -384,7 +384,9 @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
384384
* A3V == 1 (non-zero values of Affinity level 3 supported)
385385
* IDbits == 0xf (we support 16-bit interrupt identifiers)
386386
* DVIS == 0 (Direct virtual LPI injection not supported)
387-
* LPIS == 0 (LPIs not supported)
387+
* LPIS == 1 (LPIs are supported if affinity routing is enabled)
388+
* num_LPIs == 0b00000 (bits [15:11],Number of LPIs as indicated
389+
* by GICD_TYPER.IDbits)
388390
* MBIS == 0 (message-based SPIs not supported)
389391
* SecurityExtn == 1 if security extns supported
390392
* CPUNumber == 0 since for us ARE is always 1
@@ -399,6 +401,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
399401
bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
400402

401403
*data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
404+
(s->lpi_enable << GICD_TYPER_LPIS_SHIFT) |
402405
(0xf << 19) | itlinesnumber;
403406
return true;
404407
}

hw/intc/arm_gicv3_redist.c

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -248,10 +248,16 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
248248
case GICR_CTLR:
249249
/* For our implementation, GICR_TYPER.DPGS is 0 and so all
250250
* the DPG bits are RAZ/WI. We don't do anything asynchronously,
251-
* so UWP and RWP are RAZ/WI. And GICR_TYPER.LPIS is 0 (we don't
252-
* implement LPIs) so Enable_LPIs is RES0. So there are no writable
253-
* bits for us.
251+
* so UWP and RWP are RAZ/WI. GICR_TYPER.LPIS is 1 (we
252+
* implement LPIs) so Enable_LPIs is programmable.
254253
*/
254+
if (cs->gicr_typer & GICR_TYPER_PLPIS) {
255+
if (value & GICR_CTLR_ENABLE_LPIS) {
256+
cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS;
257+
} else {
258+
cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS;
259+
}
260+
}
255261
return MEMTX_OK;
256262
case GICR_STATUSR:
257263
/* RAZ/WI for our implementation */

hw/intc/gicv3_internal.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,8 @@
6868
#define GICD_CTLR_E1NWF (1U << 7)
6969
#define GICD_CTLR_RWP (1U << 31)
7070

71+
#define GICD_TYPER_LPIS_SHIFT 17
72+
7173
/* 16 bits EventId */
7274
#define GICD_TYPER_IDBITS 0xf
7375

include/hw/intc/arm_gicv3_common.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -221,6 +221,7 @@ struct GICv3State {
221221
uint32_t num_cpu;
222222
uint32_t num_irq;
223223
uint32_t revision;
224+
bool lpi_enable;
224225
bool security_extn;
225226
bool irq_reset_nonsecure;
226227
bool gicd_no_migration_shift_bug;

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