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tcg/s390x: Implement tcg_out_mov for vector types
Reviewed-by: David Hildenbrand <[email protected]> Signed-off-by: Richard Henderson <[email protected]>
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1 file changed

+68
-4
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tcg/s390x/tcg-target.c.inc

Lines changed: 68 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -265,6 +265,11 @@ typedef enum S390Opcode {
265265
RX_STC = 0x42,
266266
RX_STH = 0x40,
267267

268+
VRRa_VLR = 0xe756,
269+
270+
VRSb_VLVG = 0xe722,
271+
VRSc_VLGV = 0xe721,
272+
268273
VRX_VL = 0xe706,
269274
VRX_VLLEZ = 0xe704,
270275
VRX_VST = 0xe70e,
@@ -558,6 +563,39 @@ static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
558563
| ((v4 & 0x10) << (4 + 0));
559564
}
560565

566+
static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op,
567+
TCGReg v1, TCGReg v2, int m3)
568+
{
569+
tcg_debug_assert(is_vector_reg(v1));
570+
tcg_debug_assert(is_vector_reg(v2));
571+
tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf));
572+
tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12));
573+
}
574+
575+
static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1,
576+
intptr_t d2, TCGReg b2, TCGReg r3, int m4)
577+
{
578+
tcg_debug_assert(is_vector_reg(v1));
579+
tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
580+
tcg_debug_assert(is_general_reg(b2));
581+
tcg_debug_assert(is_general_reg(r3));
582+
tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r3);
583+
tcg_out16(s, b2 << 12 | d2);
584+
tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12));
585+
}
586+
587+
static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1,
588+
intptr_t d2, TCGReg b2, TCGReg v3, int m4)
589+
{
590+
tcg_debug_assert(is_general_reg(r1));
591+
tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
592+
tcg_debug_assert(is_general_reg(b2));
593+
tcg_debug_assert(is_vector_reg(v3));
594+
tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 0xf));
595+
tcg_out16(s, b2 << 12 | d2);
596+
tcg_out16(s, (op & 0x00ff) | RXB(0, 0, v3, 0) | (m4 << 12));
597+
}
598+
561599
static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1,
562600
TCGReg b2, TCGReg x2, intptr_t d2, int m3)
563601
{
@@ -591,12 +629,38 @@ static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
591629

592630
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
593631
{
594-
if (src != dst) {
595-
if (type == TCG_TYPE_I32) {
632+
if (src == dst) {
633+
return true;
634+
}
635+
switch (type) {
636+
case TCG_TYPE_I32:
637+
if (likely(is_general_reg(dst) && is_general_reg(src))) {
596638
tcg_out_insn(s, RR, LR, dst, src);
597-
} else {
598-
tcg_out_insn(s, RRE, LGR, dst, src);
639+
break;
640+
}
641+
/* fallthru */
642+
643+
case TCG_TYPE_I64:
644+
if (likely(is_general_reg(dst))) {
645+
if (likely(is_general_reg(src))) {
646+
tcg_out_insn(s, RRE, LGR, dst, src);
647+
} else {
648+
tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3);
649+
}
650+
break;
651+
} else if (is_general_reg(src)) {
652+
tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3);
653+
break;
599654
}
655+
/* fallthru */
656+
657+
case TCG_TYPE_V64:
658+
case TCG_TYPE_V128:
659+
tcg_out_insn(s, VRRa, VLR, dst, src, 0);
660+
break;
661+
662+
default:
663+
g_assert_not_reached();
600664
}
601665
return true;
602666
}

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