tcg/i386: Fix %r12 guest_base initialization

rth7680 · stsquad · commit cce743abbf39 · 2020-04-07T16:19:49.000+01:00
When %gs cannot be used, we use register offset addressing.
This path is almost never used, so it was clearly not tested.

Signed-off-by: Richard Henderson &lt;richard.henderson@linaro.org&gt;
Reviewed-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Tested-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
Message-Id: &lt;20200406174803.8192-1-richard.henderson@linaro.org&gt;
Signed-off-by: Alex Bennée &lt;alex.bennee@linaro.org&gt;
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
@@ -3737,7 +3737,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
         } else {
             /* Choose R12 because, as a base, it requires a SIB byte. */
             x86_guest_base_index = TCG_REG_R12;
-            tcg_out_mov(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base);
+            tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base);
             tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index);
         }
     }

Original file line number	Diff line number	Diff line change
`@@ -3737,7 +3737,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)`
`3737`	`3737`	`} else {`
`3738`	`3738`	`/* Choose R12 because, as a base, it requires a SIB byte. */`
`3739`	`3739`	`x86_guest_base_index = TCG_REG_R12;`
`3740`		`- tcg_out_mov(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base);`
	`3740`	`+ tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base);`
`3741`	`3741`	`tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index);`
`3742`	`3742`	`}`
`3743`	`3743`	`}`