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hw/mips/boston: Massage memory map information
Use memmap array to uinfy address of memory map. That would allow us reuse address information for FDT generation. Signed-off-by: Jiaxun Yang <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> [PMD: Use local 'regaddr' in gen_firmware(), fix coding style] Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Message-Id: <[email protected]>
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‎hw/mips/boston.c‎

Lines changed: 80 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -64,6 +64,44 @@ struct BostonState {
6464
hwaddr fdt_base;
6565
};
6666

67+
enum {
68+
BOSTON_LOWDDR,
69+
BOSTON_PCIE0,
70+
BOSTON_PCIE1,
71+
BOSTON_PCIE2,
72+
BOSTON_PCIE2_MMIO,
73+
BOSTON_CM,
74+
BOSTON_GIC,
75+
BOSTON_CDMM,
76+
BOSTON_CPC,
77+
BOSTON_PLATREG,
78+
BOSTON_UART,
79+
BOSTON_LCD,
80+
BOSTON_FLASH,
81+
BOSTON_PCIE1_MMIO,
82+
BOSTON_PCIE0_MMIO,
83+
BOSTON_HIGHDDR,
84+
};
85+
86+
static const MemMapEntry boston_memmap[] = {
87+
[BOSTON_LOWDDR] = { 0x0, 0x10000000 },
88+
[BOSTON_PCIE0] = { 0x10000000, 0x2000000 },
89+
[BOSTON_PCIE1] = { 0x12000000, 0x2000000 },
90+
[BOSTON_PCIE2] = { 0x14000000, 0x2000000 },
91+
[BOSTON_PCIE2_MMIO] = { 0x16000000, 0x100000 },
92+
[BOSTON_CM] = { 0x16100000, 0x20000 },
93+
[BOSTON_GIC] = { 0x16120000, 0x20000 },
94+
[BOSTON_CDMM] = { 0x16140000, 0x8000 },
95+
[BOSTON_CPC] = { 0x16200000, 0x8000 },
96+
[BOSTON_PLATREG] = { 0x17ffd000, 0x1000 },
97+
[BOSTON_UART] = { 0x17ffe000, 0x20 },
98+
[BOSTON_LCD] = { 0x17fff000, 0x8 },
99+
[BOSTON_FLASH] = { 0x18000000, 0x8000000 },
100+
[BOSTON_PCIE1_MMIO] = { 0x20000000, 0x20000000 },
101+
[BOSTON_PCIE0_MMIO] = { 0x40000000, 0x40000000 },
102+
[BOSTON_HIGHDDR] = { 0x80000000, 0x0 },
103+
};
104+
67105
enum boston_plat_reg {
68106
PLAT_FPGA_BUILD = 0x00,
69107
PLAT_CORE_CL = 0x04,
@@ -275,24 +313,24 @@ type_init(boston_register_types)
275313

276314
static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
277315
{
278-
const uint32_t cm_base = 0x16100000;
279-
const uint32_t gic_base = 0x16120000;
280-
const uint32_t cpc_base = 0x16200000;
316+
uint64_t regaddr;
281317

282318
/* Move CM GCRs */
283-
bl_gen_write_ulong(&p,
284-
cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS),
285-
cm_base);
319+
regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS),
320+
bl_gen_write_ulong(&p, regaddr,
321+
boston_memmap[BOSTON_CM].base);
286322

287323
/* Move & enable GIC GCRs */
288-
bl_gen_write_ulong(&p,
289-
cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS),
290-
gic_base | GCR_GIC_BASE_GICEN_MSK);
324+
regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
325+
+ GCR_GIC_BASE_OFS),
326+
bl_gen_write_ulong(&p, regaddr,
327+
boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK);
291328

292329
/* Move & enable CPC GCRs */
293-
bl_gen_write_ulong(&p,
294-
cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS),
295-
cpc_base | GCR_CPC_BASE_CPCEN_MSK);
330+
regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
331+
+ GCR_CPC_BASE_OFS),
332+
bl_gen_write_ulong(&p, regaddr,
333+
boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK);
296334

297335
/*
298336
* Setup argument registers to follow the UHI boot protocol:
@@ -333,8 +371,9 @@ static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
333371
ram_low_sz = MIN(256 * MiB, machine->ram_size);
334372
ram_high_sz = machine->ram_size - ram_low_sz;
335373
qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg",
336-
1, 0x00000000, 1, ram_low_sz,
337-
1, 0x90000000, 1, ram_high_sz);
374+
1, boston_memmap[BOSTON_LOWDDR].base, 1, ram_low_sz,
375+
1, boston_memmap[BOSTON_HIGHDDR].base + ram_low_sz,
376+
1, ram_high_sz);
338377

339378
fdt = g_realloc(fdt, fdt_totalsize(fdt));
340379
qemu_fdt_dumpdtb(fdt, fdt_sz);
@@ -438,11 +477,15 @@ static void boston_mach_init(MachineState *machine)
438477
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
439478

440479
flash = g_new(MemoryRegion, 1);
441-
memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB,
442-
&error_fatal);
443-
memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
480+
memory_region_init_rom(flash, NULL, "boston.flash",
481+
boston_memmap[BOSTON_FLASH].size, &error_fatal);
482+
memory_region_add_subregion_overlap(sys_mem,
483+
boston_memmap[BOSTON_FLASH].base,
484+
flash, 0);
444485

445-
memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0);
486+
memory_region_add_subregion_overlap(sys_mem,
487+
boston_memmap[BOSTON_HIGHDDR].base,
488+
machine->ram, 0);
446489

447490
ddr_low_alias = g_new(MemoryRegion, 1);
448491
memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr",
@@ -451,32 +494,41 @@ static void boston_mach_init(MachineState *machine)
451494
memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);
452495

453496
xilinx_pcie_init(sys_mem, 0,
454-
0x10000000, 32 * MiB,
455-
0x40000000, 1 * GiB,
497+
boston_memmap[BOSTON_PCIE0].base,
498+
boston_memmap[BOSTON_PCIE0].size,
499+
boston_memmap[BOSTON_PCIE0_MMIO].base,
500+
boston_memmap[BOSTON_PCIE0_MMIO].size,
456501
get_cps_irq(&s->cps, 2), false);
457502

458503
xilinx_pcie_init(sys_mem, 1,
459-
0x12000000, 32 * MiB,
460-
0x20000000, 512 * MiB,
504+
boston_memmap[BOSTON_PCIE1].base,
505+
boston_memmap[BOSTON_PCIE1].size,
506+
boston_memmap[BOSTON_PCIE1_MMIO].base,
507+
boston_memmap[BOSTON_PCIE1_MMIO].size,
461508
get_cps_irq(&s->cps, 1), false);
462509

463510
pcie2 = xilinx_pcie_init(sys_mem, 2,
464-
0x14000000, 32 * MiB,
465-
0x16000000, 1 * MiB,
511+
boston_memmap[BOSTON_PCIE2].base,
512+
boston_memmap[BOSTON_PCIE2].size,
513+
boston_memmap[BOSTON_PCIE2_MMIO].base,
514+
boston_memmap[BOSTON_PCIE2_MMIO].size,
466515
get_cps_irq(&s->cps, 0), true);
467516

468517
platreg = g_new(MemoryRegion, 1);
469518
memory_region_init_io(platreg, NULL, &boston_platreg_ops, s,
470-
"boston-platregs", 0x1000);
471-
memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0);
519+
"boston-platregs",
520+
boston_memmap[BOSTON_PLATREG].size);
521+
memory_region_add_subregion_overlap(sys_mem,
522+
boston_memmap[BOSTON_PLATREG].base, platreg, 0);
472523

473-
s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2,
524+
s->uart = serial_mm_init(sys_mem, boston_memmap[BOSTON_UART].base, 2,
474525
get_cps_irq(&s->cps, 3), 10000000,
475526
serial_hd(0), DEVICE_NATIVE_ENDIAN);
476527

477528
lcd = g_new(MemoryRegion, 1);
478529
memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8);
479-
memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0);
530+
memory_region_add_subregion_overlap(sys_mem,
531+
boston_memmap[BOSTON_LCD].base, lcd, 0);
480532

481533
chr = qemu_chr_new("lcd", "vc:320x240", NULL);
482534
qemu_chr_fe_init(&s->lcd_display, chr, NULL);

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