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target/xtensa: statically allocate xtensa_insnbufs in DisasContext
Rather than dynamically allocate, and risk failing to free when we longjmp out of the translator, allocate the maximum buffer size based on the maximum supported instruction length. Suggested-by: Richard Henderson <[email protected]> Signed-off-by: Max Filippov <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Tested-by: Richard Henderson <[email protected]>
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3 files changed

+6
-16
lines changed

3 files changed

+6
-16
lines changed

target/xtensa/cpu.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -213,6 +213,9 @@ enum {
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#define MEMCTL_IL0EN 0x1
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#define MAX_INSN_LENGTH 64
216+
#define MAX_INSNBUF_LENGTH \
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((MAX_INSN_LENGTH + sizeof(xtensa_insnbuf_word) - 1) / \
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sizeof(xtensa_insnbuf_word))
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#define MAX_INSN_SLOTS 32
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#define MAX_OPCODE_ARGS 16
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#define MAX_NAREG 64

target/xtensa/helper.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,7 @@ static void init_libisa(XtensaConfig *config)
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config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL);
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assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH);
99+
assert(xtensa_insnbuf_size(config->isa) <= MAX_INSNBUF_LENGTH);
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opcodes = xtensa_isa_num_opcodes(config->isa);
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formats = xtensa_isa_num_formats(config->isa);
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regfiles = xtensa_isa_num_regfiles(config->isa);

target/xtensa/translate.c

Lines changed: 2 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -72,8 +72,8 @@ struct DisasContext {
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unsigned cpenable;
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uint32_t op_flags;
75-
xtensa_insnbuf insnbuf;
76-
xtensa_insnbuf slotbuf;
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xtensa_insnbuf_word insnbuf[MAX_INSNBUF_LENGTH];
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xtensa_insnbuf_word slotbuf[MAX_INSNBUF_LENGTH];
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};
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static TCGv_i32 cpu_pc;
@@ -1173,16 +1173,6 @@ static void xtensa_tr_init_disas_context(DisasContextBase *dcbase,
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dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE;
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dc->callinc = ((tb_flags & XTENSA_TBFLAG_CALLINC_MASK) >>
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XTENSA_TBFLAG_CALLINC_SHIFT);
1176-
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/*
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* FIXME: This will leak when a failed instruction load or similar
1179-
* event causes us to longjump out of the translation loop and
1180-
* hence not clean-up in xtensa_tr_tb_stop
1181-
*/
1182-
if (dc->config->isa) {
1183-
dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa);
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dc->slotbuf = xtensa_insnbuf_alloc(dc->config->isa);
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}
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init_sar_tracker(dc);
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}
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@@ -1272,10 +1262,6 @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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reset_sar_tracker(dc);
1275-
if (dc->config->isa) {
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xtensa_insnbuf_free(dc->config->isa, dc->insnbuf);
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xtensa_insnbuf_free(dc->config->isa, dc->slotbuf);
1278-
}
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if (dc->icount) {
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tcg_temp_free(dc->next_icount);
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}

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