update compilation settings

* add flash clock definition on SDC
* add RF exp related clocks on SDC
* update bram function attributes

Author: marqs

ossc_pro.qsf

@@ -629,7 +629,7 @@ set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
 
 set_global_assignment -name SMART_RECOMPILE ON
 
-set_global_assignment -name SEED 1
+set_global_assignment -name SEED 2
 
 set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
 
@@ -667,4 +667,5 @@ set_global_assignment -name QIP_FILE rtl/lpm_mult_sl.qip
 set_global_assignment -name QIP_FILE rtl/dc_fifo_emif_wr.qip
 set_global_assignment -name QIP_FILE rtl/pll_sdp.qip
 set_global_assignment -name SIP_FILE rtl/pll_sdp.sip
+
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

ossc_pro.sdc

@@ -15,6 +15,7 @@ create_clock -period 5MHz -name bck_hdmirx [get_ports HDMIRX_I2S_BCK_i]
 
 if {$legacy_av_in} {
     create_clock -period 27MHz -name pclk_sdp [get_ports EXT_IO_A_io[0]]
+    create_clock -period 24.576MHz -name bck_extpcm [get_ports EXT_IO_B_io[12]]
 }
 
 create_generated_clock -source {sys_inst|pll_0|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin} -divide_by 2 -multiply_by 88 -duty_cycle 50.00 -name pll_0_vco {sys_inst|pll_0|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}
@@ -26,13 +27,16 @@ create_generated_clock -source {u_pll_sdp|pll_sdp_inst|altera_pll_i|general[0].g
 
 create_generated_clock -name sd_clk -divide_by 2 -source {sys_inst|pll_0|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} [get_pins sys:sys_inst|sdc_controller_top:sdc_controller_0|sdc_controller:sdc0|sd_clock_divider:clock_divider0|SD_CLK_O|q]
 
+create_generated_clock -name flash_clk -divide_by 2 -source {sys_inst|pll_0|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} [get_pins sys:sys_inst|sys_intel_generic_serial_flash_interface_top_0:intel_generic_serial_flash_interface_top_0|sys_intel_generic_serial_flash_interface_top_0_qspi_inf_inst:qspi_inf_inst|flash_clk_reg|q]
+
 # output clocks
 #set pclk_out_port [get_ports HDMITX_PCLK_o]
 set i2s_bck_out_port [get_ports HDMITX_I2S_BCK_o]
 #create_generated_clock -name pclk_out -master_clock pclk_isl -source [get_ports ISL_PCLK_i] -multiply_by 1 $pclk_out_port
 #create_generated_clock -name pclk_out -master_clock pclk_hdmirx -source [get_ports HDMIRX_PCLK_i] -multiply_by 1 $pclk_out_port
-#create_generated_clock -name bck_out -master_clock bck_pcm -source [get_ports PCM_I2S_BCK_i] -multiply_by 1 $i2s_bck_out_port
-create_generated_clock -name bck_out -master_clock bck_hdmirx -source [get_ports HDMIRX_I2S_BCK_i] -multiply_by 1 $i2s_bck_out_port
+create_generated_clock -name bck_pcm_out -master_clock bck_pcm -source [get_ports PCM_I2S_BCK_i] -multiply_by 1 $i2s_bck_out_port
+create_generated_clock -name bck_hdmirx_out -master_clock bck_hdmirx -source [get_ports HDMIRX_I2S_BCK_i] -multiply_by 1 $i2s_bck_out_port -add
+create_generated_clock -name bck_extpcm_out -master_clock bck_extpcm -source [get_ports EXT_IO_B_io[12]] -multiply_by 1 $i2s_bck_out_port -add
 create_generated_clock -name sd_clk_out -master_clock sd_clk -source [get_pins sys:sys_inst|sdc_controller_top:sdc_controller_0|sdc_controller:sdc0|sd_clock_divider:clock_divider0|SD_CLK_O|q] -multiply_by 1 [get_ports {SD_CLK_o}]
 
 # retrieve post-mapping clkmux output pin
@@ -68,7 +72,7 @@ derive_clock_uncertainty
 
 set_clock_groups -asynchronous -group \
                             {clk27} \
-                            {clk108 sd_clk sd_clk_out} \
+                            {clk108 sd_clk sd_clk_out flash_clk} \
                             {clk148p5} \
                             {pclk_isl pclk_isl_postmux} \
                             {pclk_isl_postmux_div2} \
@@ -78,8 +82,10 @@ set_clock_groups -asynchronous -group \
                             {pclk_sdp_postmux_div2} \
                             {pclk_si pclk_si_out pclk_si_out_vga} \
                             {pclk_si_div2} \
-                            {si_clk_extra} \
-                            {bck_hdmirx bck_pcm bck_out}
+                            {bck_pcm bck_pcm_out} \
+                            {bck_hdmirx bck_hdmirx_out} \
+                            {bck_extpcm bck_extpcm_out} \
+                            {si_clk_extra}
 
 
 ### IO delays ###
@@ -126,8 +132,12 @@ foreach_in_collection c [get_clocks pclk_*_out] {
     set_output_delay -clock $c -clock_fall -max $hdmitx_dmax $hdmitx_data_outputs -add_delay
 }
 
-set_output_delay -clock bck_out -min $hdmitx_dmin [get_ports {HDMITX_I2S_WS_o HDMITX_I2S_DATA_o}] -add_delay
-set_output_delay -clock bck_out -max $hdmitx_dmax [get_ports {HDMITX_I2S_WS_o HDMITX_I2S_DATA_o}] -add_delay
+set_output_delay -clock bck_pcm_out -min $hdmitx_dmin [get_ports {HDMITX_I2S_WS_o HDMITX_I2S_DATA_o}] -add_delay
+set_output_delay -clock bck_pcm_out -max $hdmitx_dmax [get_ports {HDMITX_I2S_WS_o HDMITX_I2S_DATA_o}] -add_delay
+set_output_delay -clock bck_hdmirx_out -min $hdmitx_dmin [get_ports {HDMITX_I2S_WS_o HDMITX_I2S_DATA_o}] -add_delay
+set_output_delay -clock bck_hdmirx_out -max $hdmitx_dmax [get_ports {HDMITX_I2S_WS_o HDMITX_I2S_DATA_o}] -add_delay
+set_output_delay -clock bck_extpcm_out -min $hdmitx_dmin [get_ports {HDMITX_I2S_WS_o HDMITX_I2S_DATA_o}] -add_delay
+set_output_delay -clock bck_extpcm_out -max $hdmitx_dmax [get_ports {HDMITX_I2S_WS_o HDMITX_I2S_DATA_o}] -add_delay
 set_false_path -to [get_ports {HDMITX_SPDIF_o HDMITX_5V_EN_o}]
 
 # extra_av_out
@@ -153,6 +163,9 @@ if {$legacy_av_in} {
     set sdp_inputs [get_ports {EXT_IO_B_io[0] EXT_IO_B_io[3] EXT_IO_B_io[4] EXT_IO_B_io[5] EXT_IO_B_io[6] EXT_IO_B_io[7] EXT_IO_B_io[8] EXT_IO_B_io[9] EXT_IO_B_io[10] EXT_IO_B_io[11]}]
     set_input_delay -clock pclk_sdp -clock_fall -min $sdp_dmin $sdp_inputs -add_delay
     set_input_delay -clock pclk_sdp -clock_fall -max $sdp_dmax $sdp_inputs -add_delay
+
+    # PCM1808
+    set_input_delay 0 -clock bck_extpcm -clock_fall [get_ports {EXT_IO_B_io[13] EXT_IO_B_io[14]}]
 } else {
     set_false_path -from [get_ports {EXT_IO_A_io* EXT_IO_B_io*}]
 }

software/sys_controller/src/firmware.c

@@ -147,7 +147,7 @@ int fw_update(char *dirname, char *filename) {
 }
 
 // commit FW update. Do not call functions located in flash during update
-void __attribute__((noinline, __section__(".text_bram"))) fw_update_commit(fw_header *hdr) {
+void __attribute__((noinline, flatten, noreturn, __section__(".text_bram"))) fw_update_commit(fw_header *hdr) {
     int i, j, sectors;
     uint32_t addr;
     uint32_t *data_from, *data_to, *data_end;

software/sys_controller/src/flash.c

@@ -20,7 +20,7 @@
 #include <unistd.h>
 #include "flash.h"
 
-void __attribute__((noinline, __section__(".text_bram"))) flash_write_protect(flash_ctrl_dev *dev, int enable) {
+void __attribute__((noinline, flatten, __section__(".text_bram"))) flash_write_protect(flash_ctrl_dev *dev, int enable) {
     // Write enable
     dev->regs->flash_cmd_cfg = 0x00000006;
     dev->regs->flash_cmd_ctrl = 1;
@@ -43,7 +43,7 @@ void __attribute__((noinline, __section__(".text_bram"))) flash_write_protect(fl
     dev->regs->flash_cmd_ctrl = 1;
 }
 
-void __attribute__((noinline, __section__(".text_bram"))) flash_sector_erase(flash_ctrl_dev *dev, uint32_t addr) {
+void __attribute__((noinline, flatten, __section__(".text_bram"))) flash_sector_erase(flash_ctrl_dev *dev, uint32_t addr) {
     // Write enable
     dev->regs->flash_cmd_cfg = 0x00000006;
     dev->regs->flash_cmd_ctrl = 1;

software/sys_controller/src/utils.c

@@ -41,7 +41,7 @@ uint32_t gcd(uint32_t a, uint32_t b)
 }
 
 #ifdef HW_CRC32_0_BASE
-unsigned long __attribute__((noinline, __section__(".text_bram"))) crc32(unsigned char *input_data, unsigned long input_data_length, int do_initialize)
+unsigned long __attribute__((noinline, flatten, __section__(".text_bram"))) crc32(unsigned char *input_data, unsigned long input_data_length, int do_initialize)
 {
     unsigned long index;
 

software/sys_controller_bsp/HAL/src/alt_busy_sleep.c

@@ -1,42 +1,42 @@
 /*
- * Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA.  
+ * Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA.
  * All rights reserved.
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to 
- * deal in the Software without restriction, including without limitation the 
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is 
+ * sell copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
  *
- * The above copyright notice and this permission notice shall be included in 
+ * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
- * 
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
- * 
+ *
  * ------------
  *
- * Altera does not recommend, suggest or require that this reference design 
+ * Altera does not recommend, suggest or require that this reference design
  * file be used in conjunction or combination with any other product.
  *
  * alt_busy_sleep.c - Microsecond delay routine which uses a calibrated busy
  *                    loop to perform the delay. This is used to implement
- *                    usleep for both uC/OS-II and the standalone HAL.  
+ *                    usleep for both uC/OS-II and the standalone HAL.
  *
  * Author PRR
  *
  * Calibrated delay with no timer required
- * 
- * The ASM instructions in the routine are equivalent to 
+ *
+ * The ASM instructions in the routine are equivalent to
  *
  * for (i=0;i<us*(ALT_CPU_FREQ/3);i++);
- * 
+ *
  * and takes three cycles each time around the loop
  *
  */
@@ -52,7 +52,7 @@
 #include "altera_avalon_timer.h"
 #include "sys/alt_timestamp.h"
 
-unsigned int __attribute__((noinline, __section__(".text_bram"))) alt_busy_sleep (unsigned int us)
+unsigned int __attribute__((noinline, flatten, __section__(".text_bram"))) alt_busy_sleep (unsigned int us)
 {
 /*
  * Only delay if ALT_SIM_OPTIMIZE is not defined; i.e., if software

software/sys_controller_bsp/drivers/src/altera_avalon_timer_ts.c

@@ -45,20 +45,20 @@
  * for this system.
  */
 
-#if (ALT_TIMESTAMP_CLK_BASE != none_BASE) 
+#if (ALT_TIMESTAMP_CLK_BASE != none_BASE)
 
 /*
  * The function alt_timestamp_start() can be called at application level to
  * initialise the timestamp facility. In this case the period register is
  * set to full scale, i.e. 0xffffffff, and then started running. Note that
- * the period register may not be writable, depending on the hardware 
+ * the period register may not be writable, depending on the hardware
  * configuration, in which case this function does not reset the period.
  *
  * The timer is not run in continuous mode, so that the user can detect timer
  * roll-over, i.e. alt_timestamp() returns 0.
  *
  * The return value of this function is 0 upon sucess and -1 if in timestamp
- * device has not been registered. 
+ * device has not been registered.
  */
 
 int alt_timestamp_start(void)
@@ -82,8 +82,8 @@ int alt_timestamp_start(void)
         IOWR_ALTERA_AVALON_TIMER_CONTROL (base,ALTERA_AVALON_TIMER_CONTROL_STOP_MSK);
         IOWR_ALTERA_AVALON_TIMER_PERIODL (base, 0xFFFF);
         IOWR_ALTERA_AVALON_TIMER_PERIODH (base, 0xFFFF);
-        IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK); 
-    } 
+        IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK);
+    }
   }
   return 0;
 }
@@ -94,10 +94,10 @@ int alt_timestamp_start(void)
  * function return -1.
  *
  * The returned timestamp counts up from the last time the period register
- * was reset. 
+ * was reset.
  */
 
-alt_timestamp_type __attribute__((noinline, __section__(".text_bram"))) alt_timestamp(void)
+alt_timestamp_type __attribute__((noinline, flatten, __section__(".text_bram"))) alt_timestamp(void)
 {
 
   void* base = altera_avalon_timer_ts_base;
@@ -118,14 +118,14 @@ alt_timestamp_type __attribute__((noinline, __section__(".text_bram"))) alt_time
         alt_timestamp_type snap_1 = IORD_ALTERA_AVALON_TIMER_SNAP_1(base) & ALTERA_AVALON_TIMER_SNAP_1_MSK;
         alt_timestamp_type snap_2 = IORD_ALTERA_AVALON_TIMER_SNAP_2(base) & ALTERA_AVALON_TIMER_SNAP_2_MSK;
         alt_timestamp_type snap_3 = IORD_ALTERA_AVALON_TIMER_SNAP_3(base) & ALTERA_AVALON_TIMER_SNAP_3_MSK;
-        
+
         return (0xFFFFFFFFFFFFFFFFULL - ( (snap_3 << 48) | (snap_2 << 32) | (snap_1 << 16) | (snap_0) ));
 #else
         IOWR_ALTERA_AVALON_TIMER_SNAPL (base, 0);
         alt_timestamp_type lower = IORD_ALTERA_AVALON_TIMER_SNAPL(base) & ALTERA_AVALON_TIMER_SNAPL_MSK;
         alt_timestamp_type upper = IORD_ALTERA_AVALON_TIMER_SNAPH(base) & ALTERA_AVALON_TIMER_SNAPH_MSK;
-        
-        return (0xFFFFFFFF - ((upper << 16) | lower)); 
+
+        return (0xFFFFFFFF - ((upper << 16) | lower));
 #endif
   }
 }