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1077 lines (959 loc) · 89.7 KB
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--------------------------------------------------------------------------------
Release 14.7 Trace (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
C:\HDL\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s
1 -n 3 -fastpaths -xml system_top.twx system_top.ncd -o system_top.twr
system_top.pcf -ucf system_top.ucf
Design file: system_top.ncd
Physical constraint file: system_top.pcf
Device,package,speed: xc7z010,clg400,C,-1 (PRODUCTION 1.08 2013-10-13)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: PATH "TS_axi_interconnect_1_reset_resync_path" TIG;
2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------
Paths for end point system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1 (SLICE_X15Y23.BX), 1 path
--------------------------------------------------------------------------------
Delay (setup path): 1.092ns (data path - clock path skew + uncertainty)
Source: system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_0 (FF)
Destination: system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1 (FF)
Data Path Delay: 1.057ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 0.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_0 to system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X15Y23.AQ Tcko 0.456 system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>
system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_0
SLICE_X15Y23.BX net (fanout=1) 0.520 system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<0>
SLICE_X15Y23.CLK Tdick 0.081 system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>
system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1
------------------------------------------------- ---------------------------
Total 1.057ns (0.537ns logic, 0.520ns route)
(50.8% logic, 49.2% route)
--------------------------------------------------------------------------------
Paths for end point system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_2 (SLICE_X15Y23.CX), 1 path
--------------------------------------------------------------------------------
Delay (setup path): 1.071ns (data path - clock path skew + uncertainty)
Source: system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1 (FF)
Destination: system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_2 (FF)
Data Path Delay: 1.036ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 0.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1 to system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X15Y23.BQ Tcko 0.456 system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>
system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1
SLICE_X15Y23.CX net (fanout=1) 0.519 system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<1>
SLICE_X15Y23.CLK Tdick 0.061 system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>
system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_2
------------------------------------------------- ---------------------------
Total 1.036ns (0.517ns logic, 0.519ns route)
(49.9% logic, 50.1% route)
--------------------------------------------------------------------------------
Hold Paths: PATH "TS_axi_interconnect_1_reset_resync_path" TIG;
--------------------------------------------------------------------------------
Paths for end point system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1 (SLICE_X15Y23.BX), 1 path
--------------------------------------------------------------------------------
Delay (hold path): 0.245ns (datapath - clock path skew - uncertainty)
Source: system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_0 (FF)
Destination: system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1 (FF)
Data Path Delay: 0.245ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_0 to system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X15Y23.AQ Tcko 0.141 system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>
system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_0
SLICE_X15Y23.BX net (fanout=1) 0.170 system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<0>
SLICE_X15Y23.CLK Tckdi (-Th) 0.066 system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>
system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1
------------------------------------------------- ---------------------------
Total 0.245ns (0.075ns logic, 0.170ns route)
(30.6% logic, 69.4% route)
--------------------------------------------------------------------------------
Paths for end point system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_2 (SLICE_X15Y23.CX), 1 path
--------------------------------------------------------------------------------
Delay (hold path): 0.241ns (datapath - clock path skew - uncertainty)
Source: system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1 (FF)
Destination: system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_2 (FF)
Data Path Delay: 0.241ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1 to system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X15Y23.BQ Tcko 0.141 system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>
system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_1
SLICE_X15Y23.CX net (fanout=1) 0.170 system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<1>
SLICE_X15Y23.CLK Tckdi (-Th) 0.070 system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>
system_i/axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync_2
------------------------------------------------- ---------------------------
Total 0.241ns (0.071ns logic, 0.170ns route)
(29.5% logic, 70.5% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_0" 100 MHz HIGH
50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
4842 paths analyzed, 1788 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 6.634ns.
--------------------------------------------------------------------------------
Paths for end point system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_6 (SLICE_X15Y45.C3), 34 paths
--------------------------------------------------------------------------------
Slack (setup path): 3.366ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/processing_system7_0/processing_system7_0/PS7_i (OTHER)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_6 (FF)
Requirement: 10.000ns
Data Path Delay: 6.450ns (Levels of Logic = 5)
Clock Path Skew: -0.149ns (0.780 - 0.929)
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 0.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/processing_system7_0/processing_system7_0/PS7_i to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------- -------------------
PS7_X0Y0.MAXIGP0ARLEN0 Tpsscko_MAXIGP0ARLEN 1.416 system_i/processing_system7_0/processing_system7_0/PS7_i
system_i/processing_system7_0/processing_system7_0/PS7_i
SLICE_X10Y49.A2 net (fanout=6) 1.694 system_i/axi_interconnect_1_M_ARLEN<0>
SLICE_X10Y49.A Tilo 0.124 system_i/axi_interconnect_1_M_RLAST
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<0>1
SLICE_X11Y48.D1 net (fanout=2) 0.822 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<0>
SLICE_X11Y48.D Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>11
SLICE_X11Y48.C5 net (fanout=1) 0.263 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>1
SLICE_X11Y48.C Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11_SW0
SLICE_X14Y45.B4 net (fanout=4) 0.924 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>
SLICE_X14Y45.B Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<8>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11
SLICE_X15Y45.C3 net (fanout=3) 0.742 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>1
SLICE_X15Y45.CLK Tas 0.093 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<7>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_xor<6>11
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_6
--------------------------------------------------- ---------------------------
Total 6.450ns (2.005ns logic, 4.445ns route)
(31.1% logic, 68.9% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.458ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/processing_system7_0/processing_system7_0/PS7_i (OTHER)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_6 (FF)
Requirement: 10.000ns
Data Path Delay: 6.358ns (Levels of Logic = 5)
Clock Path Skew: -0.149ns (0.780 - 0.929)
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 0.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/processing_system7_0/processing_system7_0/PS7_i to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------- -------------------
PS7_X0Y0.MAXIGP0ARLEN1 Tpsscko_MAXIGP0ARLEN 1.416 system_i/processing_system7_0/processing_system7_0/PS7_i
system_i/processing_system7_0/processing_system7_0/PS7_i
SLICE_X10Y48.B1 net (fanout=5) 1.697 system_i/axi_interconnect_1_M_ARLEN<1>
SLICE_X10Y48.B Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<2>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/mux1111
SLICE_X11Y48.D3 net (fanout=2) 0.727 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_A<1>
SLICE_X11Y48.D Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>11
SLICE_X11Y48.C5 net (fanout=1) 0.263 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>1
SLICE_X11Y48.C Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11_SW0
SLICE_X14Y45.B4 net (fanout=4) 0.924 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>
SLICE_X14Y45.B Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<8>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11
SLICE_X15Y45.C3 net (fanout=3) 0.742 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>1
SLICE_X15Y45.CLK Tas 0.093 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<7>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_xor<6>11
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_6
--------------------------------------------------- ---------------------------
Total 6.358ns (2.005ns logic, 4.353ns route)
(31.5% logic, 68.5% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.553ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/processing_system7_0/processing_system7_0/PS7_i (OTHER)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_6 (FF)
Requirement: 10.000ns
Data Path Delay: 6.263ns (Levels of Logic = 5)
Clock Path Skew: -0.149ns (0.780 - 0.929)
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 0.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/processing_system7_0/processing_system7_0/PS7_i to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------- -------------------
PS7_X0Y0.MAXIGP0ARLEN1 Tpsscko_MAXIGP0ARLEN 1.416 system_i/processing_system7_0/processing_system7_0/PS7_i
system_i/processing_system7_0/processing_system7_0/PS7_i
SLICE_X11Y49.A3 net (fanout=5) 1.520 system_i/axi_interconnect_1_M_ARLEN<1>
SLICE_X11Y49.A Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/PWR_8_o_rdt_cs[1]_equal_77_o
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<1>1
SLICE_X11Y48.D2 net (fanout=2) 0.809 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<1>
SLICE_X11Y48.D Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>11
SLICE_X11Y48.C5 net (fanout=1) 0.263 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>1
SLICE_X11Y48.C Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11_SW0
SLICE_X14Y45.B4 net (fanout=4) 0.924 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>
SLICE_X14Y45.B Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<8>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11
SLICE_X15Y45.C3 net (fanout=3) 0.742 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>1
SLICE_X15Y45.CLK Tas 0.093 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<7>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_xor<6>11
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_6
--------------------------------------------------- ---------------------------
Total 6.263ns (2.005ns logic, 4.258ns route)
(32.0% logic, 68.0% route)
--------------------------------------------------------------------------------
Paths for end point system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_7 (SLICE_X15Y45.D3), 34 paths
--------------------------------------------------------------------------------
Slack (setup path): 3.372ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/processing_system7_0/processing_system7_0/PS7_i (OTHER)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_7 (FF)
Requirement: 10.000ns
Data Path Delay: 6.444ns (Levels of Logic = 5)
Clock Path Skew: -0.149ns (0.780 - 0.929)
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 0.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/processing_system7_0/processing_system7_0/PS7_i to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_7
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------- -------------------
PS7_X0Y0.MAXIGP0ARLEN0 Tpsscko_MAXIGP0ARLEN 1.416 system_i/processing_system7_0/processing_system7_0/PS7_i
system_i/processing_system7_0/processing_system7_0/PS7_i
SLICE_X10Y49.A2 net (fanout=6) 1.694 system_i/axi_interconnect_1_M_ARLEN<0>
SLICE_X10Y49.A Tilo 0.124 system_i/axi_interconnect_1_M_RLAST
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<0>1
SLICE_X11Y48.D1 net (fanout=2) 0.822 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<0>
SLICE_X11Y48.D Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>11
SLICE_X11Y48.C5 net (fanout=1) 0.263 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>1
SLICE_X11Y48.C Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11_SW0
SLICE_X14Y45.B4 net (fanout=4) 0.924 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>
SLICE_X14Y45.B Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<8>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11
SLICE_X15Y45.D3 net (fanout=3) 0.737 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>1
SLICE_X15Y45.CLK Tas 0.092 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<7>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_xor<7>11
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_7
--------------------------------------------------- ---------------------------
Total 6.444ns (2.004ns logic, 4.440ns route)
(31.1% logic, 68.9% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.464ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/processing_system7_0/processing_system7_0/PS7_i (OTHER)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_7 (FF)
Requirement: 10.000ns
Data Path Delay: 6.352ns (Levels of Logic = 5)
Clock Path Skew: -0.149ns (0.780 - 0.929)
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 0.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/processing_system7_0/processing_system7_0/PS7_i to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_7
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------- -------------------
PS7_X0Y0.MAXIGP0ARLEN1 Tpsscko_MAXIGP0ARLEN 1.416 system_i/processing_system7_0/processing_system7_0/PS7_i
system_i/processing_system7_0/processing_system7_0/PS7_i
SLICE_X10Y48.B1 net (fanout=5) 1.697 system_i/axi_interconnect_1_M_ARLEN<1>
SLICE_X10Y48.B Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<2>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/mux1111
SLICE_X11Y48.D3 net (fanout=2) 0.727 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_A<1>
SLICE_X11Y48.D Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>11
SLICE_X11Y48.C5 net (fanout=1) 0.263 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>1
SLICE_X11Y48.C Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11_SW0
SLICE_X14Y45.B4 net (fanout=4) 0.924 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>
SLICE_X14Y45.B Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<8>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11
SLICE_X15Y45.D3 net (fanout=3) 0.737 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>1
SLICE_X15Y45.CLK Tas 0.092 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<7>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_xor<7>11
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_7
--------------------------------------------------- ---------------------------
Total 6.352ns (2.004ns logic, 4.348ns route)
(31.5% logic, 68.5% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.559ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/processing_system7_0/processing_system7_0/PS7_i (OTHER)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_7 (FF)
Requirement: 10.000ns
Data Path Delay: 6.257ns (Levels of Logic = 5)
Clock Path Skew: -0.149ns (0.780 - 0.929)
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 0.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/processing_system7_0/processing_system7_0/PS7_i to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_7
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------- -------------------
PS7_X0Y0.MAXIGP0ARLEN1 Tpsscko_MAXIGP0ARLEN 1.416 system_i/processing_system7_0/processing_system7_0/PS7_i
system_i/processing_system7_0/processing_system7_0/PS7_i
SLICE_X11Y49.A3 net (fanout=5) 1.520 system_i/axi_interconnect_1_M_ARLEN<1>
SLICE_X11Y49.A Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/PWR_8_o_rdt_cs[1]_equal_77_o
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<1>1
SLICE_X11Y48.D2 net (fanout=2) 0.809 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<1>
SLICE_X11Y48.D Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>11
SLICE_X11Y48.C5 net (fanout=1) 0.263 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>1
SLICE_X11Y48.C Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11_SW0
SLICE_X14Y45.B4 net (fanout=4) 0.924 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>
SLICE_X14Y45.B Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<8>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11
SLICE_X15Y45.D3 net (fanout=3) 0.737 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>1
SLICE_X15Y45.CLK Tas 0.092 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<7>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_xor<7>11
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_7
--------------------------------------------------- ---------------------------
Total 6.257ns (2.004ns logic, 4.253ns route)
(32.0% logic, 68.0% route)
--------------------------------------------------------------------------------
Paths for end point system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8 (SLICE_X14Y45.A4), 34 paths
--------------------------------------------------------------------------------
Slack (setup path): 3.662ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/processing_system7_0/processing_system7_0/PS7_i (OTHER)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8 (FF)
Requirement: 10.000ns
Data Path Delay: 6.154ns (Levels of Logic = 5)
Clock Path Skew: -0.149ns (0.780 - 0.929)
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 0.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/processing_system7_0/processing_system7_0/PS7_i to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------- -------------------
PS7_X0Y0.MAXIGP0ARLEN0 Tpsscko_MAXIGP0ARLEN 1.416 system_i/processing_system7_0/processing_system7_0/PS7_i
system_i/processing_system7_0/processing_system7_0/PS7_i
SLICE_X10Y49.A2 net (fanout=6) 1.694 system_i/axi_interconnect_1_M_ARLEN<0>
SLICE_X10Y49.A Tilo 0.124 system_i/axi_interconnect_1_M_RLAST
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<0>1
SLICE_X11Y48.D1 net (fanout=2) 0.822 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<0>
SLICE_X11Y48.D Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>11
SLICE_X11Y48.C5 net (fanout=1) 0.263 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>1
SLICE_X11Y48.C Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11_SW0
SLICE_X14Y45.B4 net (fanout=4) 0.924 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>
SLICE_X14Y45.B Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<8>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11
SLICE_X14Y45.A4 net (fanout=3) 0.444 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>1
SLICE_X14Y45.CLK Tas 0.095 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<8>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_xor<8>11
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8
--------------------------------------------------- ---------------------------
Total 6.154ns (2.007ns logic, 4.147ns route)
(32.6% logic, 67.4% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.754ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/processing_system7_0/processing_system7_0/PS7_i (OTHER)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8 (FF)
Requirement: 10.000ns
Data Path Delay: 6.062ns (Levels of Logic = 5)
Clock Path Skew: -0.149ns (0.780 - 0.929)
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 0.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/processing_system7_0/processing_system7_0/PS7_i to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------- -------------------
PS7_X0Y0.MAXIGP0ARLEN1 Tpsscko_MAXIGP0ARLEN 1.416 system_i/processing_system7_0/processing_system7_0/PS7_i
system_i/processing_system7_0/processing_system7_0/PS7_i
SLICE_X10Y48.B1 net (fanout=5) 1.697 system_i/axi_interconnect_1_M_ARLEN<1>
SLICE_X10Y48.B Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<2>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/mux1111
SLICE_X11Y48.D3 net (fanout=2) 0.727 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_A<1>
SLICE_X11Y48.D Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>11
SLICE_X11Y48.C5 net (fanout=1) 0.263 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>1
SLICE_X11Y48.C Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11_SW0
SLICE_X14Y45.B4 net (fanout=4) 0.924 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>
SLICE_X14Y45.B Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<8>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11
SLICE_X14Y45.A4 net (fanout=3) 0.444 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>1
SLICE_X14Y45.CLK Tas 0.095 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<8>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_xor<8>11
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8
--------------------------------------------------- ---------------------------
Total 6.062ns (2.007ns logic, 4.055ns route)
(33.1% logic, 66.9% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.849ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/processing_system7_0/processing_system7_0/PS7_i (OTHER)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8 (FF)
Requirement: 10.000ns
Data Path Delay: 5.967ns (Levels of Logic = 5)
Clock Path Skew: -0.149ns (0.780 - 0.929)
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 0.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/processing_system7_0/processing_system7_0/PS7_i to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
--------------------------------------------------- -------------------
PS7_X0Y0.MAXIGP0ARLEN1 Tpsscko_MAXIGP0ARLEN 1.416 system_i/processing_system7_0/processing_system7_0/PS7_i
system_i/processing_system7_0/processing_system7_0/PS7_i
SLICE_X11Y49.A3 net (fanout=5) 1.520 system_i/axi_interconnect_1_M_ARLEN<1>
SLICE_X11Y49.A Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/PWR_8_o_rdt_cs[1]_equal_77_o
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<1>1
SLICE_X11Y48.D2 net (fanout=2) 0.809 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<1>
SLICE_X11Y48.D Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>11
SLICE_X11Y48.C5 net (fanout=1) 0.263 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>1
SLICE_X11Y48.C Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<1>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11_SW0
SLICE_X14Y45.B4 net (fanout=4) 0.924 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>
SLICE_X14Y45.B Tilo 0.124 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<8>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11
SLICE_X14Y45.A4 net (fanout=3) 0.444 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>1
SLICE_X14Y45.CLK Tas 0.095 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count<8>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_xor<8>11
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8
--------------------------------------------------- ---------------------------
Total 5.967ns (2.007ns logic, 3.960ns route)
(33.6% logic, 66.4% route)
--------------------------------------------------------------------------------
Hold Paths: TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_0" 100 MHz HIGH 50%;
--------------------------------------------------------------------------------
Paths for end point system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d1_3 (SLICE_X20Y48.CX), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.003ns (requirement - (clock path skew + uncertainty - data path))
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_3 (FF)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d1_3 (FF)
Requirement: 0.000ns
Data Path Delay: 0.268ns (Levels of Logic = 0)
Clock Path Skew: 0.265ns (0.776 - 0.511)
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_3 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d1_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X22Y48.AMUX Tshcko 0.182 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count<2>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_3
SLICE_X20Y48.CX net (fanout=3) 0.149 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count<3>
SLICE_X20Y48.CLK Tckdi (-Th) 0.063 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d1<3>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d1_3
------------------------------------------------- ---------------------------
Total 0.268ns (0.119ns logic, 0.149ns route)
(44.4% logic, 55.6% route)
--------------------------------------------------------------------------------
Paths for end point system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA (SLICE_X16Y50.D2), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.017ns (requirement - (clock path skew + uncertainty - data path))
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d2_1 (FF)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA (RAM)
Requirement: 0.000ns
Data Path Delay: 0.284ns (Levels of Logic = 0)
Clock Path Skew: 0.267ns (0.830 - 0.563)
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d2_1 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X19Y48.BQ Tcko 0.141 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d2<3>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d2_1
SLICE_X16Y50.D2 net (fanout=10) 0.452 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d2<1>
SLICE_X16Y50.CLK Tah (-Th) 0.309 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i<11>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA
------------------------------------------------- ---------------------------
Total 0.284ns (-0.168ns logic, 0.452ns route)
(-59.2% logic, 159.2% route)
--------------------------------------------------------------------------------
Paths for end point system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA_D1 (SLICE_X16Y50.D2), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.017ns (requirement - (clock path skew + uncertainty - data path))
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d2_1 (FF)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA_D1 (RAM)
Requirement: 0.000ns
Data Path Delay: 0.284ns (Levels of Logic = 0)
Clock Path Skew: 0.267ns (0.830 - 0.563)
Source Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Destination Clock: system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d2_1 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA_D1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X19Y48.BQ Tcko 0.141 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d2<3>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d2_1
SLICE_X16Y50.D2 net (fanout=10) 0.452 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc1.count_d2<1>
SLICE_X16Y50.CLK Tah (-Th) 0.309 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i<11>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdfifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA_D1
------------------------------------------------- ---------------------------
Total 0.284ns (-0.168ns logic, 0.452ns route)
(-59.2% logic, 159.2% route)
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_0" 100 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 5.508ns (period - min period limit)
Period: 6.757ns
Min period limit: 1.249ns (800.641MHz) (Tmmcmper_CLKOUT(Foutmax))
Physical resource: system_i/clock_generator_0/clock_generator_0/MMCM1_INST/MMCM_ADV_inst/CLKOUT0
Logical resource: system_i/clock_generator_0/clock_generator_0/MMCM1_INST/MMCM_ADV_inst/CLKOUT0
Location pin: MMCME2_ADV_X0Y0.CLKOUT0
Clock network: system_i/clock_generator_0/clock_generator_0/SIG_MMCM1_CLKOUT0
--------------------------------------------------------------------------------
Slack: 6.000ns (period - (min low pulse limit / (low pulse / period)))
Period: 10.000ns
Low pulse: 5.000ns
Low pulse limit: 2.000ns (Tmmcmpw_CLKIN1_100_150)
Physical resource: system_i/clock_generator_0/clock_generator_0/MMCM1_INST/MMCM_ADV_inst/CLKIN1
Logical resource: system_i/clock_generator_0/clock_generator_0/MMCM1_INST/MMCM_ADV_inst/CLKIN1
Location pin: MMCME2_ADV_X0Y0.CLKIN1
Clock network: system_i/processing_system7_0_FCLK_CLK0
--------------------------------------------------------------------------------
Slack: 6.000ns (period - (min high pulse limit / (high pulse / period)))
Period: 10.000ns
High pulse: 5.000ns
High pulse limit: 2.000ns (Tmmcmpw_CLKIN1_100_150)
Physical resource: system_i/clock_generator_0/clock_generator_0/MMCM1_INST/MMCM_ADV_inst/CLKIN1
Logical resource: system_i/clock_generator_0/clock_generator_0/MMCM1_INST/MMCM_ADV_inst/CLKIN1
Location pin: MMCME2_ADV_X0Y0.CLKIN1
Clock network: system_i/processing_system7_0_FCLK_CLK0
--------------------------------------------------------------------------------
================================================================================
Timing constraint:
TS_system_i_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0 = PERIOD
TIMEGRP
"system_i_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0"
TS_clk_fpga_0 * 1.48 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
3348 paths analyzed, 1169 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 5.109ns.
--------------------------------------------------------------------------------
Paths for end point system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node_2 (SLICE_X28Y58.C1), 4 paths
--------------------------------------------------------------------------------
Slack (setup path): 1.647ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/reset_p2d (FF)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node_2 (FF)
Requirement: 6.756ns
Data Path Delay: 4.704ns (Levels of Logic = 2)
Clock Path Skew: -0.253ns (1.487 - 1.740)
Source Clock: system_i/clock_generator_0_CLKOUT0 rising at 0.000ns
Destination Clock: system_i/clock_generator_0_CLKOUT0 rising at 6.756ns
Clock Uncertainty: 0.152ns
Clock Uncertainty: 0.152ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.295ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/reset_p2d to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X38Y31.DQ Tcko 0.518 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/reset_p2d
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/reset_p2d
SLICE_X30Y57.A2 net (fanout=54) 2.778 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/reset_p2d
SLICE_X30Y57.AMUX Tilo 0.350 system_i/cdc_vga_axi_slave_0/N31
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/_n01411_SW12
SLICE_X28Y58.C1 net (fanout=1) 1.013 system_i/cdc_vga_axi_slave_0/N34
SLICE_X28Y58.CLK Tas 0.045 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node<2>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node_2_glue_rst
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node_2
------------------------------------------------- ---------------------------
Total 4.704ns (0.913ns logic, 3.791ns route)
(19.4% logic, 80.6% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.739ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/temp_color_15 (FF)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node_2 (FF)
Requirement: 6.756ns
Data Path Delay: 2.840ns (Levels of Logic = 2)
Clock Path Skew: -0.025ns (0.169 - 0.194)
Source Clock: system_i/clock_generator_0_CLKOUT0 rising at 0.000ns
Destination Clock: system_i/clock_generator_0_CLKOUT0 rising at 6.756ns
Clock Uncertainty: 0.152ns
Clock Uncertainty: 0.152ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.295ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/temp_color_15 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X31Y58.AMUX Tshcko 0.594 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/temp_color<15>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/temp_color_15
SLICE_X30Y57.A1 net (fanout=1) 0.834 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/temp_color<15>
SLICE_X30Y57.AMUX Tilo 0.354 system_i/cdc_vga_axi_slave_0/N31
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/_n01411_SW12
SLICE_X28Y58.C1 net (fanout=1) 1.013 system_i/cdc_vga_axi_slave_0/N34
SLICE_X28Y58.CLK Tas 0.045 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node<2>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node_2_glue_rst
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node_2
------------------------------------------------- ---------------------------
Total 2.840ns (0.993ns logic, 1.847ns route)
(35.0% logic, 65.0% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.957ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_data_node_0 (FF)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node_2 (FF)
Requirement: 6.756ns
Data Path Delay: 2.587ns (Levels of Logic = 2)
Clock Path Skew: -0.060ns (0.777 - 0.837)
Source Clock: system_i/clock_generator_0_CLKOUT0 rising at 0.000ns
Destination Clock: system_i/clock_generator_0_CLKOUT0 rising at 6.756ns
Clock Uncertainty: 0.152ns
Clock Uncertainty: 0.152ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.295ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_data_node_0 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X27Y53.AQ Tcko 0.456 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_data_node<3>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_data_node_0
SLICE_X30Y57.A5 net (fanout=5) 0.753 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_data_node<0>
SLICE_X30Y57.AMUX Tilo 0.320 system_i/cdc_vga_axi_slave_0/N31
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/_n01411_SW12
SLICE_X28Y58.C1 net (fanout=1) 1.013 system_i/cdc_vga_axi_slave_0/N34
SLICE_X28Y58.CLK Tas 0.045 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node<2>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node_2_glue_rst
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/red_node_2
------------------------------------------------- ---------------------------
Total 2.587ns (0.821ns logic, 1.766ns route)
(31.7% logic, 68.3% route)
--------------------------------------------------------------------------------
Paths for end point system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST (RAMB18_X1Y21.ADDRARDADDR10), 2 paths
--------------------------------------------------------------------------------
Slack (setup path): 1.652ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem5 (RAM)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST (RAM)
Requirement: 6.756ns
Data Path Delay: 4.760ns (Levels of Logic = 0)
Clock Path Skew: -0.192ns (1.530 - 1.722)
Source Clock: system_i/clock_generator_0_CLKOUT0 rising at 0.000ns
Destination Clock: system_i/clock_generator_0_CLKOUT0 rising at 6.756ns
Clock Uncertainty: 0.152ns
Clock Uncertainty: 0.152ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.295ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem5 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------- -------------------
RAMB36_X0Y9.DOBDO0 Trcko_DOB 2.454 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem5
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem5
RAMB18_X1Y21.ADDRARDADDR10 net (fanout=1) 1.740 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_dout<4>
RAMB18_X1Y21.CLKARDCLK Trcck_ADDRA 0.566 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
------------------------------------------------------- ---------------------------
Total 4.760ns (3.020ns logic, 1.740ns route)
(63.4% logic, 36.6% route)
--------------------------------------------------------------------------------
Slack (setup path): 1.652ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem5 (RAM)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST (RAM)
Requirement: 6.756ns
Data Path Delay: 4.760ns (Levels of Logic = 0)
Clock Path Skew: -0.192ns (1.530 - 1.722)
Source Clock: system_i/clock_generator_0_CLKOUT0 rising at 0.000ns
Destination Clock: system_i/clock_generator_0_CLKOUT0 rising at 6.756ns
Clock Uncertainty: 0.152ns
Clock Uncertainty: 0.152ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.295ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem5 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------- -------------------
RAMB36_X0Y9.DOBDO0 Trcko_DOB 2.454 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem5
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem5
RAMB18_X1Y21.ADDRARDADDR10 net (fanout=1) 1.740 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_dout<4>
RAMB18_X1Y21.CLKARDCLK Trcck_ADDRA 0.566 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
------------------------------------------------------- ---------------------------
Total 4.760ns (3.020ns logic, 1.740ns route)
(63.4% logic, 36.6% route)
--------------------------------------------------------------------------------
Paths for end point system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST (RAMB18_X1Y21.ADDRARDADDR9), 2 paths
--------------------------------------------------------------------------------
Slack (setup path): 1.778ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem4 (RAM)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST (RAM)
Requirement: 6.756ns
Data Path Delay: 4.658ns (Levels of Logic = 0)
Clock Path Skew: -0.168ns (1.390 - 1.558)
Source Clock: system_i/clock_generator_0_CLKOUT0 rising at 0.000ns
Destination Clock: system_i/clock_generator_0_CLKOUT0 rising at 6.756ns
Clock Uncertainty: 0.152ns
Clock Uncertainty: 0.152ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.295ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem4 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------ -------------------
RAMB36_X0Y10.DOBDO0 Trcko_DOB 2.454 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem4
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem4
RAMB18_X1Y21.ADDRARDADDR9 net (fanout=1) 1.638 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_dout<3>
RAMB18_X1Y21.CLKARDCLK Trcck_ADDRA 0.566 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
------------------------------------------------------ ---------------------------
Total 4.658ns (3.020ns logic, 1.638ns route)
(64.8% logic, 35.2% route)
--------------------------------------------------------------------------------
Slack (setup path): 1.778ns (requirement - (data path - clock path skew + uncertainty))
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem4 (RAM)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST (RAM)
Requirement: 6.756ns
Data Path Delay: 4.658ns (Levels of Logic = 0)
Clock Path Skew: -0.168ns (1.390 - 1.558)
Source Clock: system_i/clock_generator_0_CLKOUT0 rising at 0.000ns
Destination Clock: system_i/clock_generator_0_CLKOUT0 rising at 6.756ns
Clock Uncertainty: 0.152ns
Clock Uncertainty: 0.152ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.295ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem4 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------ -------------------
RAMB36_X0Y10.DOBDO0 Trcko_DOB 2.454 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem4
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem4
RAMB18_X1Y21.ADDRARDADDR9 net (fanout=1) 1.638 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_dout<3>
RAMB18_X1Y21.CLKARDCLK Trcck_ADDRA 0.566 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
------------------------------------------------------ ---------------------------
Total 4.658ns (3.020ns logic, 1.638ns route)
(64.8% logic, 35.2% route)
--------------------------------------------------------------------------------
Hold Paths: TS_system_i_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0 = PERIOD
TIMEGRP
"system_i_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0"
TS_clk_fpga_0 * 1.48 HIGH 50%;
--------------------------------------------------------------------------------
Paths for end point system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST (RAMB18_X1Y21.ADDRARDADDR4), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.017ns (requirement - (clock path skew + uncertainty - data path))
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/disp_timing_inst/v_addr_node_1 (FF)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST (RAM)
Requirement: 0.000ns
Data Path Delay: 0.325ns (Levels of Logic = 0)
Clock Path Skew: 0.308ns (0.871 - 0.563)
Source Clock: system_i/clock_generator_0_CLKOUT0 rising at 0.000ns
Destination Clock: system_i/clock_generator_0_CLKOUT0 rising at 0.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/disp_timing_inst/v_addr_node_1 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------ -------------------
SLICE_X32Y47.BQ Tcko 0.164 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/v_addr<2>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/disp_timing_inst/v_addr_node_1
RAMB18_X1Y21.ADDRARDADDR4 net (fanout=17) 0.344 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/v_addr<1>
RAMB18_X1Y21.CLKARDCLK Trckc_ADDRA (-Th) 0.183 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST
------------------------------------------------------ ---------------------------
Total 0.325ns (-0.019ns logic, 0.344ns route)
(-5.8% logic, 105.8% route)
--------------------------------------------------------------------------------
Paths for end point system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem7 (RAMB36_X1Y9.ADDRBWRADDRL10), 1 path
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Slack (hold path): 0.037ns (requirement - (clock path skew + uncertainty - data path))
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_addr_10 (FF)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem7 (RAM)
Requirement: 0.000ns
Data Path Delay: 0.352ns (Levels of Logic = 0)
Clock Path Skew: 0.315ns (0.872 - 0.557)
Source Clock: system_i/clock_generator_0_CLKOUT0 rising at 0.000ns
Destination Clock: system_i/clock_generator_0_CLKOUT0 rising at 0.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_addr_10 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem7
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------- -------------------
SLICE_X23Y53.CQ Tcko 0.141 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_addr<11>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_addr_10
RAMB36_X1Y9.ADDRBWRADDRL10 net (fanout=34) 0.394 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_addr<10>
RAMB36_X1Y9.CLKBWRCLKL Trckc_ADDRB (-Th) 0.183 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem7
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem7
------------------------------------------------------- ---------------------------
Total 0.352ns (-0.042ns logic, 0.394ns route)
(-11.9% logic, 111.9% route)
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Paths for end point system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem7 (RAMB36_X1Y9.ADDRBWRADDRU10), 1 path
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Slack (hold path): 0.037ns (requirement - (clock path skew + uncertainty - data path))
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_addr_10 (FF)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem7 (RAM)
Requirement: 0.000ns
Data Path Delay: 0.352ns (Levels of Logic = 0)
Clock Path Skew: 0.315ns (0.872 - 0.557)
Source Clock: system_i/clock_generator_0_CLKOUT0 rising at 0.000ns
Destination Clock: system_i/clock_generator_0_CLKOUT0 rising at 0.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_addr_10 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem7
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------- -------------------
SLICE_X23Y53.CQ Tcko 0.141 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_addr<11>
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_addr_10
RAMB36_X1Y9.ADDRBWRADDRU10 net (fanout=34) 0.394 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/display_addr<10>
RAMB36_X1Y9.CLKBWRCLKU Trckc_ADDRB (-Th) 0.183 system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem7
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem7
------------------------------------------------------- ---------------------------
Total 0.352ns (-0.042ns logic, 0.394ns route)
(-11.9% logic, 111.9% route)
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Component Switching Limit Checks: TS_system_i_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0 = PERIOD