cpu: 16 bit core inaccuracies #38
Description
Background
The instruction fuzzer allows some confidence in comparing instruction emulation details with another system. This has helped improving the accuracy compared to other vm implementations. Mostly this has uncovered some bugs with flags so far.
Problem
Most 8-bit instructions have now been fuzzed with the instruction fuzzer.
A few instructions have been found to differ enough to warrant more research:
Neg8: mov ah,0; not ah = OVERFLOW flag differs vs winxp
Idiv8: hard to fuzz due to input that triggers DIV0 exception
SPECIAL NOTES:
Rol8, Ror8, Rcl8, Rcr8 - OVERFLOW flag differ from winxp
XXX: Aam - P Z S flags differ from winxp & dosbox-x
XXX: Rcl8 register values don't match with dosbox-x, but with bochs & winxp
dustbox tries to be consistent with dosbox-x where behavior differs
TODO:
- fuzz the 16 bit opcodes
- test Rol8, Ror8, Rcl8, Rcr8 ops on real hardware