Skip to content

Commit a2cde2e

Browse files
0xc01700xc0170
authored
Merge pull request ARMmbed#10570 from jeromecoutant/PR_ASTYLE
STM32 astyle updates
2 parents 3ea1c56 + 0352bbb commit a2cde2e

File tree

9 files changed

+179
-190
lines changed

9 files changed

+179
-190
lines changed

‎targets/TARGET_STM/TARGET_STM32F7/flash_api.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -284,7 +284,7 @@ static uint32_t GetSectorBase(uint32_t SectorId)
284284
int i = 0;
285285
uint32_t address_sector = FLASH_BASE;
286286

287-
for(i=0;i<SectorId;i++){
287+
for (i = 0; i < SectorId; i++) {
288288
address_sector += GetSectorSize(i);
289289
}
290290
return address_sector;

‎targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TARGET_NUCLEO_WB55RG/PeripheralPins.c

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -141,38 +141,38 @@ MBED_WEAK const PinMap PinMap_PWM[] = {
141141
//*** SERIAL ***
142142

143143
MBED_WEAK const PinMap PinMap_UART_TX[] = {
144-
{PA_2, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
144+
{PA_2, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
145145
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
146-
{PB_5, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD1 [Blue Led]
146+
{PB_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD1 [Blue Led]
147147
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX
148-
{PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
149-
{PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
148+
{PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
149+
{PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
150150
{NC, NC, 0}
151151
};
152152

153153
MBED_WEAK const PinMap PinMap_UART_RX[] = {
154-
{PA_3, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
154+
{PA_3, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
155155
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
156-
{PA_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_DP
156+
{PA_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_DP
157157
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX
158-
{PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
159-
{PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
158+
{PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
159+
{PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
160160
{NC, NC, 0}
161161
};
162162

163163
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
164164
{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP
165-
{PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD3 [Red Led]
165+
{PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD3 [Red Led]
166166
{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to JTDO
167-
{PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
167+
{PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
168168
{NC, NC, 0}
169169
};
170170

171171
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
172-
{PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
172+
{PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
173173
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM
174174
{PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
175-
{PB_13, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
175+
{PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
176176
{NC, NC, 0}
177177
};
178178

‎targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TARGET_NUCLEO_WB55RG/system_clock.c

Lines changed: 69 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ static void Configure_RF_Clock_Sources(void)
6262
{
6363
static uint8_t RF_ON = 0;
6464

65-
if ( !RF_ON ) {
65+
if (!RF_ON) {
6666
// Reset backup domain
6767
if ((LL_RCC_IsActiveFlag_PINRST()) && (!LL_RCC_IsActiveFlag_SFTRST())) {
6868
// Write twice the value to flush the APB-AHB bridge
@@ -97,18 +97,17 @@ static void Configure_RF_Clock_Sources(void)
9797

9898
static void Config_HSE(void)
9999
{
100-
OTP_ID0_t * p_otp;
101-
102-
/**
103-
* Read HSE_Tuning from OTP
104-
*/
105-
p_otp = (OTP_ID0_t *) OTP_Read(0);
106-
if (p_otp)
107-
{
108-
LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
109-
}
110-
111-
return;
100+
OTP_ID0_t *p_otp;
101+
102+
/**
103+
* Read HSE_Tuning from OTP
104+
*/
105+
p_otp = (OTP_ID0_t *) OTP_Read(0);
106+
if (p_otp) {
107+
LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
108+
}
109+
110+
return;
112111
}
113112

114113

@@ -122,7 +121,7 @@ static void Config_HSE(void)
122121

123122
void SetSysClock(void)
124123
{
125-
while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
124+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
126125
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
127126
/* 1- Try to start with HSE and external clock */
128127
if (SetSysClock_PLL_HSE(1) == 0)
@@ -157,7 +156,7 @@ void SetSysClock(void)
157156
#if DEBUG_MCO == 1
158157
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 64 MHz
159158
#endif
160-
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
159+
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
161160
}
162161

163162
#if (((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC))
@@ -166,66 +165,63 @@ void SetSysClock(void)
166165
/******************************************************************************/
167166
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
168167
{
169-
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
170-
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
171-
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
168+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
169+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
170+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
171+
172+
Config_HSE();
173+
174+
/** Configure the main internal regulator output voltage
175+
*/
176+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
177+
/** Initializes the CPU, AHB and APB busses clocks
178+
*/
179+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
180+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
181+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
182+
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
183+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
184+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
185+
return 0; // FAIL
186+
}
187+
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
188+
*/
189+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
190+
| RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
191+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
192+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
193+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
194+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
195+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
196+
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
197+
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
198+
199+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
200+
return 0; // FAIL
201+
}
202+
/** Initializes the peripherals clocks
203+
*/
204+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
205+
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
206+
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
172207

173-
Config_HSE();
208+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
209+
return 0; // FAIL
210+
}
174211

175-
/** Configure the main internal regulator output voltage
176-
*/
177-
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
178-
/** Initializes the CPU, AHB and APB busses clocks
179-
*/
180-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE;
181-
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
182-
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
183-
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
184-
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
185-
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
186-
{
187-
return 0; // FAIL
188-
}
189-
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
190-
*/
191-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
192-
|RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
193-
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
194-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
195-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
196-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
197-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
198-
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
199-
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
200-
201-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
202-
{
203-
return 0; // FAIL
204-
}
205-
/** Initializes the peripherals clocks
206-
*/
207-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
208-
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
209-
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
210-
211-
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
212-
{
213-
return 0; // FAIL
214-
}
215-
216-
/**
217-
* Select HSI as system clock source after Wake Up from Stop mode
218-
*/
219-
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
220-
221-
/**
222-
* Set RNG on HSI48
223-
*/
224-
LL_RCC_HSI48_Enable();
225-
while(!LL_RCC_HSI48_IsReady());
226-
LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_HSI48);
227-
228-
return 1;
212+
/**
213+
* Select HSI as system clock source after Wake Up from Stop mode
214+
*/
215+
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
216+
217+
/**
218+
* Set RNG on HSI48
219+
*/
220+
LL_RCC_HSI48_Enable();
221+
while (!LL_RCC_HSI48_IsReady());
222+
LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_HSI48);
223+
224+
return 1;
229225
}
230226

231227
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */

‎targets/TARGET_STM/TARGET_STM32WB/flash_api.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
7777

7878
#if defined(CFG_HW_FLASH_SEMID)
7979
/* In case RNG is a shared ressource, get the HW semaphore first */
80-
while( LL_HSEM_1StepLock( HSEM, CFG_HW_FLASH_SEMID ) );
80+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID));
8181
#endif
8282

8383
/* Unlock the Flash to enable the flash control register access */
@@ -109,7 +109,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
109109
HAL_FLASH_Lock();
110110

111111
#if defined(CFG_HW_FLASH_SEMID)
112-
LL_HSEM_ReleaseLock( HSEM, CFG_HW_FLASH_SEMID, 0 );
112+
LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, 0);
113113
#endif
114114

115115
return status;
@@ -141,7 +141,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
141141

142142
#if defined(CFG_HW_FLASH_SEMID)
143143
/* In case RNG is a shared ressource, get the HW semaphore first */
144-
while( LL_HSEM_1StepLock( HSEM, CFG_HW_FLASH_SEMID ) );
144+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID));
145145
#endif
146146

147147
/* Unlock the Flash to enable the flash control register access */
@@ -182,7 +182,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
182182
HAL_FLASH_Lock();
183183

184184
#if defined(CFG_HW_FLASH_SEMID)
185-
LL_HSEM_ReleaseLock( HSEM, CFG_HW_FLASH_SEMID, 0 );
185+
LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, 0);
186186
#endif
187187

188188
return status;

0 commit comments

Comments
 (0)