diff --git a/TODO b/TODO
new file mode 100644
index 0000000000000..fb9a6bb1936d5
--- /dev/null
+++ b/TODO
@@ -0,0 +1 @@
+* update code in HAL side
diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c
index 447e819a64a13..17b6f186bf823 100644
--- a/drivers/adc/adc_stm32.c
+++ b/drivers/adc/adc_stm32.c
@@ -43,6 +43,8 @@
 #define ADC_CONTEXT_ENABLE_ON_COMPLETE
 #include "adc_context.h"
 
+#include <stm32_global_periph_clocks.h>
+
 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(adc_stm32);
@@ -1587,21 +1589,33 @@ static int adc_stm32_set_clock(const struct device *dev)
 
 static void adc_stm32_enable_analog_supply(void)
 {
+	if (IS_ENABLED(CONFIG_SOC_SERIES_STM32N6X) ||
+	    IS_ENABLED(CONFIG_SOC_SERIES_STM32U5X) ||
+	    IS_ENABLED(CONFIG_SOC_SERIES_STM32U3X)) {
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 #if defined(CONFIG_SOC_SERIES_STM32N6X)
-	LL_PWR_EnableVddADC();
+		LL_PWR_EnableVddADC();
 #elif defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32U3X)
-	LL_PWR_EnableVDDA();
+		LL_PWR_EnableVDDA();
 #endif /* CONFIG_SOC_SERIES_STM32U5X */
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+	}
 }
 
 #ifdef CONFIG_PM_DEVICE
 static void adc_stm32_disable_analog_supply(void)
 {
+	if (IS_ENABLED(CONFIG_SOC_SERIES_STM32N6X) ||
+	    IS_ENABLED(CONFIG_SOC_SERIES_STM32U5X) ||
+	    IS_ENABLED(CONFIG_SOC_SERIES_STM32U3X)) {
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 #if defined(CONFIG_SOC_SERIES_STM32N6X)
 	LL_PWR_DisableVddADC();
 #elif defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32U3X)
 	LL_PWR_DisableVDDA();
 #endif /* CONFIG_SOC_SERIES_STM32U5X */
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+	}
 }
 #endif
 
diff --git a/drivers/adc/adc_stm32wb0.c b/drivers/adc/adc_stm32wb0.c
index 02d65e1c7ab5b..1b424643ff2ee 100644
--- a/drivers/adc/adc_stm32wb0.c
+++ b/drivers/adc/adc_stm32wb0.c
@@ -47,6 +47,7 @@
 
 #include <soc.h>
 #include <stm32_bitops.h>
+#include <stm32_global_periph_clocks.h>
 #include <stm32_ll_adc.h>
 #include <stm32_ll_utils.h>
 
@@ -1101,8 +1102,10 @@ int adc_stm32wb0_init(const struct device *dev)
 #endif
 
 #if defined(PWR_CR2_ENTS)
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	/* Enable on-die temperature sensor */
 	LL_PWR_EnableTempSens();
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 #endif
 
 	/* Set ADC sample rate to 1 Msps (maximum speed) */
diff --git a/drivers/bluetooth/hci/hci_stm32wb0.c b/drivers/bluetooth/hci/hci_stm32wb0.c
index 66cae4b8964ca..68333eea34d78 100644
--- a/drivers/bluetooth/hci/hci_stm32wb0.c
+++ b/drivers/bluetooth/hci/hci_stm32wb0.c
@@ -320,12 +320,16 @@ static int ble_pm_action(const struct device *dev,
 
 	switch (action) {
 	case PM_DEVICE_ACTION_SUSPEND:
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		LL_PWR_EnableWU_EWBLE();
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 		pka_cr_vr = PKA->CR;
 		/* TBD: Manage PKA save for WB06 & WB07 */
 		break;
 	case PM_DEVICE_ACTION_RESUME:
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		LL_PWR_DisableWU_EWBLE();
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 		/* TBD: Manage PKA restore for WB06 & WB07 */
 		PKA->CLRFR = PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC;
 		PKA->CR = pka_cr_vr;
diff --git a/drivers/bluetooth/hci/hci_stm32wba.c b/drivers/bluetooth/hci/hci_stm32wba.c
index c60e41bcbd585..dede4a5f5d6a0 100644
--- a/drivers/bluetooth/hci/hci_stm32wba.c
+++ b/drivers/bluetooth/hci/hci_stm32wba.c
@@ -21,6 +21,8 @@
 #endif /* CONFIG_PM_DEVICE */
 #include <linklayer_plat_local.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <zephyr/sys/byteorder.h>
 
 #include "blestack.h"
@@ -561,10 +563,12 @@ static int radio_pm_action(const struct device *dev, enum pm_device_action actio
 	case PM_DEVICE_ACTION_RESUME:
 		LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_RADIO);
 #if defined(CONFIG_PM_S2RAM)
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		if (LL_PWR_IsActiveFlag_SB() == 1U) {
 			/* Put the radio in active state */
 			link_layer_register_isr();
 		}
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 #endif /* CONFIG_PM_S2RAM */
 		LINKLAYER_PLAT_NotifyWFIExit();
 		ll_sys_dp_slp_exit();
diff --git a/drivers/bluetooth/hci/ipm_stm32wb.c b/drivers/bluetooth/hci/ipm_stm32wb.c
index 0f61f7c36f788..2a156fd76b076 100644
--- a/drivers/bluetooth/hci/ipm_stm32wb.c
+++ b/drivers/bluetooth/hci/ipm_stm32wb.c
@@ -16,6 +16,8 @@
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/irq.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include "app_conf.h"
 #include "stm32_wpan_common.h"
 #include "shci.h"
@@ -545,8 +547,10 @@ static int bt_ipm_open(const struct device *dev, bt_hci_recv_t recv)
 	if (!c2_started_flag) {
 		/* C2 has been teared down. Reinit required */
 		SHCI_C2_Reinit();
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR); //TODO: before C2_Reinit?
 		while (LL_PWR_IsActiveFlag_C2DS() == 0) {
 		};
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 
 		err = c2_reset();
 		if (err) {
@@ -599,8 +603,10 @@ static int bt_ipm_close(const struct device *dev)
 	}
 
 	/* Wait till C2DS set */
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	while (LL_PWR_IsActiveFlag_C2DS() == 0) {
 	};
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 
 	c2_started_flag = false;
 
diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c
index c657a3db2b51a..12d51306cbd6b 100644
--- a/drivers/clock_control/clock_stm32_ll_common.c
+++ b/drivers/clock_control/clock_stm32_ll_common.c
@@ -17,6 +17,7 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/__assert.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <stm32_global_periph_clocks.h>
 #include <stm32_backup_domain.h>
 #include <stm32_hsem.h>
 
@@ -1027,8 +1028,9 @@ static void set_up_fixed_clock_sources(void)
 		 * HSI48 requires VREFINT (see RM0376 section 7.2.4).
 		 * The SYSCFG is needed to control VREFINT, so clock it.
 		 */
-		LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
 		LL_SYSCFG_VREFINT_EnableHSI48();
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
 #endif /* CONFIG_SOC_SERIES_STM32L0X */
 
 		/*
diff --git a/drivers/clock_control/clock_stm32_ll_h5.c b/drivers/clock_control/clock_stm32_ll_h5.c
index 466305b4e690e..296a173eb6b95 100644
--- a/drivers/clock_control/clock_stm32_ll_h5.c
+++ b/drivers/clock_control/clock_stm32_ll_h5.c
@@ -19,6 +19,7 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <stm32_backup_domain.h>
+#include <stm32_global_periph_clocks.h>
 
 /* Macros to fill up prescaler values */
 #define z_hsi_divider(v) LL_RCC_HSI_DIV_ ## v
@@ -438,6 +439,8 @@ static uint32_t get_vco_output_range(uint32_t vco_input_range)
 
 static void set_regu_voltage(uint32_t hclk_freq)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	if (hclk_freq <= MHZ(100)) {
 		LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE3);
 	} else if (hclk_freq <= MHZ(150)) {
@@ -449,6 +452,8 @@ static void set_regu_voltage(uint32_t hclk_freq)
 	}
 	while (LL_PWR_IsActiveFlag_VOS() == 0) {
 	}
+
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 }
 
 __unused
diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c
index 2f0a581d24bec..60d645f5a043f 100644
--- a/drivers/clock_control/clock_stm32_ll_h7.c
+++ b/drivers/clock_control/clock_stm32_ll_h7.c
@@ -16,6 +16,7 @@
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <stm32_global_periph_clocks.h>
 #include <stm32_backup_domain.h>
 #include <stm32_hsem.h>
 
@@ -1025,6 +1026,9 @@ int stm32_clock_control_init(const struct device *dev)
 {
 	int r = 0;
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
+
 #if defined(CONFIG_CPU_CORTEX_M7)
 	uint32_t old_hclk_freq;
 	uint32_t new_hclk_freq;
@@ -1142,6 +1146,8 @@ int stm32_clock_control_init(const struct device *dev)
 		LL_RCC_SetTIMPrescaler(LL_RCC_TIM_PRESCALER_TWICE);
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	ARG_UNUSED(dev);
 
 	/* Update CMSIS variable */
diff --git a/drivers/clock_control/clock_stm32_ll_n6.c b/drivers/clock_control/clock_stm32_ll_n6.c
index 1b44c30230e42..4ae08f0272f9b 100644
--- a/drivers/clock_control/clock_stm32_ll_n6.c
+++ b/drivers/clock_control/clock_stm32_ll_n6.c
@@ -892,9 +892,6 @@ static void set_up_fixed_clock_sources(void)
 	}
 
 	if (IS_ENABLED(STM32_LSE_ENABLED)) {
-		/* Enable the power interface clock */
-		LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
-
 		stm32_backup_domain_enable_access();
 
 		/* Configure driving capability */
diff --git a/drivers/clock_control/clock_stm32_ll_u3.c b/drivers/clock_control/clock_stm32_ll_u3.c
index abda0bf388b1b..dfb367ca981a9 100644
--- a/drivers/clock_control/clock_stm32_ll_u3.c
+++ b/drivers/clock_control/clock_stm32_ll_u3.c
@@ -15,6 +15,7 @@
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/sys/util.h>
 #include <stm32_backup_domain.h>
+#include <stm32_global_periph_clocks.h>
 
 /* Macros to fill up prescaler values */
 #define ahb_prescaler(v) CONCAT(LL_RCC_HCLK_SYSCLK_DIV_, v)
@@ -575,6 +576,8 @@ int stm32_clock_control_init(const struct device *dev)
 
 	ARG_UNUSED(dev);
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	/* Current hclk value */
 	old_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(get_startup_frequency(), LL_RCC_GetAHBPrescaler());
 
@@ -621,6 +624,8 @@ int stm32_clock_control_init(const struct device *dev)
 		LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/* Update CMSIS variable */
 	SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
 
diff --git a/drivers/clock_control/clock_stm32_ll_u5.c b/drivers/clock_control/clock_stm32_ll_u5.c
index d7b69a9b90d05..f1d0703eb4fbb 100644
--- a/drivers/clock_control/clock_stm32_ll_u5.c
+++ b/drivers/clock_control/clock_stm32_ll_u5.c
@@ -19,6 +19,7 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <stm32_backup_domain.h>
+#include <stm32_global_periph_clocks.h>
 
 /* Macros to fill up prescaler values */
 #define z_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
@@ -744,9 +745,6 @@ static void set_up_fixed_clock_sources(void)
 	}
 
 	if (IS_ENABLED(STM32_LSE_ENABLED)) {
-		/* Enable the power interface clock */
-		LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
-
 		stm32_backup_domain_enable_access();
 
 		/* Configure driving capability */
@@ -822,11 +820,6 @@ static void set_up_fixed_clock_sources(void)
 	}
 
 	if (IS_ENABLED(STM32_LSI_ENABLED)) {
-		if (!LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PWR)) {
-			/* Enable the power interface clock */
-			LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
-		}
-
 		stm32_backup_domain_enable_access();
 
 		/* Enable LSI oscillator */
@@ -851,6 +844,9 @@ int stm32_clock_control_init(const struct device *dev)
 
 	ARG_UNUSED(dev);
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
+
 	/* Current hclk value */
 	old_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(get_startup_frequency(), LL_RCC_GetAHBPrescaler());
 
@@ -922,6 +918,8 @@ int stm32_clock_control_init(const struct device *dev)
 		LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/* Update CMSIS variable */
 	SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
 
diff --git a/drivers/clock_control/clock_stm32_ll_wb0.c b/drivers/clock_control/clock_stm32_ll_wb0.c
index 9600fa602281b..785c53129f9aa 100644
--- a/drivers/clock_control/clock_stm32_ll_wb0.c
+++ b/drivers/clock_control/clock_stm32_ll_wb0.c
@@ -21,6 +21,8 @@
 #include <zephyr/arch/common/sys_bitops.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 
+#include <stm32_global_periph_clocks.h>
+
 /* Driver definitions */
 #define RCC_REG(_reg_offset) (DT_REG_ADDR(STM32_CLOCK_CONTROL_NODE) + (_reg_offset))
 #define RADIO_CTRL_IRQn		21	/* Not provided by CMSIS; must be declared manually */
@@ -570,8 +572,11 @@ static void set_up_fixed_clock_sources(void)
 		/* Configure driving capability */
 		LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_CSSWCR_LSEDRV_Pos);
 #endif
+
 		/* Unconditionally disable pull-up & pull-down on LSE pins */
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		LL_PWR_SetNoPullB(LL_PWR_GPIO_BIT_12 | LL_PWR_GPIO_BIT_13);
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 
 		if (IS_ENABLED(STM32_LSE_BYPASS)) {
 			/* Configure LSE bypass */
@@ -716,9 +721,6 @@ int stm32_clock_control_init(const struct device *dev)
 			: LL_FLASH_LATENCY_0
 	);
 
-	/* Unconditionally enable SYSCFG clock for other drivers */
-	LL_APB0_GRP1_EnableClock(LL_APB0_GRP1_PERIPH_SYSCFG);
-
 	/* Set up indiviual enabled clocks */
 	set_up_fixed_clock_sources();
 
diff --git a/drivers/clock_control/clock_stm32_ll_wba.c b/drivers/clock_control/clock_stm32_ll_wba.c
index 1de94493bd55a..79aa10f1a7b6d 100644
--- a/drivers/clock_control/clock_stm32_ll_wba.c
+++ b/drivers/clock_control/clock_stm32_ll_wba.c
@@ -14,6 +14,7 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/__assert.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <stm32_global_periph_clocks.h>
 #include <stm32_backup_domain.h>
 #include <stm32_hsem.h>
 
@@ -345,6 +346,7 @@ static int get_vco_input_range(uint32_t m_div, uint32_t *range)
 
 static void set_regu_voltage(uint32_t hclk_freq)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	if (hclk_freq <= MHZ(16)) {
 		LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
 	} else {
@@ -352,6 +354,7 @@ static void set_regu_voltage(uint32_t hclk_freq)
 	}
 	while (LL_PWR_IsActiveFlag_VOS() == 0) {
 	}
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 }
 
 /*
diff --git a/drivers/clock_control/clock_stm32c0.c b/drivers/clock_control/clock_stm32c0.c
index a20c919c5d9db..e6255f9e8463f 100644
--- a/drivers/clock_control/clock_stm32c0.c
+++ b/drivers/clock_control/clock_stm32c0.c
@@ -21,9 +21,6 @@
  */
 void config_enable_default_clocks(void)
 {
-	/* Enable the power interface clock */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-
 #if IS_ENABLED(STM32_HSI48_CRS_USB_SOF)
 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS);
 	LL_CRS_SetSyncSignalSource(LL_CRS_SYNC_SOURCE_USB);
diff --git a/drivers/clock_control/clock_stm32f0_f3.c b/drivers/clock_control/clock_stm32f0_f3.c
index 2557355a6f419..51354d7600edf 100644
--- a/drivers/clock_control/clock_stm32f0_f3.c
+++ b/drivers/clock_control/clock_stm32f0_f3.c
@@ -144,20 +144,4 @@ uint32_t get_pllout_frequency(void)
  */
 void config_enable_default_clocks(void)
 {
-	/* Enable PWR clock, required to access BDCR and PWR_CR */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-
-#ifndef CONFIG_SOC_SERIES_STM32F3X
-#if defined(CONFIG_EXTI_STM32) || defined(CONFIG_USB_DC_STM32)
-	/* Enable System Configuration Controller clock. */
-	LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
-#endif
-#else
-#if defined(CONFIG_USB_DC_STM32) && defined(SYSCFG_CFGR1_USB_IT_RMP)
-	/* Enable System Configuration Controller clock. */
-	/* SYSCFG is required to remap IRQ to avoid conflicts with CAN */
-	/* cf §14.1.3, RM0316 */
-	LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
-#endif
-#endif /* !CONFIG_SOC_SERIES_STM32F3X */
 }
diff --git a/drivers/clock_control/clock_stm32f1.c b/drivers/clock_control/clock_stm32f1.c
index 752d29aba9f22..ec0a87a28f244 100644
--- a/drivers/clock_control/clock_stm32f1.c
+++ b/drivers/clock_control/clock_stm32f1.c
@@ -169,7 +169,6 @@ void config_enable_default_clocks(void)
 {
 	if (IS_ENABLED(STM32_LSE_ENABLED)) {
 		/* Set the PWREN and BKPEN bits in the RCC_APB1ENR register */
-		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_BKP);
 	}
 }
diff --git a/drivers/clock_control/clock_stm32f2_f4_f7.c b/drivers/clock_control/clock_stm32f2_f4_f7.c
index a7be342a5d9ac..fb971fb2f7bb1 100644
--- a/drivers/clock_control/clock_stm32f2_f4_f7.c
+++ b/drivers/clock_control/clock_stm32f2_f4_f7.c
@@ -17,6 +17,8 @@
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include "clock_stm32_ll_common.h"
 
+#include <stm32_global_periph_clocks.h>
+
 #if defined(STM32_PLL_ENABLED)
 
 /**
@@ -124,6 +126,7 @@ void config_pll_sysclock(void)
 		 */
 		LL_RCC_PLL_Enable();
 
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		/* Set Overdrive if needed before configuring the Flash Latency */
 		LL_PWR_EnableOverDriveMode();
 		while (LL_PWR_IsActiveFlag_OD() != 1) {
@@ -133,6 +136,7 @@ void config_pll_sysclock(void)
 		while (LL_PWR_IsActiveFlag_ODSW() != 1) {
 			/* Wait for OverDrive switch ready */
 		}
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 
 		/* The PLL could still not be locked when returning to the caller
 		 * function. But the caller doesn't know we've turned on the PLL
@@ -264,6 +268,4 @@ void config_pllsai(void)
  */
 void config_enable_default_clocks(void)
 {
-	/* Power Interface clock enabled by default */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 }
diff --git a/drivers/clock_control/clock_stm32g0_u0.c b/drivers/clock_control/clock_stm32g0_u0.c
index f337ad739ae13..c916fa0b74510 100644
--- a/drivers/clock_control/clock_stm32g0_u0.c
+++ b/drivers/clock_control/clock_stm32g0_u0.c
@@ -108,9 +108,6 @@ uint32_t get_ck48_frequency(void)
  */
 void config_enable_default_clocks(void)
 {
-	/* Enable the power interface clock */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-
 #if defined(CRS)
 	if (IS_ENABLED(STM32_HSI48_CRS_USB_SOF)) {
 		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS);
diff --git a/drivers/clock_control/clock_stm32g4.c b/drivers/clock_control/clock_stm32g4.c
index a3c1727794109..c6b385cd87dfc 100644
--- a/drivers/clock_control/clock_stm32g4.c
+++ b/drivers/clock_control/clock_stm32g4.c
@@ -16,6 +16,8 @@
 #include <zephyr/sys/time_units.h>
 #include "clock_stm32_ll_common.h"
 
+#include <stm32_global_periph_clocks.h>
+
 #if defined(STM32_PLL_ENABLED)
 
 /**
@@ -59,7 +61,9 @@ void config_pll_sysclock(void)
 {
 	/* set power boost mode for sys clock greater than 150MHz */
 	if (sys_clock_hw_cycles_per_sec() >= MHZ(150)) {
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		LL_PWR_EnableRange1BoostMode();
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 	}
 
 	LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
@@ -77,6 +81,4 @@ void config_pll_sysclock(void)
  */
 void config_enable_default_clocks(void)
 {
-	/* Enable the power interface clock */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 }
diff --git a/drivers/clock_control/clock_stm32l0_l1.c b/drivers/clock_control/clock_stm32l0_l1.c
index dc6b3adbcf351..59e395d6f0cc3 100644
--- a/drivers/clock_control/clock_stm32l0_l1.c
+++ b/drivers/clock_control/clock_stm32l0_l1.c
@@ -16,6 +16,8 @@
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include "clock_stm32_ll_common.h"
 
+#include <stm32_global_periph_clocks.h>
+
 #if defined(STM32_PLL_ENABLED)
 
 /* Macros to fill up multiplication and division factors values */
@@ -91,6 +93,8 @@ uint32_t get_pllout_frequency(void)
  */
 void config_regulator_voltage(uint32_t hclk_freq)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	if (hclk_freq <= MHZ(4.2)) {
 		LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE3);
 	} else if (hclk_freq <= MHZ(16)) {
@@ -100,6 +104,8 @@ void config_regulator_voltage(uint32_t hclk_freq)
 	}
 	while (LL_PWR_IsActiveFlag_VOS() == 1) {
 	}
+
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 }
 
 /**
@@ -107,11 +113,4 @@ void config_regulator_voltage(uint32_t hclk_freq)
  */
 void config_enable_default_clocks(void)
 {
-#if defined(CONFIG_EXTI_STM32) || defined(CONFIG_USB_DC_STM32) || \
-	(defined(CONFIG_SOC_SERIES_STM32L0X) &&			  \
-	 defined(CONFIG_ENTROPY_STM32_RNG))
-	/* Enable System Configuration Controller clock. */
-	LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
-#endif
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 }
diff --git a/drivers/clock_control/clock_stm32l4_l5_wb_wl.c b/drivers/clock_control/clock_stm32l4_l5_wb_wl.c
index aec6a892b3a32..690abbf0fa59e 100644
--- a/drivers/clock_control/clock_stm32l4_l5_wb_wl.c
+++ b/drivers/clock_control/clock_stm32l4_l5_wb_wl.c
@@ -17,6 +17,8 @@
 #include <zephyr/sys/time_units.h>
 #include "clock_stm32_ll_common.h"
 
+#include <stm32_global_periph_clocks.h>
+
 #if defined(STM32_PLL_ENABLED) || defined(STM32_PLLSAI1_ENABLED) || defined(STM32_PLLSAI2_ENABLED)
 
 #if defined(LL_RCC_MSIRANGESEL_RUN)
@@ -76,7 +78,9 @@ void config_pll_sysclock(void)
 #ifdef PWR_CR5_R1MODE
 	/* set power boost mode for sys clock greater than 80MHz */
 	if (sys_clock_hw_cycles_per_sec() >= MHZ(80)) {
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		LL_PWR_EnableRange1BoostMode();
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 	}
 #endif /* PWR_CR5_R1MODE */
 
@@ -291,10 +295,6 @@ void config_pllsai2(void)
  */
 void config_enable_default_clocks(void)
 {
-#ifdef LL_APB1_GRP1_PERIPH_PWR
-	/* Enable the power interface clock */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-#endif
 #if defined(CONFIG_SOC_SERIES_STM32WBX)
 	/* HW semaphore Clock enable */
 	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM);
diff --git a/drivers/flash/flash_stm32_xspi.c b/drivers/flash/flash_stm32_xspi.c
index feef05889f271..9c399ed815dbe 100644
--- a/drivers/flash/flash_stm32_xspi.c
+++ b/drivers/flash/flash_stm32_xspi.c
@@ -25,6 +25,8 @@
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/irq.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include "spi_nor.h"
 #include "jesd216.h"
 
@@ -2118,9 +2120,13 @@ static int flash_stm32_xspi_init(const struct device *dev)
 		return -ENOTSUP;
 	}
 #if defined(CONFIG_SOC_SERIES_STM32H7RSX)
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
 	LL_PWR_EnableXSPIM2();
 	__HAL_RCC_SBS_CLK_ENABLE();
 	LL_SBS_EnableXSPI2SpeedOptim();
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 #endif /* CONFIG_SOC_SERIES_STM32H7RSX */
 
 	/* Signals configuration */
diff --git a/drivers/flash/flash_stm32g4x.c b/drivers/flash/flash_stm32g4x.c
index 50e62f0e2f66a..6be281a6b2c06 100644
--- a/drivers/flash/flash_stm32g4x.c
+++ b/drivers/flash/flash_stm32g4x.c
@@ -19,6 +19,8 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
 #include <stm32_bitops.h>
 #include <stm32_ll_system.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include "flash_stm32.h"
 
 #define STM32G4_SERIES_MAX_FLASH	512
@@ -167,8 +169,11 @@ static int erase_page(const struct device *dev, unsigned int offset)
 
 #if defined(FLASH_STM32_DBANK)
 	bool bank_swap;
+
 	/* Check whether bank1/2 are swapped */
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
 	bank_swap = (LL_SYSCFG_GetFlashBankMode() == LL_SYSCFG_BANKMODE_BANK2);
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
 
 	if ((offset < (FLASH_SIZE / 2)) && !bank_swap) {
 		/* The pages to be erased is in bank 1 */
diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c
index fe12d9ea8f7b0..44bdc0917b7a5 100644
--- a/drivers/gpio/gpio_stm32.c
+++ b/drivers/gpio/gpio_stm32.c
@@ -13,6 +13,7 @@
 #include <zephyr/device.h>
 #include <soc.h>
 #include <stm32_bitops.h>
+#include <stm32_global_periph_clocks.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_exti.h>
 #include <stm32_ll_gpio.h>
@@ -180,6 +181,7 @@ static inline void ll_gpio_set_pin_pull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3
 #if defined(CONFIG_SOC_SERIES_STM32WB0X)
 	/* On STM32WB0, the PWRC PU/PD control registers should be used instead
 	 * of the GPIO controller registers, so we cannot use LL_GPIO_SetPinPull.
+	 * N.B.: PWRC clock is always-on so clock enablement helpers aren't used.
 	 */
 	const uint32_t gpio = (GPIOx == GPIOA) ? LL_PWR_GPIO_A : LL_PWR_GPIO_B;
 
@@ -203,6 +205,7 @@ __maybe_unused static inline uint32_t ll_gpio_get_pin_pull(GPIO_TypeDef *GPIOx,
 #if defined(CONFIG_SOC_SERIES_STM32WB0X)
 	/* On STM32WB0, the PWRC PU/PD control registers should be used instead
 	 * of the GPIO controller registers, so we cannot use LL_GPIO_GetPinPull.
+	 * N.B.: PWRC clock is always-on so clock enablement helpers aren't used.
 	 */
 	const uint32_t gpio = (GPIOx == GPIOA) ? LL_PWR_GPIO_A : LL_PWR_GPIO_B;
 
@@ -725,11 +728,14 @@ __maybe_unused static int gpio_stm32_init(const struct device *dev)
 	z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
 	/* Port G[15:2] requires external power supply */
 	/* Cf: L4/L5/U3 RM, Chapter "Independent I/O supply rail" */
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 #ifdef CONFIG_SOC_SERIES_STM32U3X
 	LL_PWR_EnableVDDIO2();
 #else
 	LL_PWR_EnableVddIO2();
+
 #endif
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 	z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
 #endif
 
diff --git a/drivers/hwinfo/hwinfo_stm32.c b/drivers/hwinfo/hwinfo_stm32.c
index b224107ec72ae..b65679e9a87f0 100644
--- a/drivers/hwinfo/hwinfo_stm32.c
+++ b/drivers/hwinfo/hwinfo_stm32.c
@@ -6,6 +6,7 @@
 
 #include <soc.h>
 #include <stm32_bitops.h>
+#include <stm32_global_periph_clocks.h>
 #include <stm32_ll_utils.h>
 #include <stm32_ll_rcc.h>
 #if defined(CONFIG_SOC_SERIES_STM32H5X)
@@ -157,6 +158,8 @@ int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
 	}
 #endif
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 #if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM4)
 	if (LL_PWR_CPU2_IsActiveFlag_SB()) {
 		flags |= RESET_LOW_POWER_WAKE;
@@ -187,6 +190,8 @@ int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
 	}
 #endif /* PWR_FLAG_SB */
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	*cause = flags;
 
 	return 0;
@@ -196,6 +201,8 @@ int z_impl_hwinfo_clear_reset_cause(void)
 {
 	LL_RCC_ClearResetFlags();
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 #if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM4)
 	LL_PWR_ClearFlag_CPU2();
 #elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CORE_CM7)
@@ -216,6 +223,8 @@ int z_impl_hwinfo_clear_reset_cause(void)
 	LL_PWR_ClearFlag_SB();
 #endif /* PWR_FLAG_SB */
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	return 0;
 }
 
diff --git a/drivers/ieee802154/ieee802154_stm32wba.c b/drivers/ieee802154/ieee802154_stm32wba.c
index 5f1714a213cc4..b7cb401f95539 100644
--- a/drivers/ieee802154/ieee802154_stm32wba.c
+++ b/drivers/ieee802154/ieee802154_stm32wba.c
@@ -38,6 +38,8 @@
 #include "ieee802154_stm32wba.h"
 #include <stm32wba_802154_intf.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #define DT_DRV_COMPAT st_stm32wba_ieee802154
 
 #define LOG_MODULE_NAME ieee802154_stm32wba
@@ -992,6 +994,8 @@ static int radio_pm_action(const struct device *dev, enum pm_device_action actio
 	case PM_DEVICE_ACTION_RESUME:
 		LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_RADIO);
 #if defined(CONFIG_PM_S2RAM)
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 		if (LL_PWR_IsActiveFlag_SB() == 1U) {
 			/* Put the radio in active state */
 			LL_AHB5_GRP1_EnableClock(LL_AHB5_GRP1_PERIPH_RADIO);
@@ -999,6 +1003,8 @@ static int radio_pm_action(const struct device *dev, enum pm_device_action actio
 		}
 		LINKLAYER_PLAT_NotifyWFIExit();
 		ll_sys_dp_slp_exit();
+
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 #endif
 		break;
 	case PM_DEVICE_ACTION_SUSPEND:
diff --git a/drivers/interrupt_controller/intc_gpio_stm32.c b/drivers/interrupt_controller/intc_gpio_stm32.c
index 6f55cf7750f49..01534c35dc8f0 100644
--- a/drivers/interrupt_controller/intc_gpio_stm32.c
+++ b/drivers/interrupt_controller/intc_gpio_stm32.c
@@ -26,6 +26,8 @@
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/irq.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include "stm32_hsem.h"
 #include "intc_exti_stm32_priv.h"
 
@@ -296,6 +298,7 @@ void stm32_exti_set_line_src_port(gpio_pin_t line, uint32_t port)
 #endif
 
 	z_stm32_hsem_lock(CFG_HW_EXTI_SEMID, HSEM_LOCK_DEFAULT_RETRY);
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
 
 #ifdef CONFIG_SOC_SERIES_STM32F1X
 	LL_GPIO_AF_SetEXTISource(port, ll_line);
@@ -309,6 +312,7 @@ void stm32_exti_set_line_src_port(gpio_pin_t line, uint32_t port)
 #else
 	LL_SYSCFG_SetEXTISource(port, ll_line);
 #endif
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
 	z_stm32_hsem_unlock(CFG_HW_EXTI_SEMID);
 }
 
@@ -317,6 +321,8 @@ uint32_t stm32_exti_get_line_src_port(gpio_pin_t line)
 	uint32_t ll_line = stm32_exti_linenum_to_src_cfg_line(line);
 	uint32_t port;
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
+
 #ifdef CONFIG_SOC_SERIES_STM32F1X
 	port = LL_GPIO_AF_GetEXTISource(ll_line);
 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti)
@@ -329,6 +335,8 @@ uint32_t stm32_exti_get_line_src_port(gpio_pin_t line)
 	port = LL_SYSCFG_GetEXTISource(ll_line);
 #endif
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
+
 #if defined(CONFIG_SOC_SERIES_STM32L0X) && defined(LL_SYSCFG_EXTI_PORTH)
 	/*
 	 * Ports F and G are not present on some STM32L0 parts, so
diff --git a/drivers/lora/loramac_node/sx126x_stm32wl.c b/drivers/lora/loramac_node/sx126x_stm32wl.c
index c6a484ab34f69..372c25aaa50e3 100644
--- a/drivers/lora/loramac_node/sx126x_stm32wl.c
+++ b/drivers/lora/loramac_node/sx126x_stm32wl.c
@@ -12,6 +12,8 @@
 #include <stm32wlxx_ll_pwr.h>
 #include <stm32wlxx_ll_rcc.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
 LOG_MODULE_DECLARE(sx126x, CONFIG_LORA_LOG_LEVEL);
@@ -31,7 +33,13 @@ void sx126x_reset(struct sx126x_data *dev_data)
 
 bool sx126x_is_busy(struct sx126x_data *dev_data)
 {
-	return LL_PWR_IsActiveFlag_RFBUSYS();
+	bool busy;
+
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+	busy = LL_PWR_IsActiveFlag_RFBUSYS();
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
+	return busy;
 }
 
 uint32_t sx126x_get_dio1_pin_state(struct sx126x_data *dev_data)
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 5ac3b1d3ff762..25882b7d4c78b 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -13,6 +13,8 @@
 #include <zephyr/pm/device_runtime.h>
 #include <gpio/gpio_stm32.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <stm32_ll_bus.h>
 #include <stm32_ll_gpio.h>
 #include <stm32_ll_system.h>
@@ -101,13 +103,14 @@ int stm32_pinmux_init_remap(void)
 #error "Pin remap property available only on STM32G0 and STM32C0 SoC series"
 #endif
 
-	LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
 #if REMAP_PA11
 	LL_SYSCFG_EnablePinRemap(LL_SYSCFG_PIN_RMP_PA11);
 #endif
 #if REMAP_PA12
 	LL_SYSCFG_EnablePinRemap(LL_SYSCFG_PIN_RMP_PA12);
 #endif
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
 
 #elif REMAP_PA11_PA12
 
@@ -115,8 +118,9 @@ int stm32_pinmux_init_remap(void)
 #error "Pin remap property available only on STM32F070x SoC series"
 #endif
 
-	LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
 	LL_SYSCFG_EnablePinRemap();
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
 
 #endif /* (REMAP_PA11 || REMAP_PA12) || REMAP_PA11_PA12 */
 
diff --git a/drivers/serial/uart_stm32.c b/drivers/serial/uart_stm32.c
index f5f62635cc612..6936b33d20e31 100644
--- a/drivers/serial/uart_stm32.c
+++ b/drivers/serial/uart_stm32.c
@@ -47,6 +47,8 @@
 #include <zephyr/mem_mgmt/mem_attr.h>
 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
 LOG_MODULE_REGISTER(uart_stm32, CONFIG_UART_LOG_LEVEL);
@@ -133,7 +135,9 @@ static void uart_stm32_pm_enable_wakeup_line(uint32_t wakeup_line)
 	 * If SoC is equipped with LPUART instance,
 	 * enable the associated wake-up line in PWRC.
 	 */
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	LL_PWR_EnableInternWU2();
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 #endif /* PWR_CR3_EIWL2 */
 #else
 	if (wakeup_line != STM32_WAKEUP_LINE_NONE) {
diff --git a/drivers/spi/spi_ll_stm32.c b/drivers/spi/spi_ll_stm32.c
index de3f2b48b68eb..647616b59e54a 100644
--- a/drivers/spi/spi_ll_stm32.c
+++ b/drivers/spi/spi_ll_stm32.c
@@ -472,11 +472,13 @@ static void spi_stm32_cs_control(const struct device *dev, bool on __maybe_unuse
 	const struct spi_stm32_config *cfg = dev->config;
 
 	if (cfg->use_subghzspi_nss) {
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		if (on) {
 			LL_PWR_SelectSUBGHZSPI_NSS();
 		} else {
 			LL_PWR_UnselectSUBGHZSPI_NSS();
 		}
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 	}
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_spi_subghz) */
 }
diff --git a/drivers/usb/device/usb_dc_stm32.c b/drivers/usb/device/usb_dc_stm32.c
index 8409cd85afa54..ad5802921ecc1 100644
--- a/drivers/usb/device/usb_dc_stm32.c
+++ b/drivers/usb/device/usb_dc_stm32.c
@@ -25,8 +25,11 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/pinctrl.h>
+
+#include <stm32_global_periph_clocks.h>
 #include "stm32_hsem.h"
 
+
 #define LOG_LEVEL CONFIG_USB_DRIVER_LOG_LEVEL
 #include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
@@ -301,12 +304,7 @@ static int usb_dc_stm32_phy_specific_clock_enable(const struct device *const clk
 {
 	int err;
 
-	/* Sequence to enable the power of the OTG HS on a stm32U5 serie : Enable VDDUSB */
-	bool pwr_clk = LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PWR);
-
-	if (!pwr_clk) {
-		LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
-	}
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 
 	/* Check that power range is 1 or 2 */
 	if (LL_PWR_GetRegulVoltageScaling() < LL_PWR_REGU_VOLTAGE_SCALE2) {
@@ -323,12 +321,10 @@ static int usb_dc_stm32_phy_specific_clock_enable(const struct device *const clk
 	}
 
 	/* Leave the PWR clock in its initial position */
-	if (!pwr_clk) {
-		LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PWR);
-	}
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 
 	/* Set the OTG PHY reference clock selection (through SYSCFG) block */
-	LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_SYSCFG);
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
 
 	err = usb_dc_stm32u5_phy_clock_enable(clk);
 	if (err) {
@@ -338,6 +334,8 @@ static int usb_dc_stm32_phy_specific_clock_enable(const struct device *const clk
 	/* Configuring the SYSCFG registers OTG_HS PHY : OTG_HS PHY enable*/
 	HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
+
 	if (clock_control_on(clk, (clock_control_subsys_t)&pclken[0]) != 0) {
 		LOG_ERR("Unable to enable USB clock");
 		return -EIO;
@@ -350,6 +348,7 @@ static int usb_dc_stm32_phy_specific_clock_enable(const struct device *const clk
 
 static int usb_dc_stm32_phy_specific_clock_enable(const struct device *const clk)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 #if defined(PWR_USBSCR_USB33SV) || defined(PWR_SVMCR_USV)
 	/*
 	 * VDDUSB independent USB supply (PWR clock is on)
@@ -365,6 +364,7 @@ static int usb_dc_stm32_phy_specific_clock_enable(const struct device *const clk
 	/* Enable VDDUSB */
 	LL_PWR_EnableVddUSB();
 #endif
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 
 	if (DT_INST_NUM_CLOCKS(0) > 1) {
 		if (clock_control_configure(clk, (clock_control_subsys_t)&pclken[1],
@@ -532,6 +532,7 @@ static int usb_dc_stm32_init(void)
 	LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI);
 #endif
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	LL_PWR_EnableUSBVoltageDetector();
 
 	/* Per AN2606: USBREGEN not supported when running in FS mode. */
@@ -540,6 +541,7 @@ static int usb_dc_stm32_init(void)
 		LOG_INF("PWR not active yet");
 		k_sleep(K_MSEC(100));
 	}
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 #endif
 
 #if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_otghs)
@@ -624,12 +626,9 @@ int usb_dc_attach(void)
 	 * Remap IRQ by default to enable use of both IPs simultaneoulsy
 	 * This should be done before calling any HAL function
 	 */
-	if (LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SYSCFG)) {
-		LL_SYSCFG_EnableRemapIT_USB();
-	} else {
-		LOG_ERR("System Configuration Controller clock is "
-			"disabled. Unable to enable IRQ remapping.");
-	}
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
+	LL_SYSCFG_EnableRemapIT_USB();
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
 #endif
 
 #if USB_OTG_HS_ULPI_PHY
@@ -662,17 +661,9 @@ int usb_dc_attach(void)
 	 * DM00310109.
 	 */
 #ifdef PWR_CR2_USV
-#if defined(LL_APB1_GRP1_PERIPH_PWR)
-	if (LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_PWR)) {
-		LL_PWR_EnableVddUSB();
-	} else {
-		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-		LL_PWR_EnableVddUSB();
-		LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_PWR);
-	}
-#else
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	LL_PWR_EnableVddUSB();
-#endif /* defined(LL_APB1_GRP1_PERIPH_PWR) */
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 #endif /* PWR_CR2_USV */
 
 	return 0;
diff --git a/drivers/usb/udc/udc_stm32.c b/drivers/usb/udc/udc_stm32.c
index c39d9596c8d58..ab4da22959410 100644
--- a/drivers/usb/udc/udc_stm32.c
+++ b/drivers/usb/udc/udc_stm32.c
@@ -21,6 +21,8 @@
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/sys/util.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include "udc_common.h"
 
 #include <zephyr/logging/log.h>
@@ -1257,6 +1259,7 @@ static int priv_clock_enable(void)
 	}
 
 	/* Power configuration */
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 #if defined(CONFIG_SOC_SERIES_STM32H7X)
 	LL_PWR_EnableUSBVoltageDetector();
 
@@ -1325,6 +1328,7 @@ static int priv_clock_enable(void)
 	 */
 	LL_PWR_EnableVDDUSB();
 #endif
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 
 	if (DT_INST_NUM_CLOCKS(0) > 1) {
 		if (clock_control_configure(clk, &pclken[1], NULL) != 0) {
@@ -1388,7 +1392,7 @@ static int priv_clock_enable(void)
 	const uint32_t hsphy_clknum = DT_NUM_CLOCKS(DT_NODELABEL(otghs_phy));
 
 	/* Configure OTG PHY reference clock through SYSCFG */
-	__HAL_RCC_SYSCFG_CLK_ENABLE();
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
 
 	HAL_SYSCFG_SetOTGPHYReferenceClockSelection(
 		syscfg_otg_hs_phy_clk[DT_ENUM_IDX(DT_NODELABEL(otghs_phy), clock_reference)]
@@ -1397,6 +1401,8 @@ static int priv_clock_enable(void)
 	/* De-assert reset and enable clock of OTG PHY */
 	HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
+
 	if (hsphy_clknum > 1) {
 		if (clock_control_configure(clk, (void *)&hsphy_clk[1], NULL) != 0) {
 			LOG_ERR("Failed OTGHS PHY mux configuration");
@@ -1572,12 +1578,9 @@ static int udc_stm32_driver_init0(const struct device *dev)
 	 * Remap IRQ by default to enable use of both IPs simultaneoulsy
 	 * This should be done before calling any HAL function
 	 */
-	if (LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SYSCFG)) {
-		LL_SYSCFG_EnableRemapIT_USB();
-	} else {
-		LOG_ERR("System Configuration Controller clock is "
-			"disabled. Unable to enable IRQ remapping.");
-	}
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
+	LL_SYSCFG_EnableRemapIT_USB();
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
 #endif
 
 #if UDC_STM32_NODE_PHY_ITFACE(DT_DRV_INST(0)) == PCD_PHY_ULPI
@@ -1600,17 +1603,9 @@ static int udc_stm32_driver_init0(const struct device *dev)
 	 * DM00310109.
 	 */
 #ifdef PWR_CR2_USV
-#if defined(LL_APB1_GRP1_PERIPH_PWR)
-	if (LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_PWR)) {
-		LL_PWR_EnableVddUSB();
-	} else {
-		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-		LL_PWR_EnableVddUSB();
-		LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_PWR);
-	}
-	#else
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	LL_PWR_EnableVddUSB();
-#endif /* defined(LL_APB1_GRP1_PERIPH_PWR) */
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 #endif /* PWR_CR2_USV */
 
 	return 0;
diff --git a/samples/boards/st/power_mgmt/stop3/src/main.c b/samples/boards/st/power_mgmt/stop3/src/main.c
index 5a76f8d587681..0c5b5a09413b2 100644
--- a/samples/boards/st/power_mgmt/stop3/src/main.c
+++ b/samples/boards/st/power_mgmt/stop3/src/main.c
@@ -11,6 +11,7 @@
 #include <zephyr/sys/printk.h>
 #include <stm32u5xx_ll_pwr.h>
 #include <gpio/gpio_stm32.h>
+#include <stm32_global_periph_clocks.h>
 
 #define SLEEP_TIME_MS   2000
 
@@ -36,6 +37,7 @@ int main(void)
 	 * This configuration is active only in STOP3 mode, so no need to disable it
 	 * during wake up
 	 */
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR); //keep pwrc enabled forever
 	LL_PWR_EnablePUPDConfig();
 
 	while (true) {
diff --git a/soc/st/stm32/Kconfig b/soc/st/stm32/Kconfig
index 812e4fb1c889d..93a4adc770f4d 100644
--- a/soc/st/stm32/Kconfig
+++ b/soc/st/stm32/Kconfig
@@ -131,4 +131,31 @@ config STM32_APP_IN_EXT_FLASH
 	  in external Flash and is chainloaded with MCUboot.
 	  Whether the app is eXecuted in Place (XiP) depends on the MCUboot mode used.
 
+config STM32_GLOBAL_CLOCKS_ALWAYS_ON_MASK
+	def_int 0
+	help
+	  Bitmask of clocks that are always enabled and don't need to be
+	  managed by the framework. This is SoC-specific and only has an
+	  effect when CONFIG_STM32_GLOBAL_CLOCKS_RUNTIME_GATING=y
+
+	  Bit N corresponds to global peripheral with ID=N.
+	  Refer to "stm32_global_periph_clocks.h" for which IDs correspond
+	  to what peripheral.
+
+
+config STM32_GLOBAL_CLOCKS_RUNTIME_GATING
+	bool "Enable runtime clock gating for global clocks"
+	default y
+	help
+	  When enabled, usage of clocks for global/system peripherals is
+	  reference-counted to ensure peripherals such as PWR or SYSCFG
+	  are only clocked when used which reduces the power consumption.
+	  This slightly increases the application footprint, and also makes
+	  certain operations slightly slower.
+
+	  When disabled, clocks for global/system peripherals are turned on
+	  during boot and remain active for the application lifetime, which
+	  increases power consumption but slightly decreases footprint and
+	  avoids runtime overhead.
+
 endif # SOC_FAMILY_STM32
diff --git a/soc/st/stm32/common/CMakeLists.txt b/soc/st/stm32/common/CMakeLists.txt
index e2cf58df9d7bf..cc48f4d1a841e 100644
--- a/soc/st/stm32/common/CMakeLists.txt
+++ b/soc/st/stm32/common/CMakeLists.txt
@@ -5,6 +5,7 @@ zephyr_include_directories(.)
 zephyr_sources(
 	stm32cube_hal.c
 	soc_config.c
+  stm32_global_periph_clocks.c
 )
 
 if(DEFINED CONFIG_STM32_CCM)
diff --git a/soc/st/stm32/common/stm32_backup_domain.c b/soc/st/stm32/common/stm32_backup_domain.c
index c77b8493b98a1..523b3cdf56214 100644
--- a/soc/st/stm32/common/stm32_backup_domain.c
+++ b/soc/st/stm32/common/stm32_backup_domain.c
@@ -7,6 +7,7 @@
 #include <stm32_ll_pwr.h>
 #include <zephyr/spinlock.h>
 #include <zephyr/logging/log.h>
+#include <stm32_global_periph_clocks.h>
 #include <stm32_backup_domain.h>
 #include <stddef.h>
 
@@ -30,9 +31,11 @@ void stm32_backup_domain_enable_access(void)
 	k_spinlock_key_t key = k_spin_lock(&lock);
 
 	if (refcount == 0U) {
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		ENABLE_BKUP_ACCESS();
 		while (!IS_ENABLED_BKUP_ACCESS()) {
 		}
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 	}
 	refcount++;
 
@@ -47,7 +50,9 @@ void stm32_backup_domain_disable_access(void)
 		LOG_WRN_ONCE("Unbalanced backup domain access refcount");
 	} else {
 		if (refcount == 1U) {
+			stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 			DISABLE_BKUP_ACCESS();
+			stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 		}
 		refcount--;
 	}
diff --git a/soc/st/stm32/common/stm32_backup_sram.c b/soc/st/stm32/common/stm32_backup_sram.c
index 2d1c86b3f146e..e47fa8311da85 100644
--- a/soc/st/stm32/common/stm32_backup_sram.c
+++ b/soc/st/stm32/common/stm32_backup_sram.c
@@ -13,6 +13,7 @@
 #include <stm32_ll_pwr.h>
 
 #include <stm32_backup_domain.h>
+#include <stm32_global_periph_clocks.h>
 
 LOG_MODULE_REGISTER(stm32_backup_sram, CONFIG_SOC_LOG_LEVEL);
 
@@ -46,9 +47,11 @@ static int stm32_backup_sram_init(const struct device *dev)
 	/* enable backup sram regulator (required to retain backup SRAM content
 	 * while in standby or VBAT modes).
 	 */
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	LL_PWR_EnableBkUpRegulator();
 	while (!LL_PWR_IsEnabledBkUpRegulator()) {
 	}
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 
 	return 0;
 }
diff --git a/soc/st/stm32/common/stm32_global_periph_clocks.c b/soc/st/stm32/common/stm32_global_periph_clocks.c
new file mode 100644
index 0000000000000..41d03769d6746
--- /dev/null
+++ b/soc/st/stm32/common/stm32_global_periph_clocks.c
@@ -0,0 +1,133 @@
+/**
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Clocks manager for global/system IPs
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/spinlock.h>
+#include <zephyr/sys/util.h>
+
+#include <zephyr/drivers/clock_control/stm32_clock_control.h>
+
+#include <stm32_ll_bus.h>
+
+#include "stm32_global_periph_clocks.h"
+
+/**
+ * TODO: use Clock Control API
+ *
+ * NOTE: &exti for SYSCFG clock
+ *       &pwr for PWR clock
+ * to be reviewed
+ */
+
+/*
+ * This routine is used by the enable path when runtime gating is enabled,
+ * and the enable-clocks-of-everyone when runtime gating is disabled, so
+ * it is compiled unconditionally.
+ */
+static void enable_periph_clock_gate(enum stm32_global_peripheral_id periph_id)
+{
+	switch (periph_id) {
+	case STM32_GLOBAL_PERIPH_PWR:
+#if defined(CONFIG_SOC_SERIES_STM32N6X) || defined(CONFIG_SOC_SERIES_STM32WBAX)
+	LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
+#elif defined(CONFIG_SOC_SERIES_STM32U3X)
+	LL_AHB1_GRP2_EnableClock(LL_AHB1_GRP2_PERIPH_PWR);
+#elif defined(CONFIG_SOC_SERIES_STM32U5X)
+	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
+#else
+	/* TODO: some series don't need this! */
+	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+#endif /* ... */
+
+	case STM32_GLOBAL_PERIPH_SYSCFG:
+#if defined(CONFIG_SOC_SERIES_STM32H7X)
+	LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
+#elif defined(CONFIG_SOC_SERIES_STM32C0X) || defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32U0X)
+	LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
+#elif defined(CONFIG_SOC_SERIES_STM32MP1) || defined(CONFIG_SOC_SERIES_STM32MP13X) || defined(CONFIG_SOC_SERIES_STM32U3X) || defined(CONFIG_SOC_SERIES_STM32U5X)
+	LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_SYSCFG);
+#elif defined(CONFIG_SOC_SERIES_STM32WBAX)
+	LL_APB7_GRP1_EnableClock(LL_APB7_GRP1_PERIPH_SYSCFG);
+#elif defined(CONFIG_SOC_SERIES_STM32WB0X)
+	LL_APB0_GRP1_EnableClock(LL_APB0_GRP1_PERIPH_SYSCFG);
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+	LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG);
+#elif defined(CONFIG_SOC_SERIES_STM32H5X)
+	LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_SBS);
+#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
+	LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SBS);
+#else
+	LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
+#endif /* ... */
+
+	default:
+		__ASSERT_NO_MSG(0);
+	}
+}
+
+#if !defined(CONFIG_STM32_GLOBAL_CLOCKS_RUNTIME_GATING)
+
+int stm32_global_periph_enable_all_clocks(void)
+{
+	for (int i = 0; i < STM32_GLOBAL_PERIPH_NUM; i++) {
+		enable_periph_clock_gate((enum stm32_global_peripheral_id)i);
+	}
+}
+
+/** TODO: invoke from RCC for proper ordering. for now this is a SYS_INIT() */
+//TODO: sys_init
+
+#else /* CONFIG_STM32_GLOBAL_CLOCKS_RUNTIME_GATING */
+
+static uint8_t periphs_refcount[STM32_GLOBAL_PERIPH_NUM];
+static struct k_spinlock refcounts_lock;
+
+static void disable_periph_clock_gate(enum stm32_global_peripheral_id periph_id)
+{
+	/** TODO: */
+}
+
+void _stm32_global_periph_refer(enum stm32_global_peripheral_id periph_id)
+{
+	__ASSERT(IN_RANGE(periph_id, 0, STM32_GLOBAL_PERIPH_NUM - 1),
+		"Invalid peripheral ID %d", periph_id);
+
+	K_SPINLOCK(&refcounts_lock) {
+		__ASSERT(periphs_refcount[periph_id] < UINT8_MAX,
+			"Too many enable() calls for peripheral with ID=%d", periph_id);
+
+		uint8_t old_refcount = periphs_refcount[periph_id];
+
+		periphs_refcount[periph_id] += 1;
+
+		if (old_refcount == 0U) {
+			enable_periph_clock_gate(periph_id);
+		}
+	}
+}
+
+void _stm32_global_periph_release(enum stm32_global_peripheral_id periph_id)
+{
+	__ASSERT(IN_RANGE(periph_id, 0, STM32_GLOBAL_PERIPH_NUM - 1),
+		"Invalid peripheral ID %d", periph_id);
+
+	K_SPINLOCK(&refcounts_lock) {
+		__ASSERT(periphs_refcount[periph_id] > 0,
+			"Too many disable() calls for peripheral with ID=%d", periph_id);
+
+		uint8_t new_refcount = --periphs_refcount[periph_id];
+
+		if (new_refcount == 0U) {
+			disable_periph_clock_gate(periph_id);
+		}
+	}
+}
+
+#endif /* !CONFIG_STM32_GLOBAL_CLOCKS_RUNTIME_GATING */
diff --git a/soc/st/stm32/common/stm32_global_periph_clocks.h b/soc/st/stm32/common/stm32_global_periph_clocks.h
new file mode 100644
index 0000000000000..5cb0fd08e0150
--- /dev/null
+++ b/soc/st/stm32/common/stm32_global_periph_clocks.h
@@ -0,0 +1,106 @@
+
+#ifndef ZEPHYR_INCLUDE_SOC_ST_STM32_GLOBAL_PERIPH_CLOCKS_H_
+#define ZEPHYR_INCLUDE_SOC_ST_STM32_GLOBAL_PERIPH_CLOCKS_H_
+
+#include <soc.h>
+#include <zephyr/kernel.h>
+
+/**
+ * Global peripheral identifier
+ *
+ * @internal
+ * Keep the list in increasing order starting from zero.
+ * The list must not go over 32 entries (0~31).
+ * @endinternal
+ */
+enum stm32_global_peripheral_id {
+	/** Power controller */
+	STM32_GLOBAL_PERIPH_PWR = 0,
+
+	/**
+	 * System Configuration controller
+	 *
+	 * This controller is called SBS instead on certain series.
+	 */
+	STM32_GLOBAL_PERIPH_SYSCFG,
+
+	STM32_GLOBAL_PERIPH_NUM,
+};
+
+#if defined(CONFIG_STM32_GLOBAL_CLOCKS_RUNTIME_GATING)
+/*
+ * When runtime clock gating is enabled, the RCC callback used
+ * to enable all global peripheral clocks becomes a no-op.
+ */
+#define stm32_global_periph_enable_all_clocks(...)
+
+/**
+ * @brief Add reference to global peripheral @p periph_id
+ *
+ * After a call to this function, the clock of @p periph_id
+ * is guaranteed to be enabled and its registers can be
+ * accessed.
+ *
+ * @internal
+ * If the current reference count for @p periph_id is 0,
+ * the corresponding clock is enabled; then, the reference
+ * count for @p periph_id is incremented unconditionally.
+ * @endinternal
+ */
+static inline void stm32_global_periph_refer(enum stm32_global_peripheral_id periph_id) {
+	extern void _stm32_global_periph_refer(enum stm32_global_peripheral_id periph_id);
+
+	if (CONFIG_STM32_GLOBAL_CLOCKS_ALWAYS_ON_MASK & (1U << (unsigned int)periph_id)) {
+		/* Don't do anything for always-on clocks */
+		return;
+	}
+
+	_stm32_global_periph_refer(periph_id);
+}
+
+/**
+ * @brief Release reference to global peripheral @p periph_id
+ *
+ * Each call to @ref stm32_global_periph_refer should be
+ * matched with a call to this function. After calling
+ * this function, the caller is no longer allowed to
+ * access the registers of @p periph_id
+ *
+ * @internal
+ * Decrements the reference count for @p periph_id then
+ * disables the corresponding clock is enabled if the
+ * reference count has become 0.
+ * @endinternal
+ */
+void stm32_global_periph_release(enum stm32_global_peripheral_id periph_id) { //OR: "_unref"?
+	extern void _stm32_global_periph_refer(enum stm32_global_peripheral_id periph_id);
+
+	if (CONFIG_STM32_GLOBAL_CLOCKS_ALWAYS_ON_MASK & (1U << (unsigned int)periph_id)) {
+		/* Don't do anything for always-on clocks */
+		return;
+	}
+
+	_stm32_global_periph_release(periph_id);
+}
+#else /* !CONFIG_STM32_GLOBAL_CLOCKS_RUNTIME_GATING */
+/*
+ * When runtime clock gating is disabled, the RCC callback becomes
+ * an actual function but the rest is turned into no-ops.
+ */
+
+/**
+ * @note This function is reserved for usage by the RCC driver.
+ *       No other driver is allowed to invoke it!
+ */
+int stm32_global_periph_enable_all_clocks(void);
+#define stm32_global_periph_refer(...)
+#define stm32_global_periph_release(...)
+#endif /* CONFIG_STM32_GLOBAL_CLOCKS_RUNTIME_GATING */
+
+/**
+ * TODO: on certain series, there are certain clocks that don't exist!
+ * Could we determine this and make the refer()/release() calls no-ops
+ * on these series?
+ */
+
+#endif /* ZEPHYR_INCLUDE_SOC_ST_STM32_GLOBAL_CLOCKS_H_ */
diff --git a/soc/st/stm32/common/stm32_wkup_pins.c b/soc/st/stm32/common/stm32_wkup_pins.c
index 2232efdd1e676..d7c96e8b3c3b8 100644
--- a/soc/st/stm32/common/stm32_wkup_pins.c
+++ b/soc/st/stm32/common/stm32_wkup_pins.c
@@ -16,6 +16,8 @@
 #include <stm32_ll_system.h>
 #include <stm32_ll_pwr.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <zephyr/dt-bindings/power/stm32_pwr.h>
 
 #include "stm32_wkup_pins.h"
@@ -195,6 +197,8 @@ static void wkup_pin_setup(const struct wkup_pin_cfg_t *wakeup_pin_cfg)
 {
 	uint32_t wkup_pin_index = wakeup_pin_cfg->wkup_pin_id;
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 #if PWR_STM32_WKUP_PINS_POLARITY
 	/* Set wake-up pin polarity */
 	if (wakeup_pin_cfg->polarity == STM32_PWR_WKUP_PIN_P_FALLING) {
@@ -237,6 +241,8 @@ static void wkup_pin_setup(const struct wkup_pin_cfg_t *wakeup_pin_cfg)
 #endif /* CONFIG_SOC_SERIES_STM32U5X or CONFIG_SOC_SERIES_STM32WBAX */
 
 	LL_PWR_EnableWakeUpPin(table_wakeup_pins[wkup_pin_index]);
+
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 }
 
 /**
@@ -338,11 +344,13 @@ int stm32_pwr_wkup_pin_cfg_gpio(const struct gpio_dt_spec *gpio)
 void stm32_pwr_wkup_pin_cfg_pupd(void)
 {
 #if PWR_STM32_WKUP_PINS_PUPD_CFG
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 #ifdef CONFIG_SOC_SERIES_STM32U5X
 	LL_PWR_EnablePUPDConfig();
 #else
 	LL_PWR_EnablePUPDCfg();
 #endif /* CONFIG_SOC_SERIES_STM32U5X */
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 #else
 	return;
 #endif /* PWR_STM32_WKUP_PINS_PUPD_CFG */
diff --git a/soc/st/stm32/stm32c0x/power.c b/soc/st/stm32/stm32c0x/power.c
index 3eb212e247d6c..e0571e5e7c804 100644
--- a/soc/st/stm32/stm32c0x/power.c
+++ b/soc/st/stm32/stm32c0x/power.c
@@ -7,6 +7,7 @@
 
 #include <clock_control/clock_stm32_ll_common.h>
 #include <soc.h>
+#include <stm32_global_periph_clocks.h>
 
 #include <stm32c0xx_ll_cortex.h>
 #include <stm32c0xx_ll_pwr.h>
@@ -24,6 +25,9 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
 	ARG_UNUSED(substate_id);
 
+	/* Enable PWRC during entire PM cycle */
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	switch (state) {
 	case PM_STATE_SUSPEND_TO_IDLE:
 		LL_LPM_DisableEventOnPend();
@@ -58,6 +62,9 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 		break;
 	}
 
+	/* Release PWRC at end of PM cycle */
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode. Reenable interrupts which were
 	 * disabled when OS started idling code.
diff --git a/soc/st/stm32/stm32c0x/poweroff.c b/soc/st/stm32/stm32c0x/poweroff.c
index f0dadd89e32d2..e49ada8197b9f 100644
--- a/soc/st/stm32/stm32c0x/poweroff.c
+++ b/soc/st/stm32/stm32c0x/poweroff.c
@@ -14,12 +14,17 @@
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_system.h>
 
+#include <stm32_global_periph_clocks.h>
+
 void z_sys_poweroff(void)
 {
 #ifdef CONFIG_STM32_WKUP_PINS
 	stm32_pwr_wkup_pin_cfg_pupd();
 #endif /* CONFIG_STM32_WKUP_PINS */
 
+	/* reference will be released upon platform reset */
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	LL_PWR_ClearFlag_WU();
 
 	LL_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
diff --git a/soc/st/stm32/stm32c0x/soc.c b/soc/st/stm32/stm32c0x/soc.c
index 6309fb4f24147..276c2d418dd72 100644
--- a/soc/st/stm32/stm32c0x/soc.c
+++ b/soc/st/stm32/stm32c0x/soc.c
@@ -35,7 +35,4 @@ void soc_early_init_hook(void)
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 48 MHz from HSI */
 	SystemCoreClock = 48000000;
-
-	/* Enable PWR clock */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 }
diff --git a/soc/st/stm32/stm32f0x/soc.c b/soc/st/stm32/stm32f0x/soc.c
index d34637406f87b..553101b834308 100644
--- a/soc/st/stm32/stm32f0x/soc.c
+++ b/soc/st/stm32/stm32f0x/soc.c
@@ -17,6 +17,8 @@
 
 #include <cmsis_core.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #if defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
 extern void *_vector_table_pointer;
 #endif
@@ -53,7 +55,10 @@ void relocate_vector_table(void)
 	size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
 
 	memcpy(_ram_vector_start, _vector_start, vector_size);
+
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
 	LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM);
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
 #endif
 }
 
diff --git a/soc/st/stm32/stm32f1x/power.c b/soc/st/stm32/stm32f1x/power.c
index d00be505af7c8..e23809b0d37ff 100644
--- a/soc/st/stm32/stm32f1x/power.c
+++ b/soc/st/stm32/stm32f1x/power.c
@@ -12,10 +12,14 @@
 #include <zephyr/logging/log.h>
 #include <zephyr/pm/pm.h>
 
+#include <stm32_global_periph_clocks.h>
+
 LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
 __weak void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	switch (state) {
 	case PM_STATE_SUSPEND_TO_IDLE:
 		LL_LPM_DisableEventOnPend();
@@ -57,6 +61,8 @@ __weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 		break;
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode. Reenable interrupts which were
 	 * disabled when OS started idling code.
diff --git a/soc/st/stm32/stm32f1x/soc.c b/soc/st/stm32/stm32f1x/soc.c
index e7943cf4f723c..06c196260a2b9 100644
--- a/soc/st/stm32/stm32f1x/soc.c
+++ b/soc/st/stm32/stm32f1x/soc.c
@@ -32,8 +32,4 @@ void soc_early_init_hook(void)
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 8 MHz from HSI */
 	SystemCoreClock = 8000000;
-
-#if defined(CONFIG_PM) || defined(CONFIG_POWEROFF)
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-#endif
 }
diff --git a/soc/st/stm32/stm32f4x/power.c b/soc/st/stm32/stm32f4x/power.c
index d0e677b5dc3f0..5650df933f20b 100644
--- a/soc/st/stm32/stm32f4x/power.c
+++ b/soc/st/stm32/stm32f4x/power.c
@@ -20,6 +20,8 @@
 #include <zephyr/pm/pm.h>
 #include <zephyr/init.h>
 
+#include <stm32_global_periph_clocks.h>
+
 LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
 BUILD_ASSERT(DT_SAME_NODE(DT_CHOSEN(zephyr_cortex_m_idle_timer), DT_NODELABEL(rtc)),
@@ -28,6 +30,7 @@ BUILD_ASSERT(DT_SAME_NODE(DT_CHOSEN(zephyr_cortex_m_idle_timer), DT_NODELABEL(rt
 void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
 	ARG_UNUSED(substate_id);
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 
 	switch (state) {
 	case PM_STATE_SUSPEND_TO_IDLE:
@@ -68,6 +71,8 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 		break;
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode. Reenable interrupts which were
 	 * disabled when OS started idling code.
@@ -77,8 +82,4 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 
 void stm32_power_init(void)
 {
-	/* Enable Power clock. It should by done by default, but make sure to
-	 * enable it for all STM32F4x chips.
-	 */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 }
diff --git a/soc/st/stm32/stm32f4x/poweroff.c b/soc/st/stm32/stm32f4x/poweroff.c
index 53ebbf01581b2..063a30c7f781e 100644
--- a/soc/st/stm32/stm32f4x/poweroff.c
+++ b/soc/st/stm32/stm32f4x/poweroff.c
@@ -14,8 +14,12 @@
 #include <stm32_ll_cortex.h>
 #include <stm32_ll_pwr.h>
 
+#include <stm32_global_periph_clocks.h>
+
 void z_sys_poweroff(void)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	LL_PWR_ClearFlag_WU();
 
 	LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
diff --git a/soc/st/stm32/stm32g0x/power.c b/soc/st/stm32/stm32g0x/power.c
index 88bff751d42a7..7e63b39315f6f 100644
--- a/soc/st/stm32/stm32g0x/power.c
+++ b/soc/st/stm32/stm32g0x/power.c
@@ -9,6 +9,8 @@
 #include <soc.h>
 #include <zephyr/init.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <stm32g0xx_ll_utils.h>
 #include <stm32g0xx_ll_bus.h>
 #include <stm32g0xx_ll_cortex.h>
@@ -27,6 +29,8 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 		return;
 	}
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	switch (substate_id) {
 	case 1: /* this corresponds to the STOP0 mode: */
 		/* enter STOP0 mode */
@@ -72,6 +76,8 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 		stm32_clock_control_init(NULL);
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode.
 	 * Reenable interrupts which were disabled
@@ -83,7 +89,4 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 /* Initialize STM32 Power */
 void stm32_power_init(void)
 {
-
-	/* enable Power clock */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 }
diff --git a/soc/st/stm32/stm32g0x/poweroff.c b/soc/st/stm32/stm32g0x/poweroff.c
index c14b33e4e454b..8fa8262d9a432 100644
--- a/soc/st/stm32/stm32g0x/poweroff.c
+++ b/soc/st/stm32/stm32g0x/poweroff.c
@@ -15,8 +15,12 @@
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_system.h>
 
+#include <stm32_global_periph_clocks.h>
+
 void z_sys_poweroff(void)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 #ifdef CONFIG_STM32_WKUP_PINS
 	stm32_pwr_wkup_pin_cfg_pupd();
 #endif /* CONFIG_STM32_WKUP_PINS */
diff --git a/soc/st/stm32/stm32g0x/soc.c b/soc/st/stm32/stm32g0x/soc.c
index 9b2d29d17a44a..5a42905df3268 100644
--- a/soc/st/stm32/stm32g0x/soc.c
+++ b/soc/st/stm32/stm32g0x/soc.c
@@ -65,8 +65,9 @@ static void stm32g0_disable_dead_battery(void)
 	}
 
 	if (strobe != 0) {
-		LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
 		LL_SYSCFG_DisableDBATT(strobe);
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
 	}
 #endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
 }
diff --git a/soc/st/stm32/stm32g4x/power.c b/soc/st/stm32/stm32g4x/power.c
index 092562c33ad6e..e842f4a8cfa65 100644
--- a/soc/st/stm32/stm32g4x/power.c
+++ b/soc/st/stm32/stm32g4x/power.c
@@ -11,6 +11,8 @@
 #include <zephyr/pm/pm.h>
 #include <soc.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <clock_control/clock_stm32_ll_common.h>
 #include <stm32g4xx_ll_bus.h>
 #include <stm32g4xx_ll_cortex.h>
@@ -27,6 +29,8 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 		return;
 	}
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	switch (substate_id) {
 	case 1: /* this corresponds to the STOP0 mode: */
 		/* enter STOP0 mode */
@@ -70,6 +74,8 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 		stm32_clock_control_init(NULL);
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode.
 	 * Reenable interrupts which were disabled
@@ -81,7 +87,4 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 /* Initialize STM32 Power */
 void stm32_power_init(void)
 {
-
-	/* enable Power clock */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 }
diff --git a/soc/st/stm32/stm32g4x/soc.c b/soc/st/stm32/stm32g4x/soc.c
index b43e48e67e81d..19c95a7dd15b0 100644
--- a/soc/st/stm32/stm32g4x/soc.c
+++ b/soc/st/stm32/stm32g4x/soc.c
@@ -46,9 +46,10 @@ void soc_early_init_hook(void)
 #if defined(PWR_CR3_UCPD_DBDIS)
 	if (IS_ENABLED(CONFIG_DT_HAS_ST_STM32_UCPD_ENABLED) ||
 		!IS_ENABLED(CONFIG_USB_DEVICE_DRIVER)) {
-		/* Disable USB Type-C dead battery pull-down behavior */
-		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		LL_PWR_DisableUCPDDeadBattery();
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 	}
 
 #endif /* PWR_CR3_UCPD_DBDIS */
diff --git a/soc/st/stm32/stm32h5x/power.c b/soc/st/stm32/stm32h5x/power.c
index 1af853c6c0fc6..646107a847846 100644
--- a/soc/st/stm32/stm32h5x/power.c
+++ b/soc/st/stm32/stm32h5x/power.c
@@ -8,6 +8,8 @@
 #include <soc.h>
 #include <zephyr/init.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <stm32h5xx_ll_cortex.h>
 #include <stm32h5xx_ll_pwr.h>
 #include <clock_control/clock_stm32_ll_common.h>
@@ -23,6 +25,9 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 		return;
 	}
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
+
 	switch (substate_id) {
 	case 1: /* this corresponds to the STOP mode: */
 		/* enter STOP mode */
@@ -59,6 +64,8 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 		stm32_clock_control_init(NULL);
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode.
 	 * Reenable interrupts which were disabled
diff --git a/soc/st/stm32/stm32h5x/soc.c b/soc/st/stm32/stm32h5x/soc.c
index 5ae4618b707da..ee92d827ef32a 100644
--- a/soc/st/stm32/stm32h5x/soc.c
+++ b/soc/st/stm32/stm32h5x/soc.c
@@ -16,6 +16,8 @@
 #include <stm32_ll_pwr.h>
 #include <zephyr/logging/log.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <cmsis_core.h>
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
@@ -39,7 +41,9 @@ void soc_early_init_hook(void)
 	if (IS_ENABLED(CONFIG_DT_HAS_ST_STM32_UCPD_ENABLED) ||
 		!IS_ENABLED(CONFIG_USB_DEVICE_DRIVER)) {
 		/* Disable USB Type-C dead battery pull-down behavior */
+		stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 		LL_PWR_DisableUCPDDeadBattery();
+		stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 	}
 
 #endif /* PWR_UCPDR_UCPD_DBDIS */
diff --git a/soc/st/stm32/stm32h7rsx/soc.c b/soc/st/stm32/stm32h7rsx/soc.c
index 7d19774cc2cd2..019bbc0f4b560 100644
--- a/soc/st/stm32/stm32h7rsx/soc.c
+++ b/soc/st/stm32/stm32h7rsx/soc.c
@@ -20,6 +20,7 @@
 
 #include <cmsis_core.h>
 
+#include <stm32_global_periph_clocks.h>
 
 /**
  * @brief Perform basic hardware initialization at boot.
@@ -36,6 +37,7 @@ void soc_early_init_hook(void)
 	SystemCoreClock = 64000000;
 
 	/* Power Configuration */
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 #if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
 	LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
@@ -68,4 +70,5 @@ void soc_early_init_hook(void)
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpiom), okay)
 	LL_PWR_EnableUSBVoltageDetector(); /* Required for powering GPIO M */
 #endif /* gpiom */
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 }
diff --git a/soc/st/stm32/stm32h7x/soc_m7.c b/soc/st/stm32/stm32h7x/soc_m7.c
index e479e74566335..0ed0ffeace61a 100644
--- a/soc/st/stm32/stm32h7x/soc_m7.c
+++ b/soc/st/stm32/stm32h7x/soc_m7.c
@@ -19,6 +19,8 @@
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_rcc.h>
 #include <stm32_ll_system.h>
+
+#include <stm32_global_periph_clocks.h>
 #include "stm32_hsem.h"
 
 #include <cmsis_core.h>
@@ -46,7 +48,7 @@ static int stm32h7_m4_wakeup(void)
 
 	/* HW semaphore and SysCfg Clock enable */
 	LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
-	LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_SYSCFG);
 
 	if (stm32_reg_read_bits(&SYSCFG->UR1, SYSCFG_UR1_BCM4) != 0) {
 		/**
@@ -63,6 +65,8 @@ static int stm32h7_m4_wakeup(void)
 		LL_RCC_ForceCM4Boot();
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_SYSCFG);
+
 	return 0;
 }
 #endif /* CONFIG_STM32H7_DUAL_CORE */
@@ -122,6 +126,8 @@ void soc_early_init_hook(void)
 		defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT))
 #error Unsupported configuration: Selected SoC do not support SMPS
 #endif
+
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 #if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
 	LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
@@ -141,6 +147,7 @@ void soc_early_init_hook(void)
 #else
 	LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
 #endif
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 
 	/* Errata ES0392 Rev 8:
 	 * 2.2.9: Reading from AXI SRAM may lead to data read corruption
diff --git a/soc/st/stm32/stm32l0x/power.c b/soc/st/stm32/stm32l0x/power.c
index aa3dd1caf8a52..6f14b16c05c52 100644
--- a/soc/st/stm32/stm32l0x/power.c
+++ b/soc/st/stm32/stm32l0x/power.c
@@ -17,6 +17,8 @@
 #include <clock_control/clock_stm32_ll_common.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <zephyr/logging/log.h>
 LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
@@ -32,6 +34,8 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
 	ARG_UNUSED(substate_id);
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	switch (state) {
 	case PM_STATE_SUSPEND_TO_IDLE:
 		LL_RCC_SetClkAfterWakeFromStop(RCC_STOP_WAKEUPCLOCK_SELECTED);
@@ -66,6 +70,8 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 		break;
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode. Reenable interrupts which were
 	 * disabled when OS started idling code.
diff --git a/soc/st/stm32/stm32l0x/soc.c b/soc/st/stm32/stm32l0x/soc.c
index 2fe17d17d6388..ba9d2a2aa40e1 100644
--- a/soc/st/stm32/stm32l0x/soc.c
+++ b/soc/st/stm32/stm32l0x/soc.c
@@ -42,8 +42,4 @@ void soc_early_init_hook(void)
 	 * https://github.com/zephyrproject-rtos/zephyr/issues/#34324 )
 	 */
 	LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
-#ifdef CONFIG_PM
-	/* Enable Power clock */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-#endif
 }
diff --git a/soc/st/stm32/stm32l1x/power.c b/soc/st/stm32/stm32l1x/power.c
index f9aa5196460c6..483eaa909057a 100644
--- a/soc/st/stm32/stm32l1x/power.c
+++ b/soc/st/stm32/stm32l1x/power.c
@@ -8,6 +8,8 @@
 #include <stm32l1xx_ll_cortex.h>
 #include <stm32l1xx_ll_pwr.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/pm/pm.h>
@@ -16,6 +18,8 @@ LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
 __weak void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	switch (state) {
 	case PM_STATE_RUNTIME_IDLE:
 		LL_LPM_DisableEventOnPend();
@@ -68,6 +72,8 @@ __weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 		break;
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode. Reenable interrupts which were
 	 * disabled when OS started idling code.
diff --git a/soc/st/stm32/stm32l1x/poweroff.c b/soc/st/stm32/stm32l1x/poweroff.c
index be61a9d1252ae..ddf8606237ca3 100644
--- a/soc/st/stm32/stm32l1x/poweroff.c
+++ b/soc/st/stm32/stm32l1x/poweroff.c
@@ -10,8 +10,11 @@
 #include <zephyr/kernel.h>
 #include <zephyr/sys/poweroff.h>
 
+#include <stm32_global_periph_clocks.h>
+
 void z_sys_poweroff(void)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	LL_PWR_ClearFlag_SB();
 	LL_PWR_ClearFlag_WU();
 
diff --git a/soc/st/stm32/stm32l1x/soc.c b/soc/st/stm32/stm32l1x/soc.c
index 8cb6ebf9ddff5..880875ad519b4 100644
--- a/soc/st/stm32/stm32l1x/soc.c
+++ b/soc/st/stm32/stm32l1x/soc.c
@@ -19,6 +19,8 @@
 
 #include <cmsis_core.h>
 
+#include <stm32_global_periph_clocks.h>
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -39,6 +41,7 @@ void soc_early_init_hook(void)
 	 * doesn't allow to configure Max frequency
 	 * switch to range1 to match any frequency
 	 */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 }
diff --git a/soc/st/stm32/stm32l4x/power.c b/soc/st/stm32/stm32l4x/power.c
index 056204dfe4ef3..eed632e6cefff 100644
--- a/soc/st/stm32/stm32l4x/power.c
+++ b/soc/st/stm32/stm32l4x/power.c
@@ -16,6 +16,7 @@
 #include <stm32l4xx_ll_system.h>
 #include <clock_control/clock_stm32_ll_common.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <stm32_global_periph_clocks.h>
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
@@ -57,6 +58,8 @@ void set_mode_stop(uint8_t substate_id)
 /* Invoke Low Power/System Off specific Tasks */
 void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	switch (state) {
 	case PM_STATE_SUSPEND_TO_IDLE:
 		set_mode_stop(substate_id);
@@ -111,12 +114,10 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 		break;
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 }
 
 /* Initialize STM32 Power */
 void stm32_power_init(void)
 {
-
-	/* enable Power clock */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 }
diff --git a/soc/st/stm32/stm32l4x/poweroff.c b/soc/st/stm32/stm32l4x/poweroff.c
index 5a806d9d4b204..0f7d622fdb9f4 100644
--- a/soc/st/stm32/stm32l4x/poweroff.c
+++ b/soc/st/stm32/stm32l4x/poweroff.c
@@ -10,12 +10,15 @@
 #include <zephyr/toolchain.h>
 #include <zephyr/drivers/misc/stm32_wkup_pins/stm32_wkup_pins.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <stm32_ll_cortex.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_system.h>
 
 void z_sys_poweroff(void)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 #ifdef CONFIG_STM32_WKUP_PINS
 	stm32_pwr_wkup_pin_cfg_pupd();
 #endif /* CONFIG_STM32_WKUP_PINS */
diff --git a/soc/st/stm32/stm32l5x/power.c b/soc/st/stm32/stm32l5x/power.c
index fa3cce5172cb4..78e13e64f108c 100644
--- a/soc/st/stm32/stm32l5x/power.c
+++ b/soc/st/stm32/stm32l5x/power.c
@@ -17,6 +17,8 @@
 #include <clock_control/clock_stm32_ll_common.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <zephyr/logging/log.h>
 LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
@@ -35,6 +37,8 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 		return;
 	}
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	/* ensure the proper wake-up system clock */
 	LL_RCC_SetClkAfterWakeFromStop(RCC_STOP_WAKEUPCLOCK_SELECTED);
 
@@ -89,6 +93,8 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 		stm32_clock_control_init(NULL);
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode.
 	 * Reenable interrupts which were disabled
@@ -100,7 +106,4 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 /* Initialize STM32 Power */
 void stm32_power_init(void)
 {
-
-	/* enable Power clock */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 }
diff --git a/soc/st/stm32/stm32l5x/soc.c b/soc/st/stm32/stm32l5x/soc.c
index d8aed0383a695..c29b184dc2e96 100644
--- a/soc/st/stm32/stm32l5x/soc.c
+++ b/soc/st/stm32/stm32l5x/soc.c
@@ -18,6 +18,8 @@
 
 #include <cmsis_core.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
@@ -36,7 +38,7 @@ void soc_early_init_hook(void)
 	SystemCoreClock = 4000000;
 
 	/* Enable Scale 0 to achieve 110MHz */
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
 
 	if (IS_ENABLED(CONFIG_DT_HAS_ST_STM32_UCPD_ENABLED) ||
@@ -44,6 +46,8 @@ void soc_early_init_hook(void)
 		/* Disable USB Type-C dead battery pull-down behavior */
 		LL_PWR_DisableUCPDDeadBattery();
 	}
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 #if CONFIG_PM
 	stm32_power_init();
 #endif
diff --git a/soc/st/stm32/stm32n6x/soc.c b/soc/st/stm32/stm32n6x/soc.c
index d3bae6eeff81c..da3fe269fc27d 100644
--- a/soc/st/stm32/stm32n6x/soc.c
+++ b/soc/st/stm32/stm32n6x/soc.c
@@ -20,6 +20,8 @@
 
 #include <cmsis_core.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
@@ -51,8 +53,7 @@ void soc_early_init_hook(void)
 	/* At reset, system core clock is set to 64 MHz from HSI */
 	SystemCoreClock = 64000000;
 
-	/* Enable PWR */
-	LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 
 	/* Set the main internal Regulator output voltage for best performance */
 	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
@@ -66,4 +67,6 @@ void soc_early_init_hook(void)
 	/* Set Vdd IO2 and IO3 to 1.8V */
 	LL_PWR_SetVddIO2VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8);
 	LL_PWR_SetVddIO3VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8);
+
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 }
diff --git a/soc/st/stm32/stm32u0x/power.c b/soc/st/stm32/stm32u0x/power.c
index 7b5c99f9e0fc3..e1956a97632c9 100644
--- a/soc/st/stm32/stm32u0x/power.c
+++ b/soc/st/stm32/stm32u0x/power.c
@@ -9,6 +9,8 @@
 #include <zephyr/logging/log.h>
 #include <zephyr/pm/pm.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <clock_control/clock_stm32_ll_common.h>
 #include <stm32u0xx_ll_cortex.h>
 #include <stm32u0xx_ll_pwr.h>
@@ -54,6 +56,8 @@ void set_mode_standby(uint8_t substate_id)
 /* Invoke Low Power/System Off specific Tasks */
 void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	switch (state) {
 	case PM_STATE_SUSPEND_TO_IDLE:
 		set_mode_stop(substate_id);
@@ -96,6 +100,8 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 	/* need to restore the clock */
 	stm32_clock_control_init(NULL);
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode.
 	 * Reenable interrupts which were disabled when OS started idling code.
diff --git a/soc/st/stm32/stm32u0x/soc.c b/soc/st/stm32/stm32u0x/soc.c
index 903d64578408a..4a43481a2db0f 100644
--- a/soc/st/stm32/stm32u0x/soc.c
+++ b/soc/st/stm32/stm32u0x/soc.c
@@ -36,6 +36,4 @@ void soc_early_init_hook(void)
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
 	SystemCoreClock = 16000000;
-
-	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 }
diff --git a/soc/st/stm32/stm32u3x/soc.c b/soc/st/stm32/stm32u3x/soc.c
index 7ad3edbcb7aea..da28615c42a2b 100644
--- a/soc/st/stm32/stm32u3x/soc.c
+++ b/soc/st/stm32/stm32u3x/soc.c
@@ -38,7 +38,4 @@ void soc_early_init_hook(void)
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* The MSIS is used as system clock source after startup from reset,configured at 12 MHz. */
 	SystemCoreClock = 12000000;
-
-	/* Enable power controller bus clock for other drivers */
-	LL_AHB1_GRP2_EnableClock(LL_AHB1_GRP2_PERIPH_PWR);
 }
diff --git a/soc/st/stm32/stm32u5x/power.c b/soc/st/stm32/stm32u5x/power.c
index b810743a74d11..7e857614f88ef 100644
--- a/soc/st/stm32/stm32u5x/power.c
+++ b/soc/st/stm32/stm32u5x/power.c
@@ -17,6 +17,8 @@
 #include <stm32u5xx_ll_system.h>
 #include <clock_control/clock_stm32_ll_common.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <zephyr/logging/log.h>
 LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
@@ -87,6 +89,8 @@ void set_mode_standby(uint8_t substate_id)
 /* Invoke Low Power/System Off specific Tasks */
 void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	switch (state) {
 	case PM_STATE_SUSPEND_TO_IDLE:
 		set_mode_stop(substate_id);
@@ -144,6 +148,8 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 	/* need to restore the clock */
 	stm32_clock_control_init(NULL);
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode.
 	 * Reenable interrupts which were disabled
@@ -155,10 +161,6 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 /* Initialize STM32 Power */
 void stm32_power_init(void)
 {
-
-	/* enable Power clock */
-	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
-
 #ifdef CONFIG_STM32_STOP3_LP_MODE
 	IRQ_CONNECT(PWR_S3WU_IRQn, 0,
 		    pwr_stop3_isr, 0, 0);
diff --git a/soc/st/stm32/stm32u5x/poweroff.c b/soc/st/stm32/stm32u5x/poweroff.c
index 6d5696dc24af5..faa3dff22a7bb 100644
--- a/soc/st/stm32/stm32u5x/poweroff.c
+++ b/soc/st/stm32/stm32u5x/poweroff.c
@@ -10,11 +10,14 @@
 #include <zephyr/toolchain.h>
 #include <zephyr/drivers/misc/stm32_wkup_pins/stm32_wkup_pins.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <stm32_ll_cortex.h>
 #include <stm32_ll_pwr.h>
 
 void z_sys_poweroff(void)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 #ifdef CONFIG_STM32_WKUP_PINS
 	stm32_pwr_wkup_pin_cfg_pupd();
 #endif /* CONFIG_STM32_WKUP_PINS */
diff --git a/soc/st/stm32/stm32u5x/soc.c b/soc/st/stm32/stm32u5x/soc.c
index 5263db29c3769..526df4eb7a9da 100644
--- a/soc/st/stm32/stm32u5x/soc.c
+++ b/soc/st/stm32/stm32u5x/soc.c
@@ -18,6 +18,8 @@
 
 #include <cmsis_core.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
@@ -36,7 +38,7 @@ void soc_early_init_hook(void)
 	SystemCoreClock = 4000000;
 
 	/* Enable PWR */
-	LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 
 	/* For devices with USB C PD, we can disable the dead battery
 	 * pull-down behaviour.
@@ -61,4 +63,5 @@ void soc_early_init_hook(void)
 #if CONFIG_PM
 	stm32_power_init();
 #endif
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 }
diff --git a/soc/st/stm32/stm32wbax/power.c b/soc/st/stm32/stm32wbax/power.c
index 417a2b5dd3c48..87ab2fd6ee920 100644
--- a/soc/st/stm32/stm32wbax/power.c
+++ b/soc/st/stm32/stm32wbax/power.c
@@ -18,6 +18,8 @@
 
 #include <cmsis_core.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <stm32wbaxx_ll_bus.h>
 #include <stm32wbaxx_ll_cortex.h>
 #include <stm32wbaxx_ll_pwr.h>
@@ -208,6 +210,8 @@ static void set_mode_stop_exit(uint8_t substate_id)
 /* Invoke Low Power/System Off specific Tasks */
 void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	switch (state) {
 	case PM_STATE_SUSPEND_TO_IDLE:
 		set_mode_stop_enter(substate_id);
@@ -230,6 +234,8 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 /* Handle SOC specific activity after Low Power Mode Exit */
 void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 {
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode.
 	 * Reenable interrupts which were disabled
@@ -242,8 +248,6 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 void stm32_power_init(void)
 {
 
-	LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
-
 #ifdef CONFIG_DEBUG
 	LL_DBGMCU_EnableDBGStandbyMode();
 	LL_DBGMCU_APB7_GRP1_FreezePeriph(LL_DBGMCU_APB7_GRP1_RTC_STOP);
@@ -252,6 +256,8 @@ void stm32_power_init(void)
 	LL_DBGMCU_DisableDBGStandbyMode();
 #endif
 
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	/* Enable SRAM full retention */
 	LL_PWR_SetSRAM1SBRetention(LL_PWR_SRAM1_SB_FULL_RETENTION);
 	LL_PWR_SetSRAM2SBRetention(LL_PWR_SRAM2_SB_FULL_RETENTION);
@@ -262,5 +268,7 @@ void stm32_power_init(void)
 	/* Enabling  Ultra Low power mode */
 	LL_PWR_EnableUltraLowPowerMode();
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	LL_FLASH_EnableSleepPowerDown();
 }
diff --git a/soc/st/stm32/stm32wbax/poweroff.c b/soc/st/stm32/stm32wbax/poweroff.c
index b62bc8085d674..273d207fa6e43 100644
--- a/soc/st/stm32/stm32wbax/poweroff.c
+++ b/soc/st/stm32/stm32wbax/poweroff.c
@@ -12,8 +12,11 @@
 #include <stm32_ll_cortex.h>
 #include <stm32_ll_pwr.h>
 
+#include <stm32_global_periph_clocks.h>
+
 void z_sys_poweroff(void)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 #ifdef CONFIG_STM32_WKUP_PINS
 	stm32_pwr_wkup_pin_cfg_pupd();
 #endif /* CONFIG_STM32_WKUP_PINS */
diff --git a/soc/st/stm32/stm32wbax/soc.c b/soc/st/stm32/stm32wbax/soc.c
index fb54c5b53030c..3ef2dad30d467 100644
--- a/soc/st/stm32/stm32wbax/soc.c
+++ b/soc/st/stm32/stm32wbax/soc.c
@@ -21,6 +21,8 @@
 #include "soc.h"
 #include <cmsis_core.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
 LOG_MODULE_REGISTER(soc);
 
@@ -40,14 +42,15 @@ void stm32wba_init(void)
 	/* At reset, system core clock is set to 16 MHz from HSI */
 	SystemCoreClock = 16000000;
 
-	/* Enable PWR */
-	LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
 
 #if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
 	LL_PWR_SetRegulatorSupply(LL_PWR_SMPS_SUPPLY);
 #elif defined(CONFIG_POWER_SUPPLY_LDO)
 	LL_PWR_SetRegulatorSupply(LL_PWR_LDO_SUPPLY);
 #endif
+
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
 }
 
 void soc_early_init_hook(void)
diff --git a/soc/st/stm32/stm32wbx/power.c b/soc/st/stm32/stm32wbx/power.c
index 3cab5ffbc55a4..6d6371d848360 100644
--- a/soc/st/stm32/stm32wbx/power.c
+++ b/soc/st/stm32/stm32wbx/power.c
@@ -15,6 +15,7 @@
 #include <stm32wbxx_ll_pwr.h>
 #include <stm32wbxx_ll_rcc.h>
 #include <clock_control/clock_stm32_ll_common.h>
+#include <stm32_global_periph_clocks.h>
 #include "stm32_hsem.h"
 
 #include <zephyr/logging/log.h>
@@ -59,6 +60,8 @@ static void lpm_hsem_lock(void)
 /* Invoke Low Power/System Off specific Tasks */
 void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	if (state == PM_STATE_SUSPEND_TO_IDLE) {
 
 		lpm_hsem_lock();
@@ -142,6 +145,8 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 	/* Release RCC semaphore */
 	z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode.
 	 * Reenable interrupts which were disabled
diff --git a/soc/st/stm32/stm32wlx/power.c b/soc/st/stm32/stm32wlx/power.c
index 8ab72d1a1f425..f9c9fc4ad68e4 100644
--- a/soc/st/stm32/stm32wlx/power.c
+++ b/soc/st/stm32/stm32wlx/power.c
@@ -17,6 +17,8 @@
 #include <clock_control/clock_stm32_ll_common.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 
+#include <stm32_global_periph_clocks.h>
+
 #include <zephyr/logging/log.h>
 LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
@@ -30,6 +32,8 @@ LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 /* Invoke Low Power/System Off specific Tasks */
 void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 	switch (state) {
 	case PM_STATE_SUSPEND_TO_IDLE:
 		LL_RCC_SetClkAfterWakeFromStop(RCC_STOP_WAKEUPCLOCK_SELECTED);
@@ -74,6 +78,8 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 		break;
 	}
 
+	stm32_global_periph_release(STM32_GLOBAL_PERIPH_PWR);
+
 	/*
 	 * System is now in active mode.
 	 * Reenable interrupts which were disabled
diff --git a/soc/st/stm32/stm32wlx/poweroff.c b/soc/st/stm32/stm32wlx/poweroff.c
index 15d546a74c75e..7bf9a17433a2c 100644
--- a/soc/st/stm32/stm32wlx/poweroff.c
+++ b/soc/st/stm32/stm32wlx/poweroff.c
@@ -13,8 +13,12 @@
 #include <stm32_ll_cortex.h>
 #include <stm32_ll_pwr.h>
 
+#include <stm32_global_periph_clocks.h>
+
 void z_sys_poweroff(void)
 {
+	stm32_global_periph_refer(STM32_GLOBAL_PERIPH_PWR);
+
 #ifdef CONFIG_STM32_WKUP_PINS
 	stm32_pwr_wkup_pin_cfg_pupd();
 #endif /* CONFIG_STM32_WKUP_PINS */