work around verilator 5.030 issue (#49)

mathis-s · web-flow · commit f9d815166edf · 2025-01-05T15:15:38.000+01:00
diff --git a/src/Load.sv b/src/Load.sv
@@ -98,7 +98,7 @@ end
 FuncUnit outFU[NUM_UOPS-1:0];
 
 EX_UOp outUOpReg[NUM_UOPS-1:0];
-reg[1:0] operandIsReg[NUM_UOPS-1:0];
+logic[NUM_UOPS-1:0][1:0] operandIsReg;
 
 always_comb begin
     for (integer i = 0; i < NUM_UOPS; i=i+1) begin
