From 3c51d9c714e1a2f1a7b11fe9ee370de1a358479b Mon Sep 17 00:00:00 2001 From: Clstilmldy Date: Wed, 7 Jan 2026 17:58:41 +0800 Subject: [PATCH 1/4] Feat: Added explanations of the sources of header files in model_headers.h. The content of the header files generated after executing "make soomrv" may vary across different Verilator versions. If related issues occur, you need to execute "make prepare_header" to resolve them. --- sim/model_headers.h | 64 +++++++++++++++++++++++++++++---------------- 1 file changed, 42 insertions(+), 22 deletions(-) diff --git a/sim/model_headers.h b/sim/model_headers.h index 2fe2f29e..44aa8b27 100644 --- a/sim/model_headers.h +++ b/sim/model_headers.h @@ -1,31 +1,51 @@ -#include "VTop_TagBuffer.h" -#include "VTop_CSR.h" -#include "VTop_Rename__WC5.h" -#include "VTop_IF_ICTable.h" +// Include all *.h files in obj_dir (auto-generated by Verilator) +// Use `make prepare_header` to regenerate +// Top-level core header file #include "VTop.h" -#include "VTop_RegFile__W50_S20_N1_NB1.h" -#include "VTop_ExternalAXISim.h" -#include "VTop_RenameTable__ND5.h" -#include "VTop_ROB.h" #include "VTop_Top.h" -#include "VTop_IFetchPipeline.h" -#include "VTop_MemRTL__W200_N40.h" -#include "VTop_StoreQueue.h" + +// Root module and global unit header files #include "VTop___024root.h" +#include "VTop___024unit.h" + +// Core module related +#include "VTop_Core.h" +#include "VTop_CSR.h" + +// Branch prediction related +#include "VTop_BranchPredictor__N3.h" +#include "VTop_ReturnStack.h" + +// SoC and external modules +#include "VTop_SoC.h" +#include "VTop_ExternalAXISim.h" + +// Instruction fetch stage related #include "VTop_IFetch.h" +#include "VTop_IFetchPipeline.h" #include "VTop_IF_Cache.h" -#include "VTop__Dpi.h" +#include "VTop_IF_CTable.h" +#include "VTop_IF_ICache.h" +#include "VTop_IF_ICTable.h" #include "VTop_IF_MMIO.h" + +// Memory module related +#include "VTop_MemRTL__W200_N40.h" +#include "VTop_MemRTL__W200_N100_WB80.h" +#include "VTop_MemRTL1RW__W2_N40_WB2.h" #include "VTop_MemRTL1RW__W54_N40_WB15.h" -#include "VTop_BranchPredictor__N3.h" +#include "VTop_StoreQueue.h" +#include "VTop_ROB.h" + +// Register file and rename related #include "VTop_RegFile__NB5_A1.h" -#include "VTop_ReturnStack.h" -#include "VTop_Core.h" -#include "VTop_IF_ICache.h" #include "VTop_RegFile__W23_S20_N3_NB1.h" -#include "VTop_SoC.h" -#include "VTop___024unit.h" -#include "VTop_MemRTL__W200_N100_WB80.h" -#include "VTop__Syms.h" -#include "VTop__pch.h" -#include "VTop_IF_CTable.h" +#include "VTop_RegFile__W50_S20_N1_NB1.h" +#include "VTop_RenameTable__ND5.h" +#include "VTop_Rename__WC5.h" +#include "VTop_TagBuffer.h" + +// Other auxiliary header files +#include "VTop__Dpi.h" +#include "VTop__pch.h" // Precompiled header +#include "VTop__Syms.h" \ No newline at end of file From e05d6a797b3922724b450f3f4dbb5621d103093a Mon Sep 17 00:00:00 2001 From: Clstilmldy Date: Wed, 7 Jan 2026 17:31:09 +0800 Subject: [PATCH 2/4] Fix: Solve the Warning-PROCASSINIT issue in Verilator 5.040. A variable is assigned an initial value at the time of declaration but is reassigned in sequential logic. Verilator treats such warnings as errors by default. --- src/ExternalAXISim.sv | 2 +- src/MemRTL.sv | 4 ++-- src/MemRTL1RW.sv | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ExternalAXISim.sv b/src/ExternalAXISim.sv index 101b8b5c..4b2e6924 100644 --- a/src/ExternalAXISim.sv +++ b/src/ExternalAXISim.sv @@ -94,7 +94,7 @@ initial begin end // RTL sim input -logic inputAvail /*verilator public*/ = 0; +logic inputAvail /*verilator public*/ /* = 0 */; logic[7:0] inputByte /*verilator public*/; // Read Data Output diff --git a/src/MemRTL.sv b/src/MemRTL.sv index d424629d..d038a7d9 100644 --- a/src/MemRTL.sv +++ b/src/MemRTL.sv @@ -22,8 +22,8 @@ module MemRTL (* ram_style = "block" *) reg[WORD_SIZE-1:0] mem[NUM_WORDS-1:0] /* verilator public */; -reg ce_reg = 1; -reg ce1_reg = 1; +reg ce_reg /* = 1 */; +reg ce1_reg /* = 1 */; reg we_reg; reg[$clog2(NUM_WORDS)-1:0] addr_reg; reg[$clog2(NUM_WORDS)-1:0] addr1_reg; diff --git a/src/MemRTL1RW.sv b/src/MemRTL1RW.sv index 055cadd3..92fa16af 100644 --- a/src/MemRTL1RW.sv +++ b/src/MemRTL1RW.sv @@ -18,7 +18,7 @@ module MemRTL1RW (* ram_style = "block" *) reg[WORD_SIZE-1:0] mem[NUM_WORDS-1:0] /* verilator public */; -reg ce_reg = 1; +reg ce_reg /* = 1 */; reg we_reg; reg[$clog2(NUM_WORDS)-1:0] addr_reg; reg[WORD_SIZE-1:0] data_reg; From dd82205e8763726699157401f22ccb6d21e565bc Mon Sep 17 00:00:00 2001 From: Clstilmldy Date: Wed, 7 Jan 2026 18:02:40 +0800 Subject: [PATCH 3/4] Feat: Solve the issue of different Verilator versions supporting -Wno-GENUNNAMED. Older versions, such as Verilator v5.008, do not support it, but for newer versions of Verilator like v5.040, an error will occur if it is not added. --- Makefile | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index 5ff0dca6..270a5ecd 100644 --- a/Makefile +++ b/Makefile @@ -1,9 +1,15 @@ +ifeq ($(shell verilator -Wno-GENUNNAMED --version >/dev/null 2>&1 && echo YES),YES) + SUPPORTS_GENUNNAMED := -Wno-GENUNNAMED +endif + VERILATOR_FLAGS = \ - --cc --build --threads 4 --unroll-stmts 999999 -unroll-count 999999 --assert -Wall -Wno-BLKSEQ -Wno-UNUSED \ - -Wno-PINCONNECTEMPTY -Wno-DECLFILENAME -Wno-ENUMVALUE -Wno-GENUNNAMED -O3 -sv \ - $(VFLAGS) \ - -CFLAGS "-std=c++17 -march=native" \ - -LDFLAGS "-ldl" \ + --cc --build --threads 4 --unroll-stmts 999999 -unroll-count 999999 --assert -Wall \ + -Wno-BLKSEQ -Wno-UNUSED -Wno-PINCONNECTEMPTY -Wno-DECLFILENAME -Wno-ENUMVALUE \ + $(SUPPORTS_GENUNNAMED) \ + -O3 -sv \ + $(VFLAGS) \ + -CFLAGS "-std=c++17 -march=native" \ + -LDFLAGS "-ldl" \ -MAKEFLAGS -j$(nproc) \ -CFLAGS -DNOKONATA \ -CFLAGS -DCOSIM \ From ec9a7c7c41b029640d64a1f497f5fdfc7aaa9408 Mon Sep 17 00:00:00 2001 From: Clstilmldy Date: Wed, 7 Jan 2026 18:10:36 +0800 Subject: [PATCH 4/4] Fix: If `define ENABLE_FP is set in Config.sv, a compilation error will occur: "Can't find definition of variable: INT_FSGNJ_S". It seems that the naming has been modified to have the BM_ prefix, and this can be found in Include.sv. --- src/InstrDecoder.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/InstrDecoder.sv b/src/InstrDecoder.sv index d465d181..8fe74d6b 100644 --- a/src/InstrDecoder.sv +++ b/src/InstrDecoder.sv @@ -972,11 +972,11 @@ always_comb begin uop.fu = FU_INT; if (i32.fp.rm == 3'b000) - uop.opcode = INT_FSGNJ_S; + uop.opcode = /* INT_FSGNJ_S */ BM_FSGNJ_S; else if (i32.fp.rm == 3'b001) - uop.opcode = INT_FSGNJN_S; + uop.opcode = /* INT_FSGNJN_S */ BM_FSGNJN_S; else if (i32.fp.rm == 3'b010) - uop.opcode = INT_FSGNJX_S; + uop.opcode = /* INT_FSGNJX_S */ BM_FSGNJX_S; else invalidEnc = 1; end 5'b00101: begin