[EraVM] Add pre-commit test for Set AllowRegisterRenaming to 1

Even though in tests registers are marked with
renamable flag, MachineOperand::isRenamable
returns false for them, since AllowRegisterRenaming
is 0 by default.

Signed-off-by: Vladimir Radosavljevic <[email protected]>

Author: vladimirradosavljevic

llvm/test/CodeGen/EraVM/machine-cp-bwd-prop.mir

@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -x mir -run-pass machine-cp -verify-machineinstrs -compile-twice=false < %s | FileCheck %s
+
+--- |
+
+  target datalayout = "E-p:256:256-i256:256:256-S32-a:256:256"
+  target triple = "eravm"
+
+  define void @test(i256 %a, i256 %b) { ret void }
+
+...
+---
+name:            test
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r2, $r3
+    ; CHECK-LABEL: name: test
+    ; CHECK: liveins: $r2, $r3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $r4 = SUBrrr_s killed $r2, killed $r3, i256 0
+    ; CHECK-NEXT: $r1 = COPY killed $r4
+    ; CHECK-NEXT: RET 0, implicit $r1
+    renamable $r4 = SUBrrr_s killed renamable $r2, killed renamable $r3, i256 0
+    renamable $r1 = COPY killed renamable $r4
+    RET 0, implicit $r1

llvm/test/CodeGen/EraVM/machine-cp-fwd-prop.mir

@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -x mir -run-pass machine-cp -verify-machineinstrs -compile-twice=false < %s | FileCheck %s
+
+--- |
+
+  target datalayout = "E-p:256:256-i256:256:256-S32-a:256:256"
+  target triple = "eravm"
+
+  define void @test(i256 %a, i256 %b) { ret void }
+
+...
+---
+name:            test
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r2, $r3
+    ; CHECK-LABEL: name: test
+    ; CHECK: liveins: $r2, $r3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $r4 = COPY killed $r2
+    ; CHECK-NEXT: $r1 = SUBrrr_s killed $r4, killed $r3, i256 0
+    ; CHECK-NEXT: RET 0, implicit $r1
+    renamable $r4 = COPY killed renamable $r2
+    renamable $r1 = SUBrrr_s killed renamable $r4, killed renamable $r3, i256 0
+    RET 0, implicit $r1