[EraVM] Add pre-commit tests for Fix two non-commutative arith patterns

Add tests where large_imm as a first operand is not
selected for non-commutative arith instructions. Disable
EraVMCombineAddressingMode pass in these tests, so
`add const, r0, rN` is not combined with uses in
combineMoveImmUse.

Signed-off-by: Vladimir Radosavljevic <[email protected]>

Author: vladimirradosavljevic

llvm/test/CodeGen/EraVM/rol.ll

@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --disable-eravm-scalar-opt-passes < %s | FileCheck %s
+; RUN: llc --disable-eravm-scalar-opt-passes -enable-eravm-combine-addressing-mode=false < %s | FileCheck %s
 
 target datalayout = "E-p:256:256-i256:256:256-S32-a:256:256"
 target triple = "eravm"
@@ -58,6 +58,20 @@ entry:
   ret i256 %or
 }
 
+define i256 @rolcrr_cp(i256 %rs1) {
+; CHECK-LABEL: rolcrr_cp:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    add @CPI4_0[0], r0, r2
+; CHECK-NEXT:    rol r2, r1, r1
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub i256 256, %rs1
+  %shl = shl i256 123456789, %rs1
+  %lshr = lshr i256 123456789, %sub
+  %or = or i256 %shl, %lshr
+  ret i256 %or
+}
+
 define i256 @rolyrr(i256 %rs1) {
 ; CHECK-LABEL: rolyrr:
 ; CHECK:       ; %bb.0: ; %entry
@@ -168,6 +182,23 @@ entry:
   ret void
 }
 
+define void @rolcrs_cp(i256 %rs1) {
+; CHECK-LABEL: rolcrs_cp:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    nop stack+=[1 + r0]
+; CHECK-NEXT:    add @CPI12_0[0], r0, r2
+; CHECK-NEXT:    rol r2, r1, stack-[1]
+; CHECK-NEXT:    ret
+entry:
+  %destptr = alloca i256
+  %sub = sub i256 256, %rs1
+  %shl = shl i256 123456789, %rs1
+  %lshr = lshr i256 123456789, %sub
+  %or = or i256 %shl, %lshr
+  store i256 %or, i256* %destptr
+  ret void
+}
+
 define void @rolyrs(i256 %rs1) {
 ; CHECK-LABEL: rolyrs:
 ; CHECK:       ; %bb.0: ; %entry

llvm/test/CodeGen/EraVM/ror.ll

@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --disable-eravm-scalar-opt-passes < %s | FileCheck %s
+; RUN: llc --disable-eravm-scalar-opt-passes -enable-eravm-combine-addressing-mode=false < %s | FileCheck %s
 
 target datalayout = "E-p:256:256-i256:256:256-S32-a:256:256"
 target triple = "eravm"
@@ -56,6 +56,20 @@ entry:
   ret i256 %or
 }
 
+define i256 @rorcrr_cp(i256 %rs1) {
+; CHECK-LABEL: rorcrr_cp:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    add @CPI4_0[0], r0, r2
+; CHECK-NEXT:    ror r2, r1, r1
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub i256 256, %rs1
+  %lshr = lshr i256 123456789, %rs1
+  %shl = shl i256 123456789, %sub
+  %or = or i256 %shl, %lshr
+  ret i256 %or
+}
+
 define i256 @roryrr(i256 %rs1) {
 ; CHECK-LABEL: roryrr:
 ; CHECK:       ; %bb.0: ; %entry
@@ -164,6 +178,23 @@ entry:
   ret void
 }
 
+define void @rorcrs_cp(i256 %rs1) {
+; CHECK-LABEL: rorcrs_cp:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    nop stack+=[1 + r0]
+; CHECK-NEXT:    add @CPI12_0[0], r0, r2
+; CHECK-NEXT:    ror r2, r1, stack-[1]
+; CHECK-NEXT:    ret
+entry:
+  %destptr = alloca i256
+  %sub = sub i256 256, %rs1
+  %lshr = lshr i256 123456789, %rs1
+  %shl = shl i256 123456789, %sub
+  %or = or i256 %shl, %lshr
+  store i256 %or, i256* %destptr
+  ret void
+}
+
 define void @roryrs(i256 %rs1) {
 ; CHECK-LABEL: roryrs:
 ; CHECK:       ; %bb.0: ; %entry

llvm/test/CodeGen/EraVM/shl.ll

@@ -1,4 +1,4 @@
-; RUN: llc --disable-eravm-scalar-opt-passes < %s | FileCheck %s
+; RUN: llc --disable-eravm-scalar-opt-passes -enable-eravm-combine-addressing-mode=false < %s | FileCheck %s
 
 target datalayout = "E-p:256:256-i256:256:256-S32-a:256:256"
 target triple = "eravm"
@@ -34,6 +34,13 @@ define i256 @shlcrr(i256 %rs1) nounwind {
   ret i256 %res
 }
 
+; CHECK-LABEL: shlcrr_cp
+define i256 @shlcrr_cp(i256 %rs1) nounwind {
+; CHECK: shl r2, r1, r1
+  %res = shl i256 123456789, %rs1
+  ret i256 %res
+}
+
 ; CHECK-LABEL: shlyrr
 define i256 @shlyrr(i256 %rs1) nounwind {
 ; CHECK: shl.s @val[0], r1, r1
@@ -97,6 +104,15 @@ define void @shlcrs(i256 %rs1) nounwind {
   ret void
 }
 
+; CHECK-LABEL: shlcrs_cp
+define void @shlcrs_cp(i256 %rs1) nounwind {
+  %valptr = alloca i256
+; CHECK: shl r2, r1, stack-[1]
+  %res = shl i256 123456789, %rs1
+  store i256 %res, i256* %valptr
+  ret void
+}
+
 ; CHECK-LABEL: shlyrs
 define void @shlyrs(i256 %rs1) nounwind {
   %valptr = alloca i256

llvm/test/CodeGen/EraVM/shr.ll

@@ -1,4 +1,4 @@
-; RUN: llc --disable-eravm-scalar-opt-passes < %s | FileCheck %s
+; RUN: llc --disable-eravm-scalar-opt-passes -enable-eravm-combine-addressing-mode=false < %s | FileCheck %s
 
 target datalayout = "E-p:256:256-i256:256:256-S32-a:256:256"
 target triple = "eravm"
@@ -34,6 +34,13 @@ define i256 @shrcrr(i256 %rs1) nounwind {
   ret i256 %res
 }
 
+; CHECK-LABEL: shrcrr_cp
+define i256 @shrcrr_cp(i256 %rs1) nounwind {
+; CHECK: shr r2, r1, r1
+  %res = lshr i256 123456789, %rs1
+  ret i256 %res
+}
+
 ; CHECK-LABEL: shryrr
 define i256 @shryrr(i256 %rs1) nounwind {
 ; CHECK: shr.s @val[0], r1, r1
@@ -97,6 +104,15 @@ define void @shrcrs(i256 %rs1) nounwind {
   ret void
 }
 
+; CHECK-LABEL: shrcrs_cp
+define void @shrcrs_cp(i256 %rs1) nounwind {
+  %valptr = alloca i256
+; CHECK: shr r2, r1, stack-[1]
+  %res = lshr i256 123456789, %rs1
+  store i256 %res, i256* %valptr
+  ret void
+}
+
 ; CHECK-LABEL: shryrs
 define void @shryrs(i256 %rs1) nounwind {
   %valptr = alloca i256

llvm/test/CodeGen/EraVM/sub.ll

@@ -1,4 +1,4 @@
-; RUN: llc --disable-eravm-scalar-opt-passes < %s | FileCheck %s
+; RUN: llc --disable-eravm-scalar-opt-passes -enable-eravm-combine-addressing-mode=false < %s | FileCheck %s
 
 target datalayout = "E-p:256:256-i256:256:256-S32-a:256:256"
 target triple = "eravm"
@@ -41,6 +41,13 @@ define i256 @subcrr(i256 %rs1) nounwind {
   ret i256 %res
 }
 
+; CHECK-LABEL: subcrr_cp
+define i256 @subcrr_cp(i256 %rs1) nounwind {
+; CHECK: sub r2, r1, r1
+  %res = sub i256 123456789, %rs1
+  ret i256 %res
+}
+
 ; CHECK-LABEL: subyrr
 define i256 @subyrr(i256 %rs1) nounwind {
 ; CHECK: sub.s @val[0], r1, r1
@@ -104,6 +111,15 @@ define void @subcrs(i256 %rs1) nounwind {
   ret void 
 }
 
+; CHECK-LABEL: subcrs_cp
+define void @subcrs_cp(i256 %rs1) nounwind {
+  %valptr = alloca i256
+; CHECK: sub r2, r1, stack-[1]
+  %res = sub i256 123456789, %rs1
+  store i256 %res, i256* %valptr
+  ret void
+}
+
 ; CHECK-LABEL: subyrs
 define void @subyrs(i256 %rs1) nounwind {
   %valptr = alloca i256