[EraVM][EVM] Add renamable bit to copyPhysReg

Signed-off-by: Vladimir Radosavljevic <[email protected]>

Author: vladimirradosavljevic

llvm/lib/Target/EVM/EVMInstrInfo.cpp

@@ -36,7 +36,8 @@ bool EVMInstrInfo::isReallyTriviallyReMaterializable(
 void EVMInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator I,
                                const DebugLoc &DL, MCRegister DestReg,
-                               MCRegister SrcReg, bool KillSrc) const {
+                               MCRegister SrcReg, bool KillSrc,
+                               bool RenamableDest, bool RenamableSrc) const {
   // This method is called by post-RA expansion, which expects only
   // phys registers to exist. However we expect only virtual here.
   assert(Register::isVirtualRegister(DestReg) &&

llvm/lib/Target/EVM/EVMInstrInfo.h

@@ -44,7 +44,8 @@ class EVMInstrInfo final : public EVMGenInstrInfo {
 
   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+                   bool KillSrc, bool RenamableDest = false,
+                   bool RenamableSrc = false) const override;
 
   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                      MachineBasicBlock *&FBB,

llvm/lib/Target/EraVM/EraVMInstrInfo.cpp

@@ -607,13 +607,15 @@ MachineInstr *EraVMInstrInfo::insertDecSP(MachineBasicBlock &MBB,
 void EraVMInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator I,
                                  const DebugLoc &DL, MCRegister DestReg,
-                                 MCRegister SrcReg, bool KillSrc) const {
+                                 MCRegister SrcReg, bool KillSrc,
+                                 bool RenamableDest, bool RenamableSrc) const {
   unsigned opcode = I->getFlag(MachineInstr::MIFlag::IsFatPtr)
                         ? EraVM::PTR_ADDrrr_s
                         : EraVM::ADDrrr_s;
 
   BuildMI(MBB, I, DL, get(opcode), DestReg)
-      .addReg(SrcReg, getKillRegState(KillSrc))
+      .addReg(SrcReg,
+              getKillRegState(KillSrc) | getRenamableRegState(RenamableSrc))
       .addReg(EraVM::R0)
       .addImm(EraVMCC::COND_NONE);
 }

llvm/lib/Target/EraVM/EraVMInstrInfo.h

@@ -255,7 +255,8 @@ class EraVMInstrInfo : public EraVMGenInstrInfo {
 
   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
-                   bool KillSrc) const override;
+                   bool KillSrc, bool RenamableDest = false,
+                   bool RenamableSrc = false) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI, Register SrcReg,

llvm/test/CodeGen/EraVM/renamable-copy.mir

@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -x mir -run-pass postrapseudos -verify-machineinstrs -compile-twice=false < %s | FileCheck %s
+
+--- |
+
+  target datalayout = "E-p:256:256-i256:256:256-S32-a:256:256"
+  target triple = "eravm"
+
+  define void @test() { ret void }
+
+...
+---
+name:            test
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r2
+    ; CHECK-LABEL: name: test
+    ; CHECK: liveins: $r2
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $r1 = ADDrrr_s killed renamable $r2, $r0, 0
+    ; CHECK-NEXT: RET 0, implicit $r1
+    renamable $r1 = COPY killed renamable $r2
+    RET 0, implicit $r1