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[EraVM][TableGen] Rename instruction defs according to new syntax
Rename load/store as well as several special instructions to reflect their current names according to new syntax. Remove trailing "r" from several instructions that only have a fixed set of supported operands and would need "rr" or "rrr" suffix anyway.
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8 files changed

+49
-49
lines changed

8 files changed

+49
-49
lines changed

‎llvm/lib/Target/EraVM/EraVMCombineToIndexedMemops.cpp‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -72,17 +72,17 @@ class EraVMCombineToIndexedMemops : public MachineFunctionPass {
7272
private:
7373
// map <non-inc opcode> -> <inc opcode>
7474
const DenseMap<unsigned, unsigned> PostIncOpcMap = {
75-
{EraVM::LD, EraVM::LDInc}, {EraVM::LD1r, EraVM::LD1Incr},
76-
{EraVM::LD2r, EraVM::LD2Incr}, {EraVM::ST1r, EraVM::ST1Incr},
77-
{EraVM::ST2r, EraVM::ST2Incr},
75+
{EraVM::LDP, EraVM::LDPI}, {EraVM::LDMhr, EraVM::LDMIhr},
76+
{EraVM::LDMahr, EraVM::LDMIahr}, {EraVM::STMhr, EraVM::STMIhr},
77+
{EraVM::STMahr, EraVM::STMIahr},
7878
};
7979

8080
llvm::Register getLoadStoreOffsetRegister(MachineInstr *MI) const {
81-
if (MI->getOpcode() == EraVM::LD1r || MI->getOpcode() == EraVM::LD2r ||
82-
MI->getOpcode() == EraVM::LD) {
81+
if (MI->getOpcode() == EraVM::LDMhr || MI->getOpcode() == EraVM::LDMahr ||
82+
MI->getOpcode() == EraVM::LDP) {
8383
return MI->getOperand(1).getReg();
8484
}
85-
if (MI->getOpcode() == EraVM::ST1r || MI->getOpcode() == EraVM::ST2r) {
85+
if (MI->getOpcode() == EraVM::STMhr || MI->getOpcode() == EraVM::STMahr) {
8686
return MI->getOperand(0).getReg();
8787
}
8888
llvm_unreachable("unexpected opcode");
@@ -203,7 +203,7 @@ bool EraVMCombineToIndexedMemops::runOnMachineFunction(MachineFunction &MF) {
203203
map_range(
204204
make_filter_range(RegInfo->use_instructions(OffsetReg),
205205
[&MI, this](MachineInstr &CurrentMI) {
206-
bool checkFatPtr = MI.getOpcode() == EraVM::LD;
206+
bool checkFatPtr = MI.getOpcode() == EraVM::LDP;
207207
unsigned addOpcode = checkFatPtr ?
208208
EraVM::PTR_ADDxrr_s :
209209
EraVM::ADDirr_s;
@@ -228,8 +228,8 @@ bool EraVMCombineToIndexedMemops::runOnMachineFunction(MachineFunction &MF) {
228228
++NumIndexedMemOpCombined;
229229
Changed = true;
230230
Register IncrementedOffsetReg = RegInfo->createVirtualRegister(
231-
MI.getOpcode() == EraVM::LD ? &EraVM::GRPTRRegClass
232-
: &EraVM::GR256RegClass);
231+
MI.getOpcode() == EraVM::LDP ? &EraVM::GRPTRRegClass
232+
: &EraVM::GR256RegClass);
233233
MachineInstr *MemIncInst = replaceWithIndexed(MI, IncrementedOffsetReg);
234234
eraseAndReplaceUses(Add32ToRemove, IncrementedOffsetReg);
235235

‎llvm/lib/Target/EraVM/EraVMHoistFlagSetting.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -145,11 +145,11 @@ static bool isValidCandidate(const MachineInstr &MI, const EraVMInstrInfo *TII,
145145
switch (MI.getOpcode()) {
146146
default:
147147
break;
148-
case EraVM::LDInc:
149-
case EraVM::LD1Incr:
150-
case EraVM::LD2Incr:
151-
case EraVM::ST1Incr:
152-
case EraVM::ST2Incr:
148+
case EraVM::LDPI:
149+
case EraVM::LDMIhr:
150+
case EraVM::LDMIahr:
151+
case EraVM::STMIhr:
152+
case EraVM::STMIahr:
153153
return true;
154154
}
155155
}

‎llvm/lib/Target/EraVM/EraVMISelDAGToDAG.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -403,7 +403,7 @@ void EraVMDAGToDAGISel::Select(SDNode *Node) {
403403
SDValue Chain = ld->getChain();
404404
SDValue Ptr = ld->getBasePtr();
405405
auto Zero = CurDAG->getTargetConstant(0, DL, MVT::i256);
406-
auto *LD = CurDAG->getMachineNode(EraVM::LD, DL, ld->getMemoryVT(),
406+
auto *LD = CurDAG->getMachineNode(EraVM::LDP, DL, ld->getMemoryVT(),
407407
MVT::Other, Ptr, Zero, Chain);
408408
ReplaceNode(Node, LD);
409409
return;

‎llvm/lib/Target/EraVM/EraVMInstrInfo.td‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -981,18 +981,18 @@ multiclass HeapLoadInc<EraVMOpcode opcode> {
981981
}
982982
}
983983

984-
defm LD1 : HeapLoad<OpLoadHeap, load_heap>;
985-
defm LD2 : HeapLoad<OpLoadAuxHeap, load_heapaux>;
986-
defm LD1Inc : HeapLoadInc<OpLoadHeapInc>;
987-
defm LD2Inc : HeapLoadInc<OpLoadAuxHeapInc>;
984+
defm LDMh : HeapLoad<OpLoadHeap, load_heap>;
985+
defm LDMah : HeapLoad<OpLoadAuxHeap, load_heapaux>;
986+
defm LDMIh : HeapLoadInc<OpLoadHeapInc>;
987+
defm LDMIah : HeapLoadInc<OpLoadAuxHeapInc>;
988988

989-
defm LDst : HeapLoad<OpStaticRead, load_static>;
990-
defm LDstInc : HeapLoadInc<OpStaticReadInc>;
989+
defm LDMst : HeapLoad<OpStaticRead, load_static>;
990+
defm LDMIst : HeapLoadInc<OpStaticReadInc>;
991991

992992
let mayLoad = 1 in {
993-
def LD : IUMAr_r<OpLoadPtr, (outs GR256:$rd0), (ins GRPTR:$rs0),
993+
def LDP : IUMAr_r<OpLoadPtr, (outs GR256:$rd0), (ins GRPTR:$rs0),
994994
"$rs0, $rd0", []>;
995-
def LDInc : IUMAr_rr<OpLoadPtrInc, (outs GR256:$rd0, GRPTR:$rd1), (ins GRPTR:$rs0),
995+
def LDPI : IUMAr_rr<OpLoadPtrInc, (outs GR256:$rd0, GRPTR:$rd1), (ins GRPTR:$rs0),
996996
"$rs0, $rd0, $rd1", []>;
997997
}
998998

@@ -1014,13 +1014,13 @@ multiclass HeapStoreInc<EraVMOpcode opcode> {
10141014
}
10151015
}
10161016

1017-
defm ST1 : HeapStore<OpStoreHeap, store_heap>;
1018-
defm ST2 : HeapStore<OpStoreAuxHeap, store_heapaux>;
1019-
defm ST1Inc : HeapStoreInc<OpStoreHeapInc>;
1020-
defm ST2Inc : HeapStoreInc<OpStoreAuxHeapInc>;
1017+
defm STMh : HeapStore<OpStoreHeap, store_heap>;
1018+
defm STMah : HeapStore<OpStoreAuxHeap, store_heapaux>;
1019+
defm STMIh : HeapStoreInc<OpStoreHeapInc>;
1020+
defm STMIah : HeapStoreInc<OpStoreAuxHeapInc>;
10211021

1022-
defm STst : HeapStore<OpStaticWrite, store_static>;
1023-
defm STstInc : HeapStoreInc<OpStaticWriteInc>;
1022+
defm STMst : HeapStore<OpStaticWrite, store_static>;
1023+
defm STMIst : HeapStoreInc<OpStaticWriteInc>;
10241024

10251025
//===----------------------------------------------------------------------===//
10261026
// Control flow instructions
@@ -1193,44 +1193,44 @@ def CTXIncTx : IContext_<OpContextIncrementTxNumber, (outs), (ins), "", [(int_
11931193
//===----------------------------------------------------------------------===//
11941194
// Fat Pointer
11951195
//===----------------------------------------------------------------------===//
1196-
def SLDrr : ILogRr_r<OpSload, (outs GR256:$rd0), (ins GR256:$rs0),
1196+
def LDS : ILogRr_r<OpSload, (outs GR256:$rd0), (ins GR256:$rs0),
11971197
"$rs0, $rd0",
11981198
[(set GR256:$rd0, (load_storage GR256:$rs0))]>;
1199-
def TLDrr : ILogRr_r<OpTransientLoad, (outs GR256:$rd0), (ins GR256:$rs0),
1199+
def LDT : ILogRr_r<OpTransientLoad, (outs GR256:$rd0), (ins GR256:$rs0),
12001200
"$rs0, $rd0",
12011201
[(set GR256:$rd0, (load_transient GR256:$rs0))]>;
12021202

12031203
let hasSideEffects = 1 in {
1204-
def SSTr : ILogRrr_<OpSstore, (outs), (ins GR256:$rs0, GR256:$rs1),
1204+
def STS : ILogRrr_<OpSstore, (outs), (ins GR256:$rs0, GR256:$rs1),
12051205
"$rs0, $rs1",
12061206
[(store_storage GR256:$rs1, GR256:$rs0)]>;
1207-
def TSTr : ILogRrr_<OpTransientStore, (outs), (ins GR256:$rs0, GR256:$rs1),
1207+
def STT : ILogRrr_<OpTransientStore, (outs), (ins GR256:$rs0, GR256:$rs1),
12081208
"$rs0, $rs1",
12091209
[(store_transient GR256:$rs1, GR256:$rs0)]>;
12101210
}
12111211

12121212
let hasSideEffects = 1 in {
1213-
def L1r : ILogRrr_<OpLogToL1, (outs), (ins GR256:$rs0, GR256:$rs1),
1213+
def LOGL1 : ILogRrr_<OpLogToL1, (outs), (ins GR256:$rs0, GR256:$rs1),
12141214
"$rs0, $rs1",
12151215
[(int_eravm_tol1 GR256:$rs0, GR256:$rs1, 0)]>;
1216-
def L1Firstr : ILogRrr_<OpLogToL1First, (outs), (ins GR256:$rs0, GR256:$rs1),
1216+
def LOGL1I : ILogRrr_<OpLogToL1Initial, (outs), (ins GR256:$rs0, GR256:$rs1),
12171217
"$rs0, $rs1",
12181218
[(int_eravm_tol1 GR256:$rs0, GR256:$rs1, 1)]>;
12191219

1220-
def EVTr : ILogRrr_<OpLogEvent, (outs), (ins GR256:$rs0, GR256:$rs1),
1220+
def LOG : ILogRrr_<OpLogEvent, (outs), (ins GR256:$rs0, GR256:$rs1),
12211221
"$rs0, $rs1",
12221222
[(int_eravm_event GR256:$rs0, GR256:$rs1, 0)]>;
12231223

1224-
def EVTFirstr : ILogRrr_<OpLogEventFirst, (outs), (ins GR256:$rs0, GR256:$rs1),
1224+
def LOGI : ILogRrr_<OpLogEventInitial, (outs), (ins GR256:$rs0, GR256:$rs1),
12251225
"$rs0, $rs1",
12261226
[(int_eravm_event GR256:$rs0, GR256:$rs1, 1)]>;
12271227

1228-
def PCOMPr : ILogRrr_r<OpLogPrecompile, (outs GR256:$rd0), (ins GR256:$rs0, GR256:$rs1),
1228+
def CALLP : ILogRrr_r<OpLogPrecompile, (outs GR256:$rd0), (ins GR256:$rs0, GR256:$rs1),
12291229
"$rs0, $rs1, $rd0",
12301230
[(set GR256:$rd0, (int_eravm_precompile GR256:$rs0, GR256:$rs1))]>;
12311231
}
12321232

1233-
def DECOMMITr : ILogRrr_r<OpDecommit, (outs GRPTR:$rd0), (ins GR256:$rs0, GR256:$rs1),
1233+
def DCMT : ILogRrr_r<OpDecommit, (outs GRPTR:$rd0), (ins GR256:$rs0, GR256:$rs1),
12341234
"$rs0, $rs1, $rd0",
12351235
[(set GRPTR:$rd0, (EraVMlog_decommit GR256:$rs0, GR256:$rs1))]>;
12361236

‎llvm/lib/Target/EraVM/EraVMOpcodes.td‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -174,11 +174,11 @@ def OpContextIncrementTxNumber : EraVMOpcode<"context.inc_tx_num", 1049, D
174174
def OpSload : EraVMOpcode<"sload", 1050, DirectEncoding>;
175175
def OpSstore : EraVMOpcode<"sstore", 1051, DirectEncoding>;
176176

177-
def OpLogToL1 : EraVMOpcode<"to_l1", 1052, DirectEncoding>; // is_first ⇒ 1052 + is_first
178-
def OpLogToL1First : EraVMOpcode<"to_l1.first", 1053, DirectEncoding>;
179-
def OpLogEvent : EraVMOpcode<"event", 1054, DirectEncoding>; // is_first ⇒ 1054 + is_first
180-
def OpLogEventFirst : EraVMOpcode<"event.first", 1055, DirectEncoding>;
181-
def OpLogPrecompile : EraVMOpcode<"precompile", 1056, DirectEncoding>;
177+
def OpLogToL1 : EraVMOpcode<"to_l1", 1052, DirectEncoding>; // is_first ⇒ 1052 + is_first
178+
def OpLogToL1Initial : EraVMOpcode<"to_l1.first", 1053, DirectEncoding>;
179+
def OpLogEvent : EraVMOpcode<"event", 1054, DirectEncoding>; // is_first ⇒ 1054 + is_first
180+
def OpLogEventInitial : EraVMOpcode<"event.first", 1055, DirectEncoding>;
181+
def OpLogPrecompile : EraVMOpcode<"precompile", 1056, DirectEncoding>;
182182

183183
def OpFarcall : EraVMOpcode<"far_call", 1057, FarCallEncoding>; // is_shard is_static ⇒ 1057 + 2 × is_static + is_shard
184184
def OpDelegate : EraVMOpcode<"far_call.delegate", 1061, FarCallEncoding>; // is_shard is_static ⇒ 1061 + 2 × is_static + is_shard

‎llvm/test/CodeGen/EraVM/indexed-memops-ldinc.mir‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@
2424
...
2525
---
2626
# CHECK-LABEL: test
27-
# CHECK: %1:gr256, %5:grptr = LDInc %0, 0
27+
# CHECK: %1:gr256, %5:grptr = LDPI %0, 0
2828

2929
name: test
3030
alignment: 1
@@ -82,9 +82,9 @@ body: |
8282
liveins: $r1
8383
8484
%0:grptr = COPY $r1
85-
%1:gr256 = LD %0, i256 0
85+
%1:gr256 = LDP %0, i256 0
8686
%2:grptr = PTR_ADDxrr_s i256 32, %0, 0
87-
%3:gr256 = LD killed %2, i256 0
87+
%3:gr256 = LDP killed %2, i256 0
8888
%4:gr256 = ADDrrr_s killed %1, killed %3, 0
8989
$r1 = COPY %4
9090
RET i256 0, implicit $r1

‎llvm/test/CodeGen/EraVM/phi-node-elimination-fatptr-tag.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,7 @@ body: |
117117
118118
bb.3.exit:
119119
%2:grptr = PHI %1, %bb.2, %0, %bb.1
120-
%6:gr256 = LD killed %2, i256 0
120+
%6:gr256 = LDP killed %2, i256 0
121121
$r1 = COPY killed %6
122122
RET i256 0, implicit killed $r1
123123

‎llvm/test/CodeGen/EraVM/select_fold.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -321,7 +321,7 @@ tracksRegLiveness: true
321321
body: |
322322
bb.0:
323323
liveins: $r1, $r2
324-
$r2 = LD1r $r1, 0
324+
$r2 = LDMhr $r1, 0
325325
$r1 = ADDrrr_s killed $r2, $r0, 9, implicit $flags
326326
RET 0
327327
...

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