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[TII][RISCV] Add renamable bit to copyPhysReg (#91179)
The renamable flag is useful during MachineCopyPropagation but renamable flag will be dropped after lowerCopy in some case. This patch introduces extra arguments to pass the renamable flag to copyPhysReg.
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57 files changed

+159
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lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1007,10 +1007,16 @@ class TargetInstrInfo : public MCInstrInfo {
10071007
/// The source and destination registers may overlap, which may require a
10081008
/// careful implementation when multiple copy instructions are required for
10091009
/// large registers. See for example the ARM target.
1010+
///
1011+
/// If RenamableDest is true, the copy instruction's destination operand is
1012+
/// marked renamable.
1013+
/// If RenamableSrc is true, the copy instruction's source operand is
1014+
/// marked renamable.
10101015
virtual void copyPhysReg(MachineBasicBlock &MBB,
10111016
MachineBasicBlock::iterator MI, const DebugLoc &DL,
1012-
MCRegister DestReg, MCRegister SrcReg,
1013-
bool KillSrc) const {
1017+
MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
1018+
bool RenamableDest = false,
1019+
bool RenamableSrc = false) const {
10141020
llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
10151021
}
10161022

‎llvm/lib/CodeGen/TargetInstrInfo.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -743,7 +743,9 @@ void TargetInstrInfo::lowerCopy(MachineInstr *MI,
743743
}
744744

745745
copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), DstMO.getReg(),
746-
SrcMO.getReg(), SrcMO.isKill());
746+
SrcMO.getReg(), SrcMO.isKill(),
747+
DstMO.getReg().isPhysical() ? DstMO.isRenamable() : false,
748+
SrcMO.getReg().isPhysical() ? SrcMO.isRenamable() : false);
747749

748750
if (MI->getNumOperands() > 2)
749751
transferImplicitOperands(MI, TRI);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3512,7 +3512,9 @@ void AArch64InstrInfo::copyGPRRegTuple(MachineBasicBlock &MBB,
35123512
void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
35133513
MachineBasicBlock::iterator I,
35143514
const DebugLoc &DL, MCRegister DestReg,
3515-
MCRegister SrcReg, bool KillSrc) const {
3515+
MCRegister SrcReg, bool KillSrc,
3516+
bool RenamableDest,
3517+
bool RenamableSrc) const {
35163518
if (AArch64::GPR32spRegClass.contains(DestReg) &&
35173519
(AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
35183520
const TargetRegisterInfo *TRI = &getRegisterInfo();

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -179,7 +179,8 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
179179
llvm::ArrayRef<unsigned> Indices) const;
180180
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
181181
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
182-
bool KillSrc) const override;
182+
bool KillSrc, bool RenamableDest = false,
183+
bool RenamableSrc = false) const override;
183184

184185
void storeRegToStackSlot(MachineBasicBlock &MBB,
185186
MachineBasicBlock::iterator MBBI, Register SrcReg,

‎llvm/lib/Target/AMDGPU/R600InstrInfo.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,8 @@ bool R600InstrInfo::isVector(const MachineInstr &MI) const {
4040
void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4141
MachineBasicBlock::iterator MI,
4242
const DebugLoc &DL, MCRegister DestReg,
43-
MCRegister SrcReg, bool KillSrc) const {
43+
MCRegister SrcReg, bool KillSrc,
44+
bool RenamableDest, bool RenamableSrc) const {
4445
unsigned VectorComponents = 0;
4546
if ((R600::R600_Reg128RegClass.contains(DestReg) ||
4647
R600::R600_Reg128VerticalRegClass.contains(DestReg)) &&

‎llvm/lib/Target/AMDGPU/R600InstrInfo.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,8 @@ class R600InstrInfo final : public R600GenInstrInfo {
7373

7474
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
7575
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
76-
bool KillSrc) const override;
76+
bool KillSrc, bool RenamableDest = false,
77+
bool RenamableSrc = false) const override;
7778
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
7879
MachineBasicBlock::iterator MBBI) const override;
7980

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -720,7 +720,8 @@ static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
720720
void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
721721
MachineBasicBlock::iterator MI,
722722
const DebugLoc &DL, MCRegister DestReg,
723-
MCRegister SrcReg, bool KillSrc) const {
723+
MCRegister SrcReg, bool KillSrc,
724+
bool RenamableDest, bool RenamableSrc) const {
724725
const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg);
725726

726727
// FIXME: This is hack to resolve copies between 16 bit and 32 bit

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -234,7 +234,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
234234

235235
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
236236
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
237-
bool KillSrc) const override;
237+
bool KillSrc, bool RenamableDest = false,
238+
bool RenamableSrc = false) const override;
238239

239240
void materializeImmediate(MachineBasicBlock &MBB,
240241
MachineBasicBlock::iterator MI, const DebugLoc &DL,

‎llvm/lib/Target/ARC/ARCInstrInfo.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -281,7 +281,8 @@ unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
281281
void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
282282
MachineBasicBlock::iterator I,
283283
const DebugLoc &DL, MCRegister DestReg,
284-
MCRegister SrcReg, bool KillSrc) const {
284+
MCRegister SrcReg, bool KillSrc,
285+
bool RenamableDest, bool RenamableSrc) const {
285286
assert(ARC::GPR32RegClass.contains(SrcReg) &&
286287
"Only GPR32 src copy supported.");
287288
assert(ARC::GPR32RegClass.contains(DestReg) &&

‎llvm/lib/Target/ARC/ARCInstrInfo.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,8 @@ class ARCInstrInfo : public ARCGenInstrInfo {
6565

6666
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
6767
const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
68-
bool KillSrc) const override;
68+
bool KillSrc, bool RenamableDest = false,
69+
bool RenamableSrc = false) const override;
6970

7071
void storeRegToStackSlot(MachineBasicBlock &MBB,
7172
MachineBasicBlock::iterator MI, Register SrcReg,

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