[EraVM] Add memref to instructions with constant pool operand

This will allow for MachineInstr queries to work properly
(e.g. isDereferenceableInvariantLoad), so passes like
MachineCSE, MachineSink, MachineLICM can optimize these
instructions.

Signed-off-by: Vladimir Radosavljevic <[email protected]>

Author: vladimirradosavljevic

llvm/lib/Target/EraVM/EraVMISelDAGToDAG.cpp

@@ -358,14 +358,6 @@ void EraVMDAGToDAGISel::Select(SDNode *Node) {
       SDValue CP =
           CurDAG->getTargetConstantPool(cn->getConstantIntValue(), PtrVT);
       auto *lc = CurDAG->getMachineNode(EraVM::LOADCONST, DL, MVT::i256, CP);
-
-      // Annotate the Node with memory operand information so that MachineInstr
-      // queries work properly.
-      MachineFunction &MF = CurDAG->getMachineFunction();
-      MachineMemOperand *MemOp =
-          MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
-                                  MachineMemOperand::MOLoad, 32, Align(32));
-      CurDAG->setNodeMemRefs(cast<MachineSDNode>(lc), {MemOp});
       ReplaceNode(Node, lc);
       return;
     }

llvm/lib/Target/EraVM/EraVMISelLowering.cpp

@@ -1479,3 +1479,21 @@ void EraVMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
     EraVM::out0Iterator(MI)->setIsEarlyClobber();
   }
 }
+
+void EraVMTargetLowering::finalizeLowering(MachineFunction &MF) const {
+  for (MachineBasicBlock &MBB : MF) {
+    for (MachineInstr &MI : MBB) {
+      if (none_of(MI.operands(),
+                  [](const MachineOperand &MO) { return MO.isCPI(); }))
+        continue;
+
+      // Annotate this instruction with memory operand information so that
+      // MachineInstr queries work properly.
+      MachineMemOperand *MemOp =
+          MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
+                                  MachineMemOperand::MOLoad, 32, Align(32));
+      MI.addMemOperand(MF, MemOp);
+    }
+  }
+  TargetLoweringBase::finalizeLowering(MF);
+}

llvm/lib/Target/EraVM/EraVMISelLowering.h

@@ -205,6 +205,8 @@ class EraVMTargetLowering : public TargetLowering {
   void AdjustInstrPostInstrSelection(MachineInstr &MI,
                                      SDNode *Node) const override;
 
+  void finalizeLowering(MachineFunction &MF) const override;
+
 private:
   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
                                bool isVarArg,

llvm/test/CodeGen/EraVM/machinesink-inst-with-cp-operand.ll

@@ -9,10 +9,10 @@ declare void @use(i256)
 define i256 @test(i256 %in, i1 %cond) {
 ; CHECK-LABEL: test:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    and @CPI0_0[0], r1, r1
 ; CHECK-NEXT:    sub! r2, r0, r2
 ; CHECK-NEXT:    jump.eq @.BB0_2
 ; CHECK-NEXT:  ; %bb.1: ; %bb1
+; CHECK-NEXT:    and @CPI0_0[0], r1, r1
 ; CHECK-NEXT:    near_call r0, @use, @DEFAULT_UNWIND
 ; CHECK-NEXT:    add r0, r0, r1
 ; CHECK-NEXT:    ret

llvm/test/CodeGen/EraVM/memintrinsics.ll

@@ -32,22 +32,20 @@ define fastcc void @huge_copysize1(i256 addrspace(1)* %dest, i256 addrspace(1)*
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    add @CPI1_0[0], r1, r3
 ; CHECK-NEXT:    add r2, r0, r4
-; CHECK-NEXT:    add r1, r0, r5
 ; CHECK-NEXT:  .BB1_1: ; %load-store-loop
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    ld.1.inc r4, r6, r4
-; CHECK-NEXT:    st.1.inc r5, r6, r5
-; CHECK-NEXT:    sub! r5, r3, r6
+; CHECK-NEXT:    ld.1.inc r4, r5, r4
+; CHECK-NEXT:    st.1.inc r1, r5, r1
+; CHECK-NEXT:    sub! r1, r3, r5
 ; CHECK-NEXT:    jump.ne @.BB1_1
 ; CHECK-NEXT:  ; %bb.2: ; %memcpy-split
-; CHECK-NEXT:    add @CPI1_0[0], r1, r1
-; CHECK-NEXT:    ld.1 r1, r3
-; CHECK-NEXT:    and @CPI1_1[0], r3, r3
+; CHECK-NEXT:    ld.1 r3, r1
+; CHECK-NEXT:    and @CPI1_1[0], r1, r1
 ; CHECK-NEXT:    add @CPI1_0[0], r2, r2
 ; CHECK-NEXT:    ld.1 r2, r2
 ; CHECK-NEXT:    and @CPI1_2[0], r2, r2
-; CHECK-NEXT:    or r2, r3, r2
-; CHECK-NEXT:    st.1 r1, r2
+; CHECK-NEXT:    or r2, r1, r1
+; CHECK-NEXT:    st.1 r3, r1
 ; CHECK-NEXT:    ret
   call void @llvm.memcpy.p1i256.p1i256.i256(i256 addrspace(1)* %dest, i256 addrspace(1)* %src, i256 81129638414606681695789005144065, i1 false)
   ret void
@@ -58,22 +56,20 @@ define fastcc void @huge_copysize2(i256 addrspace(2)* %dest, i256 addrspace(2)*
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    add @CPI2_0[0], r1, r3
 ; CHECK-NEXT:    add r2, r0, r4
-; CHECK-NEXT:    add r1, r0, r5
 ; CHECK-NEXT:  .BB2_1: ; %load-store-loop
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    ld.2.inc r4, r6, r4
-; CHECK-NEXT:    st.2.inc r5, r6, r5
-; CHECK-NEXT:    sub! r5, r3, r6
+; CHECK-NEXT:    ld.2.inc r4, r5, r4
+; CHECK-NEXT:    st.2.inc r1, r5, r1
+; CHECK-NEXT:    sub! r1, r3, r5
 ; CHECK-NEXT:    jump.ne @.BB2_1
 ; CHECK-NEXT:  ; %bb.2: ; %memcpy-split
-; CHECK-NEXT:    add @CPI2_0[0], r1, r1
-; CHECK-NEXT:    ld.2 r1, r3
-; CHECK-NEXT:    and @CPI2_1[0], r3, r3
+; CHECK-NEXT:    ld.2 r3, r1
+; CHECK-NEXT:    and @CPI2_1[0], r1, r1
 ; CHECK-NEXT:    add @CPI2_0[0], r2, r2
 ; CHECK-NEXT:    ld.2 r2, r2
 ; CHECK-NEXT:    and @CPI2_2[0], r2, r2
-; CHECK-NEXT:    or r2, r3, r2
-; CHECK-NEXT:    st.2 r1, r2
+; CHECK-NEXT:    or r2, r1, r1
+; CHECK-NEXT:    st.2 r3, r1
 ; CHECK-NEXT:    ret
   call void @llvm.memcpy.p2i256.p2i256.i256(i256 addrspace(2)* %dest, i256 addrspace(2)* %src, i256 81129638414606681695789005144065, i1 false)
   ret void