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atrosinenkoatrosinenko
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[EraVM] Refactor mapping between different input operand kinds
* Collapse OperandAddrMode and OperandAM fields of IBinary class * Use named constants instead of numbers * Drop synthetic Value field from OperandAddrModeValue class (renamed to SrcOperandMode)
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-83
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2 files changed

+43
-83
lines changed

‎llvm/lib/Target/EraVM/EraVMInstrFormats.td‎

Lines changed: 23 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -17,14 +17,12 @@
1717
// The addressing mode can be categorized into operand addressing and destination addressing
1818
// OperandAddrMode:
1919
// RR : Reg Reg; SR : Stack Reg; CR : Code Reg; IR : Imm Reg;
20-
class OperandAddrModeValue<bits<3> val> {
21-
bits<3> Value = val;
22-
}
23-
def OpndAddrNotSet : OperandAddrModeValue<0>;
24-
def OpndRR : OperandAddrModeValue<1>;
25-
def OpndIR : OperandAddrModeValue<2>;
26-
def OpndSR : OperandAddrModeValue<3>;
27-
def OpndCR : OperandAddrModeValue<4>;
20+
class SrcOperandMode;
21+
def OpndAddrNotSet : SrcOperandMode;
22+
def OpndRR : SrcOperandMode;
23+
def OpndIR : SrcOperandMode;
24+
def OpndSR : SrcOperandMode;
25+
def OpndCR : SrcOperandMode;
2826

2927
// DestAddrMode:
3028
class DestAddrModeValue<bits<3> val> {
@@ -98,38 +96,18 @@ def withInsNotSwapped : InstrMapping {
9896
class AddrModeRel; // generic map of addressing mode of operands
9997
class RetAddrModeRel; // generic map of addressing mode of results
10098

101-
102-
def mapRRInputTo : InstrMapping {
99+
class MapInputFrom<string from> : InstrMapping {
103100
let FilterClass = "AddrModeRel";
104101
let RowFields = ["BaseOpcode", "DestAddrMode", "Silent"];
105-
let ColFields = ["OperandAM"];
106-
let KeyCol = ["0"];
107-
let ValueCols = [["0"], ["1"], ["2"], ["3"]];
108-
}
109-
110-
def mapIRInputTo : InstrMapping {
111-
let FilterClass = "AddrModeRel";
112-
let RowFields = ["BaseOpcode", "DestAddrMode", "Silent"];
113-
let ColFields = ["OperandAM"];
114-
let KeyCol = ["1"];
115-
let ValueCols = [["0"], ["1"], ["2"], ["3"]];
102+
let ColFields = ["OperandAddrMode"];
103+
let KeyCol = [from];
104+
let ValueCols = [["OpndRR"], ["OpndIR"], ["OpndCR"], ["OpndSR"]];
116105
}
117106

118-
def mapCRInputTo : InstrMapping {
119-
let FilterClass = "AddrModeRel";
120-
let RowFields = ["BaseOpcode", "DestAddrMode", "Silent"];
121-
let ColFields = ["OperandAM"];
122-
let KeyCol = ["2"];
123-
let ValueCols = [["0"], ["1"], ["2"], ["3"]];
124-
}
125-
126-
def mapSRInputTo : InstrMapping {
127-
let FilterClass = "AddrModeRel";
128-
let RowFields = ["BaseOpcode", "DestAddrMode", "Silent"];
129-
let ColFields = ["OperandAM"];
130-
let KeyCol = ["3"];
131-
let ValueCols = [["0"], ["1"], ["2"], ["3"]];
132-
}
107+
def mapRRInputTo : MapInputFrom<"OpndRR">;
108+
def mapIRInputTo : MapInputFrom<"OpndIR">;
109+
def mapCRInputTo : MapInputFrom<"OpndCR">;
110+
def mapSRInputTo : MapInputFrom<"OpndSR">;
133111

134112
def withStackResult : InstrMapping {
135113
let FilterClass = "RetAddrModeRel";
@@ -345,9 +323,8 @@ class IBinary<EraVMOpcode opcode,
345323
string BaseOpcode;
346324
bit Silent = !eq(set_flags, PreserveFlags);
347325
bit ReverseOperands = !eq(swap, Swap);
348-
bits<3> OperandAddrMode = OpndAddrNotSet.Value;
326+
SrcOperandMode OperandAddrMode = OpndAddrNotSet;
349327
bits<3> DestAddrMode = DestAddrNotSet.Value;
350-
int OperandAM = 0;
351328
int ResultAM = 0;
352329

353330
let AsmString = !strconcat(opcode.Name,
@@ -404,8 +381,7 @@ class Irr_r<EraVMOpcode opcode,
404381
bits<4> rs0;
405382
bits<4> rs1;
406383

407-
let OperandAddrMode = OpndRR.Value;
408-
let OperandAM = 0;
384+
let OperandAddrMode = OpndRR;
409385

410386
let Src0 = rs0;
411387
let Src1 = rs1;
@@ -420,7 +396,6 @@ class Irr_rr<EraVMOpcode opcode,
420396
bits<4> rd1;
421397

422398
let DestAddrMode = ToRegReg.Value;
423-
let OperandAM = 0;
424399

425400
let Dst1 = rd1;
426401
}
@@ -434,8 +409,7 @@ class Iir_r<EraVMOpcode opcode,
434409
bits<4> rs1;
435410
bits<16> imm;
436411

437-
let OperandAddrMode = OpndIR.Value;
438-
let OperandAM = 1;
412+
let OperandAddrMode = OpndIR;
439413

440414
let Src1 = rs1;
441415
let Imm0 = imm;
@@ -450,7 +424,6 @@ class Iir_rr<EraVMOpcode opcode,
450424
bits<4> rd1;
451425

452426
let DestAddrMode = ToRegReg.Value;
453-
let OperandAM = 1;
454427

455428
let Dst1 = rd1;
456429
}
@@ -464,8 +437,7 @@ class Imr_r<EraVMOpcode opcode,
464437
bits<20> src0;
465438
bits<4> rs1;
466439

467-
let OperandAddrMode = OpndCR.Value;
468-
let OperandAM = 2;
440+
let OperandAddrMode = OpndCR;
469441

470442
let Src0 = src0{3-0};
471443
let Imm0 = src0{19-4};
@@ -481,8 +453,7 @@ class Isr_r<EraVMOpcode opcode,
481453
bits<20> src0;
482454
bits<4> rs1;
483455

484-
let OperandAddrMode = OpndSR.Value;
485-
let OperandAM = 3;
456+
let OperandAddrMode = OpndSR;
486457

487458
let Src0 = src0{3-0};
488459
let Src1 = rs1;
@@ -498,8 +469,6 @@ class Imr_rr<EraVMOpcode opcode,
498469
bits<4> rd1;
499470

500471
let DestAddrMode = ToRegReg.Value;
501-
let OperandAddrMode = OpndCR.Value;
502-
let OperandAM = 2;
503472

504473
let Dst1 = rd1;
505474
}
@@ -513,7 +482,6 @@ class Isr_rr<EraVMOpcode opcode,
513482
bits<4> rd1;
514483

515484
let DestAddrMode = ToRegReg.Value;
516-
let OperandAM = 3;
517485

518486
let Dst1 = rd1;
519487
}
@@ -527,8 +495,7 @@ class Irr_s<EraVMOpcode opcode,
527495
bits<4> rs0;
528496
bits<4> rs1;
529497

530-
let OperandAddrMode = OpndRR.Value;
531-
let OperandAM = 0;
498+
let OperandAddrMode = OpndRR;
532499

533500
let Src0 = rs0;
534501
let Src1 = rs1;
@@ -543,7 +510,6 @@ class Irr_sr<EraVMOpcode opcode,
543510
bits<4> rd1;
544511

545512
let DestAddrMode = ToStackReg.Value;
546-
let OperandAM = 0;
547513

548514
let Dst1 = rd1;
549515
}
@@ -557,8 +523,7 @@ class Iir_s<EraVMOpcode opcode,
557523
bits<16> imm;
558524
bits<4> rs1;
559525

560-
let OperandAddrMode = OpndIR.Value;
561-
let OperandAM = 1;
526+
let OperandAddrMode = OpndIR;
562527

563528
let Imm0 = imm;
564529
let Src1 = rs1;
@@ -573,7 +538,6 @@ class Iir_sr<EraVMOpcode opcode,
573538
bits<4> rd1;
574539

575540
let DestAddrMode = ToStackReg.Value;
576-
let OperandAM = 1;
577541

578542
let Dst1 = rd1;
579543
}
@@ -587,8 +551,7 @@ class Imr_s<EraVMOpcode opcode,
587551
bits<20> src0;
588552
bits<4> rs1;
589553

590-
let OperandAddrMode = OpndCR.Value;
591-
let OperandAM = 2;
554+
let OperandAddrMode = OpndCR;
592555

593556
let Src0 = src0{3-0};
594557
let Imm0 = src0{19-4};
@@ -604,8 +567,7 @@ class Isr_s<EraVMOpcode opcode,
604567
bits<20> src0;
605568
bits<4> rs1;
606569

607-
let OperandAddrMode = OpndSR.Value;
608-
let OperandAM = 3;
570+
let OperandAddrMode = OpndSR;
609571

610572
let Src0 = src0{3-0};
611573
let Src1 = rs1;
@@ -621,7 +583,6 @@ class Imr_sr<EraVMOpcode opcode,
621583
bits<4> rd1;
622584

623585
let DestAddrMode = ToStackReg.Value;
624-
let OperandAM = 2;
625586

626587
let Dst1 = rd1;
627588
}
@@ -635,7 +596,6 @@ class Isr_sr<EraVMOpcode opcode,
635596
bits<4> rd1;
636597

637598
let DestAddrMode = ToStackReg.Value;
638-
let OperandAM = 3;
639599

640600
let Dst1 = rd1;
641601
}

‎llvm/lib/Target/EraVM/EraVMInstrInfo.cpp‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -116,46 +116,46 @@ MachineInstr::mop_iterator ccIterator(MachineInstr &MI) {
116116

117117
int getWithRRInAddrMode(uint16_t Opcode) {
118118
Opcode = getWithInsNotSwapped(Opcode);
119-
if (int Result = mapRRInputTo(Opcode, OperandAM_0); Result != -1)
119+
if (int Result = mapRRInputTo(Opcode, OperandAddrMode_OpndRR); Result != -1)
120120
return Result;
121-
if (int Result = mapIRInputTo(Opcode, OperandAM_0); Result != -1)
121+
if (int Result = mapIRInputTo(Opcode, OperandAddrMode_OpndRR); Result != -1)
122122
return Result;
123-
if (int Result = mapCRInputTo(Opcode, OperandAM_0); Result != -1)
123+
if (int Result = mapCRInputTo(Opcode, OperandAddrMode_OpndRR); Result != -1)
124124
return Result;
125-
return mapSRInputTo(Opcode, OperandAM_0);
125+
return mapSRInputTo(Opcode, OperandAddrMode_OpndRR);
126126
}
127127

128128
int getWithIRInAddrMode(uint16_t Opcode) {
129129
Opcode = getWithInsNotSwapped(Opcode);
130-
if (int Result = mapRRInputTo(Opcode, OperandAM_1); Result != -1)
130+
if (int Result = mapRRInputTo(Opcode, OperandAddrMode_OpndIR); Result != -1)
131131
return Result;
132-
if (int Result = mapIRInputTo(Opcode, OperandAM_1); Result != -1)
132+
if (int Result = mapIRInputTo(Opcode, OperandAddrMode_OpndIR); Result != -1)
133133
return Result;
134-
if (int Result = mapCRInputTo(Opcode, OperandAM_1); Result != -1)
134+
if (int Result = mapCRInputTo(Opcode, OperandAddrMode_OpndIR); Result != -1)
135135
return Result;
136-
return mapSRInputTo(Opcode, OperandAM_1);
136+
return mapSRInputTo(Opcode, OperandAddrMode_OpndIR);
137137
}
138138

139139
int getWithCRInAddrMode(uint16_t Opcode) {
140140
Opcode = getWithInsNotSwapped(Opcode);
141-
if (int Result = mapRRInputTo(Opcode, OperandAM_2); Result != -1)
141+
if (int Result = mapRRInputTo(Opcode, OperandAddrMode_OpndCR); Result != -1)
142142
return Result;
143-
if (int Result = mapIRInputTo(Opcode, OperandAM_2); Result != -1)
143+
if (int Result = mapIRInputTo(Opcode, OperandAddrMode_OpndCR); Result != -1)
144144
return Result;
145-
if (int Result = mapCRInputTo(Opcode, OperandAM_2); Result != -1)
145+
if (int Result = mapCRInputTo(Opcode, OperandAddrMode_OpndCR); Result != -1)
146146
return Result;
147-
return mapSRInputTo(Opcode, OperandAM_2);
147+
return mapSRInputTo(Opcode, OperandAddrMode_OpndCR);
148148
}
149149

150150
int getWithSRInAddrMode(uint16_t Opcode) {
151151
Opcode = getWithInsNotSwapped(Opcode);
152-
if (int Result = mapRRInputTo(Opcode, OperandAM_3); Result != -1)
152+
if (int Result = mapRRInputTo(Opcode, OperandAddrMode_OpndSR); Result != -1)
153153
return Result;
154-
if (int Result = mapIRInputTo(Opcode, OperandAM_3); Result != -1)
154+
if (int Result = mapIRInputTo(Opcode, OperandAddrMode_OpndSR); Result != -1)
155155
return Result;
156-
if (int Result = mapCRInputTo(Opcode, OperandAM_3); Result != -1)
156+
if (int Result = mapCRInputTo(Opcode, OperandAddrMode_OpndSR); Result != -1)
157157
return Result;
158-
return mapSRInputTo(Opcode, OperandAM_3);
158+
return mapSRInputTo(Opcode, OperandAddrMode_OpndSR);
159159
}
160160

161161
int getWithRROutAddrMode(uint16_t Opcode) {
@@ -184,22 +184,22 @@ int getWithInsSwapped(uint16_t Opcode) {
184184

185185
bool hasRRInAddressingMode(unsigned Opcode) {
186186
Opcode = getWithInsNotSwapped(Opcode);
187-
return (unsigned)mapRRInputTo(Opcode, OperandAM_0) == Opcode;
187+
return (unsigned)mapRRInputTo(Opcode, OperandAddrMode_OpndRR) == Opcode;
188188
}
189189

190190
bool hasIRInAddressingMode(unsigned Opcode) {
191191
Opcode = getWithInsNotSwapped(Opcode);
192-
return (unsigned)mapIRInputTo(Opcode, OperandAM_1) == Opcode;
192+
return (unsigned)mapIRInputTo(Opcode, OperandAddrMode_OpndIR) == Opcode;
193193
}
194194

195195
bool hasCRInAddressingMode(unsigned Opcode) {
196196
Opcode = getWithInsNotSwapped(Opcode);
197-
return (unsigned)mapCRInputTo(Opcode, OperandAM_2) == Opcode;
197+
return (unsigned)mapCRInputTo(Opcode, OperandAddrMode_OpndCR) == Opcode;
198198
}
199199

200200
bool hasSRInAddressingMode(unsigned Opcode) {
201201
Opcode = getWithInsNotSwapped(Opcode);
202-
return (unsigned)mapSRInputTo(Opcode, OperandAM_3) == Opcode;
202+
return (unsigned)mapSRInputTo(Opcode, OperandAddrMode_OpndSR) == Opcode;
203203
}
204204

205205
bool hasAnyInAddressingMode(unsigned Opcode) {

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