[mlir][evm] Lower signextend builtin

Author: PavelKopyl

libsolidity/codegen/mlir/Target/EVM/YulToStandard.cpp

@@ -218,6 +218,22 @@ struct MulModOpLowering : public OpRewritePattern<yul::MulModOp> {
   }
 };
 
+struct SignExtendOpLowering : public OpRewritePattern<yul::SignExtendOp> {
+  using OpRewritePattern<yul::SignExtendOp>::OpRewritePattern;
+
+  LogicalResult matchAndRewrite(yul::SignExtendOp op,
+                                PatternRewriter &r) const override {
+    evm::Builder evmB(r, op.getLoc());
+
+    r.replaceOpWithNewOp<LLVM::IntrCallOp>(
+        op, llvm::Intrinsic::evm_signextend,
+        /*resTy=*/r.getIntegerType(256),
+        /*ins=*/ValueRange{op.getVal(), op.getOff()}, "evm.signextend");
+
+    return success();
+  }
+};
+
 struct LogOpLowering : public OpRewritePattern<yul::LogOp> {
   using OpRewritePattern<yul::LogOp>::OpRewritePattern;
 
@@ -895,6 +911,7 @@ void evm::populateYulPats(RewritePatternSet &pats) {
       ShrOpLowering,
       SarOpLowering,
       ExpOpLowering,
+      SignExtendOpLowering,
       LogOpLowering,
       AddressOpLowering,
       CallerOpLowering,

libsolidity/codegen/mlir/Yul/YulOps.td

@@ -381,6 +381,13 @@ def Yul_LogOp : Yul_Op<"log"> {
   let assemblyFormat = "$addr `,` $size oilist(`topics` `(` $topics `)` ) attr-dict";
 }
 
+def Yul_SignExtendOp : Yul_Op<"signextend", [Pure]> {
+  let summary = "Represents the `signextend` call in yul";
+  let arguments = (ins I256:$val, I256:$off);
+  let results = (outs I256:$out);
+  let assemblyFormat = "$val `,` $off attr-dict";
+}
+
 def Yul_SetImmutableOp : Yul_Op<"setimmutable"> {
   let summary = "Represents the `setimmutable` call in yul";
   let arguments = (ins I256:$addr, StrAttr:$name, I256:$val);

libsolidity/codegen/mlir/YulToMLIR.cpp

@@ -315,6 +315,7 @@ void YulToMLIRPass::populateBuiltinGenMap() {
   };
   defSimpleBuiltinGen<AddModOp>("addmod");
   defSimpleBuiltinGen<MulModOp>("mulmod");
+  defSimpleBuiltinGen<SignExtendOp>("signextend");
   defSimpleBuiltinGen<MLoadOp>("mload");
   defSimpleBuiltinGenNoRet<LoadImmutableOp>("loadimmutable");
   defSimpleBuiltinGenNoRet<MStoreOp>("mstore");

test/lit/mlirCodegen/EVM/yul/signextend.yul

@@ -0,0 +1,37 @@
+// RUN: solc --strict-assembly --mlir-action=print-std-mlir --mlir-target=evm --mmlir --mlir-print-debuginfo %s | FileCheck %s
+
+object "Test" {
+  code {
+    mstore(0, signextend(mload(0), mload(32)))
+    return(0, 32)
+  }
+}
+// NOTE: Assertions have been autogenerated by test/updFileCheckTest.py
+// CHECK: #Prague = #sol<EvmVersion Prague>
+// CHECK-NEXT: module @Test attributes {sol.evm_version = #Prague} {
+// CHECK-NEXT:   func.func @".unreachable"() attributes {llvm.linkage = #llvm.linkage<private>, passthrough = ["nofree", "null_pointer_is_valid"]} {
+// CHECK-NEXT:     llvm.unreachable loc(#loc1)
+// CHECK-NEXT:   } loc(#loc)
+// CHECK-NEXT:   func.func @__entry() attributes {llvm.linkage = #llvm.linkage<external>, passthrough = ["nofree", "null_pointer_is_valid"]} {
+// CHECK-NEXT:     %c32_i256 = arith.constant 32 : i256 loc(#loc)
+// CHECK-NEXT:     %c0_i256 = arith.constant 0 : i256 loc(#loc)
+// CHECK-NEXT:     %0 = llvm.inttoptr %c0_i256 : i256 to !llvm.ptr<1> loc(#loc2)
+// CHECK-NEXT:     %1 = llvm.load %0 {alignment = 1 : i64} : !llvm.ptr<1> -> i256 loc(#loc2)
+// CHECK-NEXT:     %2 = llvm.inttoptr %c32_i256 : i256 to !llvm.ptr<1> loc(#loc3)
+// CHECK-NEXT:     %3 = llvm.load %2 {alignment = 1 : i64} : !llvm.ptr<1> -> i256 loc(#loc3)
+// CHECK-NEXT:     %4 = "llvm.intrcall"(%1, %3) <{id = 3745 : i32, name = "evm.signextend"}> : (i256, i256) -> i256 loc(#loc4)
+// CHECK-NEXT:     %5 = llvm.inttoptr %c0_i256 : i256 to !llvm.ptr<1> loc(#loc5)
+// CHECK-NEXT:     llvm.store %4, %5 {alignment = 1 : i64} : i256, !llvm.ptr<1> loc(#loc5)
+// CHECK-NEXT:     %6 = llvm.inttoptr %c0_i256 : i256 to !llvm.ptr<1> loc(#loc1)
+// CHECK-NEXT:     "llvm.intrcall"(%6, %c32_i256) <{id = 3735 : i32, name = "evm.return"}> : (!llvm.ptr<1>, i256) -> () loc(#loc1)
+// CHECK-NEXT:     call @".unreachable"() : () -> () loc(#loc1)
+// CHECK-NEXT:     llvm.unreachable loc(#loc)
+// CHECK-NEXT:   } loc(#loc)
+// CHECK-NEXT: } loc(#loc)
+// CHECK-NEXT: #loc = loc(unknown)
+// CHECK-NEXT: #loc1 = loc({{.*}}:5:4)
+// CHECK-NEXT: #loc2 = loc({{.*}}:4:25)
+// CHECK-NEXT: #loc3 = loc({{.*}}:4:35)
+// CHECK-NEXT: #loc4 = loc({{.*}}:4:14)
+// CHECK-NEXT: #loc5 = loc({{.*}}:4:4)
+// CHECK-EMPTY:

test/lit/mlirCodegen/yul/signextend.yul

@@ -0,0 +1,29 @@
+// RUN: solc --strict-assembly --mlir-action=print-init --mmlir --mlir-print-debuginfo %s | FileCheck %s
+
+object "Test" {
+  code {
+    mstore(0, signextend(mload(0), mload(32)))
+  }
+}
+// NOTE: Assertions have been autogenerated by test/updFileCheckTest.py
+// CHECK: #Prague = #sol<EvmVersion Prague>
+// CHECK-NEXT: module attributes {sol.evm_version = #Prague} {
+// CHECK-NEXT:   yul.object @Test {
+// CHECK-NEXT:     %c0_i256 = arith.constant 0 : i256 loc(#loc1)
+// CHECK-NEXT:     %c0_i256_0 = arith.constant 0 : i256 loc(#loc2)
+// CHECK-NEXT:     %0 = yul.mload %c0_i256_0 loc(#loc3)
+// CHECK-NEXT:     %c32_i256 = arith.constant 32 : i256 loc(#loc4)
+// CHECK-NEXT:     %1 = yul.mload %c32_i256 loc(#loc5)
+// CHECK-NEXT:     %2 = yul.signextend %0, %1 loc(#loc6)
+// CHECK-NEXT:     yul.mstore %c0_i256, %2 loc(#loc7)
+// CHECK-NEXT:   } loc(#loc)
+// CHECK-NEXT: } loc(#loc)
+// CHECK-NEXT: #loc = loc(unknown)
+// CHECK-NEXT: #loc1 = loc({{.*}}:4:11)
+// CHECK-NEXT: #loc2 = loc({{.*}}:4:31)
+// CHECK-NEXT: #loc3 = loc({{.*}}:4:25)
+// CHECK-NEXT: #loc4 = loc({{.*}}:4:41)
+// CHECK-NEXT: #loc5 = loc({{.*}}:4:35)
+// CHECK-NEXT: #loc6 = loc({{.*}}:4:14)
+// CHECK-NEXT: #loc7 = loc({{.*}}:4:4)
+// CHECK-EMPTY: