add replace tests (#21)

Author: matth2k

.github/workflows/rust.yml

@@ -53,11 +53,11 @@ jobs:
       - name: Generate code coverage
         run: cargo llvm-cov --features default --workspace --json > coverage.json
       - name: Coverage (60% by line)
-        run: python3 utils/code_coverage.py -p 60.0 --whitelist util.rs coverage.json >> $GITHUB_STEP_SUMMARY
+        run: python3 utils/code_coverage.py -p 60.0 coverage.json --whitelist util.rs >> $GITHUB_STEP_SUMMARY
       - name: Coverage (80% by line)
-        run: python3 utils/code_coverage.py -p 80.0 --whitelist util.rs coverage.json >> $GITHUB_STEP_SUMMARY
+        run: python3 utils/code_coverage.py -p 80.0 coverage.json --whitelist util.rs >> $GITHUB_STEP_SUMMARY
       - name: Coverage (90% by line)
-        run: python3 utils/code_coverage.py -p 90.0 --whitelist util.rs coverage.json >> $GITHUB_STEP_SUMMARY
+        run: python3 utils/code_coverage.py -p 90.0 coverage.json --whitelist util.rs >> $GITHUB_STEP_SUMMARY
 
   mdformat:
     name: Markdown format

tests/edits.rs

@@ -1,3 +1,4 @@
+use safety_net::assert_verilog_eq;
 use safety_net::netlist::Gate;
 use safety_net::netlist::GateNetlist;
 use safety_net::netlist::Netlist;
@@ -38,3 +39,85 @@ fn test_clean() {
     assert_eq!(netlist.objects().count(), 3);
     assert!(!netlist.clean().unwrap());
 }
+
+#[test]
+fn test_replace() {
+    let netlist = get_simple_example();
+    let input = netlist.inputs().next().unwrap();
+    let inverter = Gate::new_logical("INV".into(), vec!["I".into()], "O".into());
+    let inverted = netlist
+        .insert_gate(inverter, "inst_0".into(), &[input.clone()])
+        .unwrap();
+    assert!(netlist.replace_net_uses(input.unwrap(), &inverted).is_ok());
+    assert_verilog_eq!(
+        netlist.to_string(),
+        "module example (
+           a,
+           b,
+           y
+         );
+           input a;
+           wire a;
+           input b;
+           wire b;
+           output y;
+           wire y;
+           wire inst_0_Y;
+           wire inst_0_O;
+           AND inst_0 (
+             .A(inst_0_O),
+             .B(b),
+             .Y(inst_0_Y)
+           );
+           INV inst_0 (
+             .I(inst_0_O),
+             .O(inst_0_O)
+           );
+           assign y = inst_0_Y;
+         endmodule\n"
+    );
+}
+
+#[test]
+fn test_replace2() {
+    let netlist = get_simple_example();
+    let input = netlist.inputs().next().unwrap();
+    let inverter = Gate::new_logical("INV".into(), vec!["I".into()], "O".into());
+    let inverted = netlist
+        .insert_gate_disconnected(inverter, "inst_0".into())
+        .unwrap();
+    // This errors, because input is not safe to delete. No replace is done.
+    assert!(
+        netlist
+            .replace_net_uses(input.clone().unwrap(), &inverted)
+            .is_err()
+    );
+    inverted.find_input(&"I".into()).unwrap().connect(input);
+    assert_verilog_eq!(
+        netlist.to_string(),
+        "module example (
+           a,
+           b,
+           y
+         );
+           input a;
+           wire a;
+           input b;
+           wire b;
+           output y;
+           wire y;
+           wire inst_0_Y;
+           wire inst_0_O;
+           AND inst_0 (
+             .A(a),
+             .B(b),
+             .Y(inst_0_Y)
+           );
+           INV inst_0 (
+             .I(a),
+             .O(inst_0_O)
+           );
+           assign y = inst_0_Y;
+         endmodule\n"
+    );
+}