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27 | 27 |
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28 | 28 | /// A table that maps nets to the circuit nodes they drive |
29 | 29 | pub struct FanOutTable<'a, I: Instantiable> { |
30 | | - // A reference to the underlying netlist |
| 30 | + /// A reference to the underlying netlist |
31 | 31 | _netlist: &'a Netlist<I>, |
32 | | - // Maps a net to the list of nodes it drives |
| 32 | + /// Maps a net to the list of nodes it drives |
33 | 33 | net_fan_out: HashMap<Net, Vec<NetRef<I>>>, |
34 | 34 | /// Maps a node to the list of nodes it drives |
35 | 35 | node_fan_out: HashMap<NetRef<I>, Vec<NetRef<I>>>, |
@@ -114,9 +114,9 @@ where |
114 | 114 | /// An simple example to analyze the logic levels of a netlist. |
115 | 115 | /// This analysis checks for cycles, but it doesn't check for registers. |
116 | 116 | pub struct SimpleCombDepth<'a, I: Instantiable> { |
117 | | - // A reference to the underlying netlist |
| 117 | + /// A reference to the underlying netlist |
118 | 118 | _netlist: &'a Netlist<I>, |
119 | | - // Maps a net to its logic level as a DAG |
| 119 | + /// Maps a net to its logic level as a DAG |
120 | 120 | comb_depth: HashMap<NetRef<I>, usize>, |
121 | 121 | /// The maximum depth of the circuit |
122 | 122 | max_depth: usize, |
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