Verilog wrong on sr flop?

[mattvenn]

wokwi-verilog-gds-test/src/cells.v

Line 77 in 17f106d

module dffsr_cell (

From Jeremy:

Btw the verilog model of the dffsr_cell is wrong - it implies S and R only have effect on their rising edges where in fact they have level sensitive effects ie if S is high it holds the output at 1 irrespective of the clock and data - and the S and R both being high should give an X output (undefined) - I think