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Fix STM32H5 init
1 parent d8f87f9 commit 07b9569

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2 files changed

+10
-5
lines changed

2 files changed

+10
-5
lines changed

connectivity/drivers/emac/TARGET_STM/STM32EthMACv2.cpp

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -249,14 +249,19 @@ namespace mbed {
249249
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
250250
EthInitPinmappings();
251251

252+
253+
#ifdef TARGET_STM32H7
252254
// Use RMII
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HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
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255257
/* Dummy read to sync with ETH */
256-
#ifdef TARGET_STM32H5
257-
(void)SBS->PMCR;
258-
#else
259258
(void)SYSCFG->PMCR;
259+
#else
260+
__HAL_RCC_SBS_CLK_ENABLE();
261+
HAL_SBS_ETHInterfaceSelect(SBS_ETH_RMII);
262+
263+
/* Dummy read to sync with ETH */
264+
(void)SBS->PMCR;
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#endif
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262267
/* Ethernet Software reset */

connectivity/drivers/emac/include/GenericEthDMA.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -310,12 +310,12 @@ namespace mbed {
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size_t rxDescsOwnedByApplication; ///< Number of Rx descriptors owned by the application and needing buffers allocated.
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std::atomic<size_t> rxNextIndex; ///< Index of the next descriptor that the DMA will populate. Updated by application but used by ISR.
312312

313-
// Alignment required for Rx memory buffers. Normally they don't need alignment but
313+
// Alignment required for Rx memory buffers. Normally they don't need more than word alignment but
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// if we are doing cache operations they need to be cache aligned.
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#if __DCACHE_PRESENT
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static constexpr size_t RX_BUFFER_ALIGN = __SCB_DCACHE_LINE_SIZE;
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#else
318-
static constexpr size_t RX_BUFFER_ALIGN = 2;
318+
static constexpr size_t RX_BUFFER_ALIGN = sizeof(uint32_t);
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#endif
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321321
/// Payload size of buffers allocated from the Rx pool. This is the allocation unit size

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