Implement 120MHz clocking

Author: multiplemonomials

targets/TARGET_NXP/TARGET_LPC17XX/device/system_LPC17xx.c

@@ -25,6 +25,7 @@
 
 #include <stdint.h>
 #include "LPC17xx.h"
+#include "mbed-target-config.h"
 
 
 /** @addtogroup LPC17xx_System
@@ -297,20 +298,28 @@
 #define CLKSRCSEL_Val         0x00000001
 #define PLL0_SETUP            1
 
-#ifdef MCB1700
-#    define PLL0CFG_Val           0x00050063
-#    define PLL1_SETUP            1
-#    define PLL1CFG_Val           0x00000023
-#    define CCLKCFG_Val           0x00000003
-#    define USBCLKCFG_Val         0x00000000
+// If in 120MHz mode, clock the PLL at 480MHz as this is the only frequency that can give us both 120MHz for the core
+// and 48MHz for USB.
+#ifdef MBED_CONF_TARGET_LPC17XX_CORE_CLK_120MHZ
+     // Multiplier for PLL0. Example: if MBED_CONF_TARGET_LPC17XX_XTAL_FREQ is 6MHz, this will be 40
+#    define PLL0_MULTIPLIER       (240000000/MBED_CONF_TARGET_LPC17XX_XTAL_FREQ)
+#    define PLL0CFG_Val           (PLL0_MULTIPLIER-1) // PLL0 clock = <input clock> * <PLL0 multiplier> * 2 / 1 = 480MHz
+#    define CCLKCFG_Val           0x00000003 // CPU clock = PLL0 clock / 4 = 120MHz
+
+#    define USBCLKCFG_Val         0x00000009 // USB clock = PLL0 clock / 10 = 48MHz
 #else
-#    define PLL0CFG_Val           0x0000000B
-#    define PLL1_SETUP            0
-#    define PLL1CFG_Val           0x00000000
-#    define CCLKCFG_Val           0x00000002
-#    define USBCLKCFG_Val         0x00000005
+     // Multiplier for PLL0. Example: if MBED_CONF_TARGET_LPC17XX_XTAL_FREQ is 6MHz, this will be 24
+#    define PLL0_MULTIPLIER       (144000000/MBED_CONF_TARGET_LPC17XX_XTAL_FREQ)
+#    define PLL0CFG_Val           (PLL0_MULTIPLIER-1) // PLL0 clock = <input clock> * <PLL0 multiplier> * 2 / 1 = 288MHz
+#    define CCLKCFG_Val           0x00000002 // CPU clock = PLL0 clock / 3 = 96MHz
+
+#    define USBCLKCFG_Val         0x00000005 // USB clock = PLL0 clock / 6 = 48MHz
 #endif
 
+// Don't enable PLL1. It is much more limited in input frequency and only acceps 10-24MHz.
+#define PLL1_SETUP            0
+#define PLL1CFG_Val           0x00000000
+
 #define PCLKSEL0_Val          0x00000000
 #define PCLKSEL1_Val          0x00000000
 #define PCONP_Val             0x042887DE
@@ -402,8 +411,7 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define XTAL        (12000000UL)        /* Oscillator frequency               */
-#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
+#define OSC_CLK     MBED_CONF_TARGET_LPC17XX_XTAL_FREQ        /* Main oscillator frequency          */
 #define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */
 #define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
 

targets/targets.json5

@@ -456,6 +456,14 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
             "us-ticker-timer": {
                 "help": "Chooses which timer (0-3) to use for us_ticker.c",
                 "value": 3
+            },
+            "lpc17xx-xtal-freq": {
+                help: "Frequency of external crystal or clock source connected to the XTAL pins. Frequency in MHz must be an integer factor of 24 (e.g. 12MHz, 6MHz, and 1MHz are OK but 5MHz is not).",
+                value: 12000000
+            },
+            "lpc17xx-core-clk-120mhz": {
+                help: "If true, the core will be clocked at 120MHz. Otherwise, it will be clocked at 96MHz. This is only officially supported with LPC1759/69 chips, but can work with others as an overclock.",
+                value: false
             }
         },
         "overrides": {
@@ -494,7 +502,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
         },
         "image_url": "https://os.mbed.com/media/cache/platforms/LPC1768.jpg.250x250_q85.jpg"
     },
-    "LPCXPRESSO_LPC1769": {
+    "LPCXPRESSO_LPC1769": { // AKA LPCXpresso LPC1769. CMSIS-DAP version (OM13085UL) should also work.
         "inherits": [
             "MCU_LPC17XX"
         ],
@@ -504,7 +512,8 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
             "LOCALFILESYSTEM"
         ],
         "overrides": {
-            "default-adc-vref": 3.3 // Vref is 3.3V
+            "default-adc-vref": 3.3, // Vref is 3.3V
+            "lpc17xx-core-clk-120mhz": true
         },
         "image_url": "https://www.embeddedartists.com/wp-content/uploads/2018/06/lpc1769_xpr_540x333-540x333.png"
     },

targets/upload_method_cfg/LPC1768.cmake

@@ -37,8 +37,7 @@ set(OPENOCD_UPLOAD_ENABLED TRUE)
 set(OPENOCD_CHIP_CONFIG_COMMANDS
     -f ${CMAKE_CURRENT_LIST_DIR}/openocd_cfgs/lpc1768.cfg)
 
-# For some reason, as of summer 2024, git version of OpenOCD does not work with LPC1768.  So, it seems like
-# the last compatible version will be the current release 0.12.
+# Due to the new quirks mode, as of summer 2024, git version of OpenOCD does not work with LPC1768.
 set(OPENOCD_VERSION_RANGE 0.10...<0.13)
 
 # Config options for LINKSERVER

targets/upload_method_cfg/LPCXPRESSO_LPC1769.cmake

@@ -37,8 +37,7 @@ set(OPENOCD_UPLOAD_ENABLED TRUE)
 set(OPENOCD_CHIP_CONFIG_COMMANDS
     -f ${CMAKE_CURRENT_LIST_DIR}/openocd_cfgs/lpc1768.cfg)
 
-# For some reason, as of summer 2024, git version of OpenOCD does not work with LPC1768.  So, it seems like
-# the last compatible version will be the current release 0.12.
+# Due to the new quirks mode, as of summer 2024, git version of OpenOCD does not work with LPC1768.
 set(OPENOCD_VERSION_RANGE 0.10...<0.13)
 
 # Config options for LINKSERVER