DMA SPI support for STM32 devices (#162)

* Start on STM32 DMA SPI

* Update all objects.hs, add interrupt function

* Initial DMA code should be ready to test out...

* Fix SPI interrupt-mode IRQ handlers, add SPI::transfer_and_wait

* Fix CMake error when building for STM32WL processors

* Now builds on all STM devices!

* Properly support STM32U5 / DMA IP v3

* Start on STM32F4 support, fix hardfault on IP v1 and v3 due to incorrect indexing

* Fix Rx-only transfers, add abort code, fix incorrect channel assignments for DMA IP v1 devices

* Start on STM32H7 SPI DMA

* Fixes for H7: Correctly manage data cache, keep SPI ISR enabled

* Implement DMA SPI header constants for all remaining STM32 families.  Also add support for freeing DMA channels

* Try and fix build on STM32G0

* Fix build on STM32G0

* Add SPI_32BIT_WORDS label, start on fixing SPI docs

* SPI: Implement reference counting so that DMA channels get freed properly

* Fix issue where SPI data could get corrupted (by TI mode turning on) depending on memory layout (if your spis pointer & 0x10 was nonzero)

* Mark DMA channels as unallocated when SPI bus is freed

* Simplify spi_abort_asynch()

* Fix some rebase issues, fix failing to allocate DMA channel on STM32U5

* Fix DMA getting stuck on STM32F4, F7, and F2

Author: Jamie Smith

drivers/source/I2C.cpp

@@ -245,7 +245,7 @@ void I2C::abort_transfer(void)
 I2C::Result I2C::transfer_and_wait(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, rtos::Kernel::Clock::duration_u32 timeout, bool repeated)
 {
     // Use EventFlags to suspend the thread until the transfer finishes
-    rtos::EventFlags transferResultFlags("I2C::Result EvFlags");
+    rtos::EventFlags transferResultFlags("I2C::transfer_and_wait EvFlags");
 
     // Simple callback from the transfer that sets the EventFlags using the I2C result event
     event_callback_t transferCallback([&](int event) {

hal/include/hal/spi_api.h

@@ -261,6 +261,9 @@ int  spi_master_write(spi_t *obj, int value);
  *  tx_length and rx_length. The bytes written will be padded with the
  *  value 0xff.
  *
+ * Note: Even if the word size / bits per frame is not 8, \c rx_length and \c tx_length
+ * still give lengths in bytes of input data, not numbers of words.
+ *
  * @param[in] obj        The SPI peripheral to use for sending
  * @param[in] tx_buffer  Pointer to the byte-array of data to write to the device
  * @param[in] tx_length  Number of bytes to write, may be zero

targets/TARGET_STM/CMakeLists.txt

@@ -52,6 +52,7 @@ target_sources(mbed-stm
         trng_api.c
         us_ticker.c
         watchdog_api.c
+		stm_dma_utils.c
 )
 
 target_link_libraries(mbed-stm INTERFACE mbed-cmsis-cortex-m)

targets/TARGET_STM/TARGET_STM32F0/objects.h

@@ -44,20 +44,6 @@ struct pwmout_s {
     uint8_t inverted;
 };
 
-struct spi_s {
-    SPI_HandleTypeDef handle;
-    IRQn_Type spiIRQ;
-    SPIName spi;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-#if DEVICE_SPI_ASYNCH
-    uint32_t event;
-    uint8_t transfer_type;
-#endif
-};
-
 struct serial_s {
     UARTName uart;
     int index; // Used by irq

targets/TARGET_STM/TARGET_STM32F0/spi_device.h

@@ -21,4 +21,7 @@
 // Defines the word length capability of the device where Nth bit allows for N window size
 #define STM32_SPI_CAPABILITY_WORD_LENGTH (0x0000FFF8)
 
+// We have DMA support
+#define STM32_SPI_CAPABILITY_DMA 1
+
 #endif

targets/TARGET_STM/TARGET_STM32F0/stm_dma_info.h

@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016-2023 STMicroelectronics
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OS_STM_DMA_INFO_H
+#define MBED_OS_STM_DMA_INFO_H
+
+#include "cmsis.h"
+#include "stm_dma_utils.h"
+
+// See STM32F0 reference manual Table 26.
+
+/// Mapping from SPI index to DMA link info for Tx
+static const DMALinkInfo SPITxDMALinks[] = {
+        {1, 3}, // SPI1 Tx is DMA1 Channel 3
+        {1, 5}, // SPI2 Tx is DMA1 Channel 5
+};
+
+/// Mapping from SPI index to DMA link info for Rx
+static const DMALinkInfo SPIRxDMALinks[] = {
+        {1, 2}, // SPI1 Rx is DMA1 Channel 2
+        {1, 4}, // SPI2 Rx is DMA1 Channel 4
+};
+
+#endif //MBED_OS_STM_DMA_INFO_H

targets/TARGET_STM/TARGET_STM32F1/objects.h

@@ -89,20 +89,6 @@ struct serial_s {
 #endif
 };
 
-struct spi_s {
-    SPI_HandleTypeDef handle;
-    IRQn_Type spiIRQ;
-    SPIName spi;
-    PinName pin_miso;
-    PinName pin_mosi;
-    PinName pin_sclk;
-    PinName pin_ssel;
-#if DEVICE_SPI_ASYNCH
-    uint32_t event;
-    uint8_t transfer_type;
-#endif
-};
-
 struct i2c_s {
     /*  The 1st 2 members I2CName i2c
      *  and I2C_HandleTypeDef handle should

targets/TARGET_STM/TARGET_STM32F1/spi_device.h

@@ -35,4 +35,7 @@
 // Defines the word length capability of the device where Nth bit allows for N window size
 #define STM32_SPI_CAPABILITY_WORD_LENGTH (0x00008080)
 
+// We have DMA support
+#define STM32_SPI_CAPABILITY_DMA 1
+
 #endif

targets/TARGET_STM/TARGET_STM32F1/stm_dma_info.h

@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016-2023 STMicroelectronics
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_OS_STM_DMA_INFO_H
+#define MBED_OS_STM_DMA_INFO_H
+
+#include "cmsis.h"
+#include "stm_dma_utils.h"
+
+// See STM32F1 reference manual Tables 78 and 79.
+
+/// Mapping from SPI index to DMA link info for Tx
+static const DMALinkInfo SPITxDMALinks[] = {
+        {1, 3}, // SPI1 Tx is DMA1 Channel 3
+        {1, 5}, // SPI2 Tx is DMA1 Channel 5
+        {2, 2}, // SPI3 Tx is DMA2 Channel 2
+};
+
+/// Mapping from SPI index to DMA link info for Rx
+static const DMALinkInfo SPIRxDMALinks[] = {
+        {1, 2}, // SPI1 Rx is DMA1 Channel 2
+        {1, 4}, // SPI2 Rx is DMA1 Channel 4
+        {2, 1}, // SPI3 Rx is DMA2 Channel 1
+};
+
+#endif //MBED_OS_STM_DMA_INFO_H

targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/STM32F2xx_HAL_Driver/stm32f2xx_hal_dma_ex.c

@@ -202,7 +202,18 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_
 
     /* Enable Common interrupts*/
     hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
-    hdma->Instance->FCR |= DMA_IT_FE;
+
+    /* Mbed CE mod: Only enable the FIFO Error interrupt if the FIFO is actually enabled.
+     * If it's not enabled, then this interrupt can trigger spuriously from memory bus
+     * stalls that the DMA engine encounters, and this creates random DMA failures.
+     * Reference forum thread here:
+     * https://community.st.com/t5/stm32-mcus-products/spi-dma-fifo-error-issue-feifx/td-p/537074
+     * also: https://community.st.com/t5/stm32-mcus-touch-gfx-and-gui/spi-dma-error-is-occurred-when-the-other-dma-memory-to-memory-is/td-p/191590
+     */
+    if(hdma->Instance->FCR & DMA_SxFCR_DMDIS)
+    {
+      hdma->Instance->FCR |= DMA_IT_FE;
+    }
 
     if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
     {