fix wrong received message length for L5,G0,G4 serieses

enable MSIPLL auto calibration for L5,U5 serieses
adjusted PLL1Q clock for H5, H7 series to enable CAN FD a data rate of 5 MBit/s

Author: wdx04

targets/TARGET_STM/TARGET_STM32H5/clock_cfg/system_clock.c

@@ -125,8 +125,9 @@ else // Divisible by 5MHz
     RCC_OscInitStruct.PLL.PLLP = 2;
     // Most of the SPI busses are clocked off of PLL1Q, and the max usable frequency for SPI is about
     // ~50MHz.  Plus, SPI has only limited, power-of-2 prescaler options so a high input clock really hurts
-    // its clock resolution.  So, give it a much lower input clock.
-    RCC_OscInitStruct.PLL.PLLQ = 10; // output freq = 50MHz
+    // its clock resolution.  So, give it a lower input clock.
+    // Note PLL1Q is also used by the CAN FD, 100MHz is needed to support a data rate of 5Mbit/s.
+    RCC_OscInitStruct.PLL.PLLQ = 5; // output freq = 100MHz
     RCC_OscInitStruct.PLL.PLLR = 2;
     RCC_OscInitStruct.PLL.PLLFRACN = 0;
     RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
@@ -194,8 +195,8 @@ uint8_t SetSysClock_PLL_HSI(void)
     RCC_OscInitStruct.PLL.PLLP = 2;
     // Most of the SPI busses are clocked off of PLL1Q, and the max usable frequency for SPI is about
     // ~50MHz.  Plus, SPI has only limited, power-of-2 prescaler options so a high input clock really hurts
-    // its clock resolution.  So, give it a much lower input clock.
-    RCC_OscInitStruct.PLL.PLLQ = 10; // output freq = 50MHz
+    // its clock resolution.  So, give it a lower input clock.
+    RCC_OscInitStruct.PLL.PLLQ = 5; // output freq = 100MHz
     RCC_OscInitStruct.PLL.PLLR = 2;
     RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_3;
     RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;

targets/TARGET_STM/TARGET_STM32H7/clock_cfg/TARGET_STM32H7_280MHZ/system_clock.c

@@ -27,12 +27,12 @@
   * It is used for all STM32H7 family microcontrollers with a top speed of 280MHz.
   * The input clock from the external oscillator may be any frequency evenly divisible by
   * 5MHz or 2MHz, and must be between 4MHz and 50MHz.
-  * 
+  *
   * Note that 280MHz is the "overdrive" mode and is basically an overclock.  It is only supported
   * under certain conditions (LDO in use) and cannot be used over the full temperature range.
   * For industrial applications it is recommended to disable overdrive.  Overdrive can be enabled/
   * disabled via the "target.enable-overdrive-mode" option in mbed_app.json.
-  * 
+  *
 **/
 
 #include "stm32h7xx.h"
@@ -160,9 +160,9 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     RCC_OscInitStruct.PLL.PLLP = 2;   // PLLCLK = SYSCLK = 280/225 MHz
 
 #if MBED_CONF_TARGET_ENABLE_OVERDRIVE_MODE
-    RCC_OscInitStruct.PLL.PLLQ = 56;  // PLL1Q used for FDCAN = 10 MHz
+    RCC_OscInitStruct.PLL.PLLQ = 7;  // PLL1Q used for FDCAN = 80 MHz
 #else
-    RCC_OscInitStruct.PLL.PLLQ = 45;  // PLL1Q used for FDCAN = 10 MHz
+    RCC_OscInitStruct.PLL.PLLQ = 5;  // PLL1Q used for FDCAN = 90 MHz
 #endif
 
     RCC_OscInitStruct.PLL.PLLR = 2;
@@ -234,11 +234,11 @@ uint8_t SetSysClock_PLL_HSI(void)
     RCC_OscInitStruct.PLL.PLLP = 2;   // PLLCLK = SYSCLK = 280/225 MHz
 
 #if MBED_CONF_TARGET_ENABLE_OVERDRIVE_MODE
-    RCC_OscInitStruct.PLL.PLLQ = 56;  // PLL1Q used for FDCAN = 10 MHz
+    RCC_OscInitStruct.PLL.PLLQ = 7;  // PLL1Q used for FDCAN = 80 MHz
 #else
-    RCC_OscInitStruct.PLL.PLLQ = 45;  // PLL1Q used for FDCAN = 10 MHz
+    RCC_OscInitStruct.PLL.PLLQ = 5;  // PLL1Q used for FDCAN = 90 MHz
 #endif
-    
+
     RCC_OscInitStruct.PLL.PLLR = 2;
     RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; // PLL1 VCO clock is between 128 and 560 MHz
     RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; // PLL1 input clock is between 2 and 4 MHz

targets/TARGET_STM/TARGET_STM32H7/clock_cfg/TARGET_STM32H7_480MHZ/system_clock.c

@@ -32,12 +32,12 @@
   * It is used for all STM32H7 family microcontrollers with a top speed of 480MHz.
   * The input clock from the external oscillator may be any frequency evenly divisible by
   * 5MHz or 2MHz, and must be between 4MHz and 50MHz.
-  * 
+  *
   * Note that 480MHz is the "overdrive" mode and is basically an overclock.  It is only supported
   * under certain conditions (LDO in use) and cannot be used over the full temperature range.
   * For industrial applications it is recommended to disable overdrive. Overdrive can be enabled/
   * disabled via the "target.enable-overdrive-mode" option in mbed_app.json.
-  * 
+  *
 **/
 
 #include "stm32h7xx.h"
@@ -171,9 +171,9 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     RCC_OscInitStruct.PLL.PLLP = 2;   // PLLCLK = SYSCLK = 480/400 MHz
 
 #if MBED_CONF_TARGET_ENABLE_OVERDRIVE_MODE
-    RCC_OscInitStruct.PLL.PLLQ = 96;  // PLL1Q used for FDCAN = 10 MHz
+    RCC_OscInitStruct.PLL.PLLQ = 12;  // PLL1Q used for FDCAN = 80 MHz
 #else
-    RCC_OscInitStruct.PLL.PLLQ = 80;  // PLL1Q used for FDCAN = 10 MHz
+    RCC_OscInitStruct.PLL.PLLQ = 10;  // PLL1Q used for FDCAN = 80 MHz
 #endif
 
     RCC_OscInitStruct.PLL.PLLR = 2;
@@ -251,11 +251,11 @@ uint8_t SetSysClock_PLL_HSI(void)
 #endif
 
     RCC_OscInitStruct.PLL.PLLP = 2;    // 480/400 MHz
-    
+
 #if MBED_CONF_TARGET_ENABLE_OVERDRIVE_MODE
-    RCC_OscInitStruct.PLL.PLLQ = 96;  // PLL1Q used for FDCAN = 10 MHz
+    RCC_OscInitStruct.PLL.PLLQ = 12;  // PLL1Q used for FDCAN = 80 MHz
 #else
-    RCC_OscInitStruct.PLL.PLLQ = 80;  // PLL1Q used for FDCAN = 10 MHz
+    RCC_OscInitStruct.PLL.PLLQ = 10;  // PLL1Q used for FDCAN = 80 MHz
 #endif
 
     RCC_OscInitStruct.PLL.PLLR = 2;
@@ -278,7 +278,7 @@ uint8_t SetSysClock_PLL_HSI(void)
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY) != HAL_OK) {
         return 0; // FAIL
     }
-    
+
     return 1; // OK
 }
 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

targets/TARGET_STM/TARGET_STM32H7/clock_cfg/TARGET_STM32H7_550MHZ/system_clock.c

@@ -32,12 +32,12 @@
   * It is used for all STM32H7 family microcontrollers with a top speed of 550MHz.
   * The input clock from the external oscillator may be any frequency evenly divisible by
   * 5MHz or 2MHz, and must be between 4MHz and 50MHz.
-  * 
+  *
   * Note that 550MHz is the "overdrive" mode and is basically an overclock.  It is only supported
   * under certain conditions (LDO in use) and cannot be used over the full temperature range.
   * For industrial applications it is recommended to disable overdrive. Overdrive can be enabled/
   * disabled via the "target.enable-overdrive-mode" option in mbed_app.json.
-  * 
+  *
 **/
 
 #include "stm32h7xx.h"
@@ -167,10 +167,10 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 
 #if MBED_CONF_TARGET_ENABLE_OVERDRIVE_MODE
     RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; // PLL1 VCO clock is between 192 and 836 MHz
-    RCC_OscInitStruct.PLL.PLLQ = 55;  // PLL1Q used for FDCAN = 10 MHz
+    RCC_OscInitStruct.PLL.PLLQ = 5;  // PLL1Q used for FDCAN = 110 MHz
 #else
     RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; // PLL1 VCO clock is between 150 and 420 MHz
-    RCC_OscInitStruct.PLL.PLLQ = 40;  // PLL1Q used for FDCAN = 10 MHz
+    RCC_OscInitStruct.PLL.PLLQ = 5;  // PLL1Q used for FDCAN = 80 MHz
 #endif
 
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
@@ -244,15 +244,15 @@ uint8_t SetSysClock_PLL_HSI(void)
 
 #if MBED_CONF_TARGET_ENABLE_OVERDRIVE_MODE
     RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; // PLL1 VCO clock is between 192 and 836 MHz
-    RCC_OscInitStruct.PLL.PLLQ = 55;  // PLL1Q used for FDCAN = 10 MHz
+    RCC_OscInitStruct.PLL.PLLQ = 5;  // PLL1Q used for FDCAN = 110 MHz
 #else
     RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; // PLL1 VCO clock is between 150 and 420 MHz
-    RCC_OscInitStruct.PLL.PLLQ = 40;  // PLL1Q used for FDCAN = 10 MHz
+    RCC_OscInitStruct.PLL.PLLQ = 5;  // PLL1Q used for FDCAN = 80 MHz
 #endif
 
     RCC_OscInitStruct.PLL.PLLR = 2;    // 275 MHz
     RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; // PLL1 input clock is between 2 and 4 MHz
-    
+
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
         return 0; // FAIL
     }

targets/TARGET_STM/TARGET_STM32L5/system_clock.c

@@ -121,7 +121,7 @@ uint8_t SetSysClock_PLL_MSI(void)
 {
     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-    
+
     /* Configure LSE Drive Capability */
     __HAL_RCC_PWR_CLK_ENABLE();
     __HAL_RCC_SYSCFG_CLK_ENABLE();
@@ -192,6 +192,9 @@ uint8_t SetSysClock_PLL_MSI(void)
     }
 #endif
 
+    /* Enable MSI Auto calibration */
+    HAL_RCCEx_EnableMSIPLLMode();
+
     return 1; // OK
 }
 #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U545xE/system_clock.c

@@ -218,6 +218,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
      */
     HAL_RCCEx_EnableMSIPLLModeSelection(RCC_MSIKPLL_MODE_SEL);
     HAL_RCCEx_EnableMSIPLLMode();
+    HAL_RCCEx_EnableMSIPLLFastStartup();
 
     return 1; // OK
 }

targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/system_clock.c

@@ -98,7 +98,7 @@ MBED_WEAK void SetSysClock(void)
 
 // Output clock on MCO pin(PA8) for debugging purpose
 #if DEBUG_MCO == 1
-    HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 160 MHz 
+    HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 160 MHz
 #endif
 
 // Output clock on LSCO pin(PA2) for debugging purpose
@@ -121,7 +121,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 #if DEVICE_USBDEVICE
     RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
 #endif /* DEVICE_USBDEVICE */
-    
+
     /* GPIO Ports Clock Enable */
     __HAL_RCC_GPIOH_CLK_ENABLE();
     __HAL_RCC_GPIOB_CLK_ENABLE();
@@ -176,7 +176,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 160 MHz
     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 160 MHz
     RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;           // 160 MHz
-    
+
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
         return 0; // FAIL
     }
@@ -274,6 +274,12 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
         return 0; // FAIL
     }
 
+    /** Enable MSI Auto calibration
+     */
+    HAL_RCCEx_EnableMSIPLLModeSelection(RCC_MSIKPLL_MODE_SEL);
+    HAL_RCCEx_EnableMSIPLLMode();
+    HAL_RCCEx_EnableMSIPLLFastStartup();
+
     return 1; // OK
 }
 #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/system_clock.c

@@ -98,7 +98,73 @@ MBED_WEAK void SetSysClock(void)
 /******************************************************************************/
 MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 {
-    return 0;
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+
+#if DEVICE_USBDEVICE
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+#endif /* DEVICE_USBDEVICE */
+
+    /* GPIO Ports Clock Enable */
+    __HAL_RCC_GPIOH_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_PWR_CLK_ENABLE();
+    if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External clock on OSC_IN
+    }
+#if DEVICE_USBDEVICE
+    RCC_OscInitStruct.HSI48State            = RCC_HSI48_ON;
+#else
+    RCC_OscInitStruct.HSI48State            = RCC_HSI48_OFF;
+#endif /* DEVICE_USBDEVICE */
+#if HSE_VALUE==10000000UL
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMBOOST         = RCC_PLLMBOOST_DIV1;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 10 MHz (10 MHz / 1)
+#else
+#error Unsupported external clock value, check HSE_VALUE define
+#endif
+    RCC_OscInitStruct.PLL.PLLN              = 16; // VCO output clock = 160 MHz (10 MHz * 16)
+    RCC_OscInitStruct.PLL.PLLP              = 2;
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 1;  // PLL clock = 160 MHz
+    RCC_OscInitStruct.PLL.PLLRGE            = RCC_PLLVCIRANGE_1;
+    RCC_OscInitStruct.PLL.PLLFRACN          = 0;
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+#if DEVICE_USBDEVICE
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkIniRCC_PeriphClkInittStruct.UsbClockSelection    = RCC_USBCLKSOURCE_HSI48; /* 48 MHz */
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+#endif /* DEVICE_USBDEVICE */
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clock dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 160 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 160 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 160 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 160 MHz
+    RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;           // 160 MHz
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+   return 1; // OK
+
 }
 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
 
@@ -167,6 +233,11 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
         return 0; // FAIL
     }
 
+    /** Enable MSI Auto calibration
+     */
+    HAL_RCCEx_EnableMSIPLLModeSelection(RCC_MSIKPLL_MODE_SEL);
+    HAL_RCCEx_EnableMSIPLLMode();
+    HAL_RCCEx_EnableMSIPLLFastStartup();
 
     return 1; // OK
 }

targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/system_clock.c

@@ -167,6 +167,12 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
         return 0; // FAIL
     }
 
+    /** Enable MSI Auto calibration
+     */
+    HAL_RCCEx_EnableMSIPLLModeSelection(RCC_MSIKPLL_MODE_SEL);
+    HAL_RCCEx_EnableMSIPLLMode();
+    HAL_RCCEx_EnableMSIPLLFastStartup();
+
     return 1; // OK
 }
 #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U5A5xJ/system_clock.c

@@ -219,6 +219,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
      */
     HAL_RCCEx_EnableMSIPLLModeSelection(RCC_MSIKPLL_MODE_SEL);
     HAL_RCCEx_EnableMSIPLLMode();
+    HAL_RCCEx_EnableMSIPLLFastStartup();
 
     return 1; // OK
 }