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added Cache_Init() weak function for STM32 targets and provide a default implementation for STM32F7/H7 with L1 cache
override Cache_Init() function for STM32U5/H5 Cache_Init() function is called by mbed_sdk_init()
1 parent 1eaecd3 commit b19a330

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10 files changed

+120
-40
lines changed

10 files changed

+120
-40
lines changed

‎targets/TARGET_STM/TARGET_STM32H5/CMakeLists.txt‎

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Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ target_sources(mbed-stm32h5
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serial_device.c
1818
spi_api.c
1919
pwmout_device.c
20+
cache.c
2021
)
2122

2223
target_include_directories(mbed-stm32h5

‎targets/TARGET_STM/TARGET_STM32H5/cache.c‎

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@@ -0,0 +1,64 @@
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/* mbed Microcontroller Library
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* SPDX-License-Identifier: BSD-3-Clause
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******************************************************************************
4+
*
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* Copyright (c) 2015-2021 STMicroelectronics.
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* All rights reserved.
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*
8+
* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
10+
* License. You may obtain a copy of the License at:
11+
* opensource.org/licenses/BSD-3-Clause
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*
13+
******************************************************************************
14+
*/
15+
#include "stm32h5xx.h"
16+
#include "mbed_error.h"
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18+
/**
19+
* @brief Enable ICACHE and define a MPU region to avoid HardFaults when accessing OTP and RO regions
20+
* @param None
21+
* @retval None
22+
*/
23+
24+
void Cache_Init()
25+
{
26+
MPU_Attributes_InitTypeDef attr;
27+
MPU_Region_InitTypeDef region;
28+
29+
/* Disable MPU before perloading and config update */
30+
HAL_MPU_Disable();
31+
32+
/* Configurate 0x00000000-0x08FFF7FF as Read Only, Executable and Cacheable */
33+
region.Enable = MPU_REGION_ENABLE;
34+
region.Number = MPU_REGION_NUMBER0;
35+
region.AttributesIndex = MPU_ATTRIBUTES_NUMBER0;
36+
region.BaseAddress = 0x00000000;
37+
region.LimitAddress = 0x08FFF7FF;
38+
region.AccessPermission = MPU_REGION_ALL_RO;
39+
region.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
40+
region.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
41+
HAL_MPU_ConfigRegion(&region);
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43+
/* Define cacheable memory via MPU */
44+
attr.Number = MPU_ATTRIBUTES_NUMBER5;
45+
attr.Attributes = INNER_OUTER(MPU_NOT_CACHEABLE);
46+
HAL_MPU_ConfigMemoryAttributes(&attr);
47+
48+
/* Configurate 0x08FFF800-0X0FFFFFFF as Read Only, Not Executable and Non-cacheable */
49+
region.Enable = MPU_REGION_ENABLE;
50+
region.Number = MPU_REGION_NUMBER5;
51+
region.AttributesIndex = MPU_ATTRIBUTES_NUMBER5;
52+
region.BaseAddress = 0x08FFF800;
53+
region.LimitAddress = MBED_CONF_TARGET_MPU_ROM_END;
54+
region.AccessPermission = MPU_REGION_ALL_RO;
55+
region.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
56+
region.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
57+
HAL_MPU_ConfigRegion(&region);
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59+
/* Enable the MPU */
60+
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
61+
62+
/* Enable ICACHE */
63+
HAL_ICACHE_Enable();
64+
}

‎targets/TARGET_STM/TARGET_STM32U5/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ target_sources(mbed-stm32u5
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i2c_device.c
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serial_device.c
2828
spi_api.c
29+
cache.c
2930
)
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3132
target_link_libraries(mbed-stm32u5 INTERFACE mbed-stm mbed-stm32u5cube-fw)

‎targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U545xE/system_clock.c‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -156,11 +156,6 @@ uint8_t SetSysClock_PLL_HSI(void)
156156
return 0; // FAIL
157157
}
158158

159-
/** Enable ICACHE
160-
*/
161-
HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
162-
HAL_ICACHE_Enable();
163-
164159
return 1; // OK
165160
}
166161
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
@@ -224,11 +219,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
224219
HAL_RCCEx_EnableMSIPLLModeSelection(RCC_MSIKPLL_MODE_SEL);
225220
HAL_RCCEx_EnableMSIPLLMode();
226221

227-
/** Enable ICACHE
228-
*/
229-
HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
230-
HAL_ICACHE_Enable();
231-
232222
return 1; // OK
233223
}
234224
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

‎targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/system_clock.c‎

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Original file line numberDiff line numberDiff line change
@@ -274,9 +274,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
274274
return 0; // FAIL
275275
}
276276

277-
HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
278-
HAL_ICACHE_Enable();
279-
280277
return 1; // OK
281278
}
282279
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

‎targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/system_clock.c‎

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Original file line numberDiff line numberDiff line change
@@ -167,8 +167,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
167167
return 0; // FAIL
168168
}
169169

170-
HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
171-
HAL_ICACHE_Enable();
172170

173171
return 1; // OK
174172
}

‎targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/system_clock.c‎

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Original file line numberDiff line numberDiff line change
@@ -167,9 +167,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
167167
return 0; // FAIL
168168
}
169169

170-
HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
171-
HAL_ICACHE_Enable();
172-
173170
return 1; // OK
174171
}
175172
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

‎targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U5A5xJ/system_clock.c‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -156,11 +156,6 @@ uint8_t SetSysClock_PLL_HSI(void)
156156
return 0; // FAIL
157157
}
158158

159-
/** Enable ICACHE
160-
*/
161-
HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
162-
HAL_ICACHE_Enable();
163-
164159
return 1; // OK
165160
}
166161
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
@@ -225,11 +220,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
225220
HAL_RCCEx_EnableMSIPLLModeSelection(RCC_MSIKPLL_MODE_SEL);
226221
HAL_RCCEx_EnableMSIPLLMode();
227222

228-
/** Enable ICACHE
229-
*/
230-
HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
231-
HAL_ICACHE_Enable();
232-
233223
return 1; // OK
234224
}
235225
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

‎targets/TARGET_STM/TARGET_STM32U5/cache.c‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
/* mbed Microcontroller Library
2+
* SPDX-License-Identifier: BSD-3-Clause
3+
******************************************************************************
4+
*
5+
* Copyright (c) 2015-2021 STMicroelectronics.
6+
* All rights reserved.
7+
*
8+
* This software component is licensed by ST under BSD 3-Clause license,
9+
* the "License"; You may not use this file except in compliance with the
10+
* License. You may obtain a copy of the License at:
11+
* opensource.org/licenses/BSD-3-Clause
12+
*
13+
******************************************************************************
14+
*/
15+
#include "stm32u5xx.h"
16+
#include "mbed_error.h"
17+
18+
/**
19+
* @brief Enable ICACHE
20+
* @param None
21+
* @retval None
22+
*/
23+
24+
void Cache_Init()
25+
{
26+
HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
27+
HAL_ICACHE_Enable();
28+
}

‎targets/TARGET_STM/mbed_overrides.c‎

Lines changed: 26 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,31 @@ MBED_WEAK void TargetBSP_Init(void)
8585
/** Do nothing */
8686
}
8787

88+
/**
89+
* @brief Enable cache if the target CPU has cache
90+
*
91+
* @note The default implementation works on STM32F7/H7 series with L1 cache.
92+
* This declaration is weak so it may be overridden for other STM32 series
93+
*
94+
* @param None
95+
* @retval None
96+
*/
97+
MBED_WEAK void Cache_Init(void)
98+
{
99+
#if defined(__ICACHE_PRESENT) /* STM32F7/H7 */
100+
// This function can be called either during cold boot or during
101+
// application boot after bootloader has been executed.
102+
// In case the bootloader has already enabled the cache,
103+
// is is needed to not enable it again.
104+
if ((SCB->CCR & (uint32_t)SCB_CCR_IC_Msk) == 0) { // If ICache is disabled
105+
SCB_EnableICache();
106+
}
107+
if ((SCB->CCR & (uint32_t)SCB_CCR_DC_Msk) == 0) { // If DCache is disabled
108+
SCB_EnableDCache();
109+
}
110+
#endif /* __ICACHE_PRESENT */
111+
}
112+
88113
#ifndef MBED_DEBUG
89114
#if MBED_CONF_TARGET_GPIO_RESET_AT_INIT
90115
void GPIO_Full_Init(void)
@@ -160,18 +185,7 @@ void GPIO_Full_Init(void)
160185
// This function is called after RAM initialization and before main.
161186
void mbed_sdk_init()
162187
{
163-
#if defined(__ICACHE_PRESENT) /* STM32F7 */
164-
// The mbed_sdk_init can be called either during cold boot or during
165-
// application boot after bootloader has been executed.
166-
// In case the bootloader has already enabled the cache,
167-
// is is needed to not enable it again.
168-
if ((SCB->CCR & (uint32_t)SCB_CCR_IC_Msk) == 0) { // If ICache is disabled
169-
SCB_EnableICache();
170-
}
171-
if ((SCB->CCR & (uint32_t)SCB_CCR_DC_Msk) == 0) { // If DCache is disabled
172-
SCB_EnableDCache();
173-
}
174-
#endif /* __ICACHE_PRESENT */
188+
Cache_Init();
175189

176190
#if defined(DUAL_CORE) && (TARGET_STM32H7)
177191
/* HW semaphore Clock enable*/

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