STM32WB55 SPI DMA erratic CS behaviour

[chrissnow]

I haven't got a definitive cause yet but I have noticed that chip select can get stuck low, most likely when transactions get queued up.

We have a GPIO IRQ that calls transfer and if another IRQ came in before it had actually completed the last transaction the SPI bus would be unusable in future with CS stuck low, but the SPI bus would still pass the data.

In addition I don't think hardware SSEL control is working at all, We have to use "use_gpio_ssel" but it would be better not to.

[multiplemonomials]

Hmm, I do have a basic test of the SPI transaction queue, but it isn't super exhaustive. If you could suggest a specific test to run that demonstrates the issue, I can take a look!