diff --git a/TESTS/configs/greentea_full.json5 b/TESTS/configs/greentea_full.json5 index f8581195cef..999784c4442 100644 --- a/TESTS/configs/greentea_full.json5 +++ b/TESTS/configs/greentea_full.json5 @@ -9,7 +9,7 @@ // Allow lots of reboots so that we don't get in a situation where the MCU refuses to boot // after crashing and being reflashed (since some MCUs/flash tools don't reset the // crash data RAM) - "platform.error-reboot-max": 2147483648, + "platform.error-reboot-max": 2147483647, // Emit a KV pair when an assert fail or hardfault occurs "platform.mbed-error-emit-greentea-kv": true, diff --git a/drivers/include/drivers/SerialBase.h b/drivers/include/drivers/SerialBase.h index a688f2b685c..42ca746a028 100644 --- a/drivers/include/drivers/SerialBase.h +++ b/drivers/include/drivers/SerialBase.h @@ -69,8 +69,22 @@ class SerialBase : private NonCopyable { enum Flow { Disabled = 0, + + /// RS-232-E RTS flow control. This is used to prevent the other end of the connection from sending more + /// bytes than the Mbed MCU can process. + /// When this flow control is active, the RTS signal will normally be asserted (low), + /// but will go deasserted (high) if the Mbed MCU might not have Rx buffer space to store another byte. + /// Note that in this configuration the RTS signal actually operates as a "ready to receive" (RTR) output, + /// not a true RTS. RTS, + + /// RS-232 CTS flow control. This is used to prevent the Mbed MCU from sending more bytes than the + /// other end of the connection can process. + /// When this flow control is active, the CTS pin will be sampled after transmitting each byte, and if + /// if is deasserted (high), transmission will pause until it becomes asserted (low) again. CTS, + + /// Combination of RTS and CTS flow control as previously defined. RTSCTS }; diff --git a/hal/include/hal/pinmap.h b/hal/include/hal/pinmap.h index fc9aa201cc3..3a2f4875a17 100644 --- a/hal/include/hal/pinmap.h +++ b/hal/include/hal/pinmap.h @@ -74,7 +74,6 @@ uint32_t pinmap_find_function(PinName pin, const PinMap *map); * { * int per = spi_master_cs_pinmap()->peripheral; * const PinList *pins_ff = pinmap_ff_default_pins(); - * const PinList *pins_avoid = pinmap_restricted_pins(); * PinName mosi = NC; * PinName miso = NC; * PinName sclk = NC; @@ -138,22 +137,6 @@ bool pinmap_list_has_pin(const PinList *list, PinName pin); */ bool pinmap_list_has_peripheral(const PeripheralList *list, int peripheral); -/** - * Get the pin list of pins to avoid during testing - * - * The restricted pin list is used to indicate to testing - * that a pin should be skipped due to some caveat about it. - * For example, using CONSOLE_RX and CONSOLE_TX during tests will interfere - * with the test runner and should be avoided. - * - * Targets should override the weak implementation of this - * function if they have additional pins which should be - * skipped during testing. - * - * @return Pointer to a pin list of pins to avoid - */ -const PinList *pinmap_restricted_pins(void); - /** * Get the pin list of peripherals per interface to avoid during testing * diff --git a/hal/source/mbed_pinmap_default.cpp b/hal/source/mbed_pinmap_default.cpp index 1290b8d58ed..616394a8122 100644 --- a/hal/source/mbed_pinmap_default.cpp +++ b/hal/source/mbed_pinmap_default.cpp @@ -66,19 +66,6 @@ const char *pinmap_ff_arduino_uno_pin_to_string(PinName pin) #endif // defined (TARGET_FF_ARDUINO) || (TARGET_FF_ARDUINO_UNO) -//*** Default restricted pins *** -MBED_WEAK const PinList *pinmap_restricted_pins() -{ - static const PinName pins[] = { - CONSOLE_TX, CONSOLE_RX - }; - static const PinList pin_list = { - sizeof(pins) / sizeof(pins[0]), - pins - }; - return &pin_list; -} - //*** Default restricted gpio pins *** // GPIO pins are special case because there are no pin-maps for GPIO MBED_WEAK const PinList *pinmap_gpio_restricted_pins() diff --git a/hal/source/mpu/mbed_mpu_v7m.c b/hal/source/mpu/mbed_mpu_v7m.c index 740c3b5c6f8..735391a6e1f 100644 --- a/hal/source/mpu/mbed_mpu_v7m.c +++ b/hal/source/mpu/mbed_mpu_v7m.c @@ -59,7 +59,7 @@ void mbed_mpu_init() MBED_ASSERT(regions >= 4); #endif - // Disable the MCU + // Disable the MPU MPU->CTRL = 0; // Reset all mapping diff --git a/platform/mbed_lib.json b/platform/mbed_lib.json index 45d611aa807..33d9dbaaf9a 100644 --- a/platform/mbed_lib.json +++ b/platform/mbed_lib.json @@ -253,6 +253,9 @@ }, "MIMXRT105X": { "crash-capture-enabled": true + }, + "MCU_LPC546XX": { + "crash-capture-enabled": true } } } diff --git a/platform/tests/TESTS/host_tests/crash_reporting.py b/platform/tests/TESTS/host_tests/crash_reporting.py index 45bf566c863..3cbed69f87d 100644 --- a/platform/tests/TESTS/host_tests/crash_reporting.py +++ b/platform/tests/TESTS/host_tests/crash_reporting.py @@ -40,6 +40,10 @@ def __init__(self): def setup(self): self.register_callback(MSG_KEY_DEVICE_READY, self.cb_device_ready) + # Disable the default behavior of ending the test when the target experiences a fatal error. + # In this test, we intentionally generate a fatal error! + self.register_callback("mbed_error", lambda key, value, timestamp: None) + def cb_device_ready(self, key, value, timestamp): """Acknowledge device rebooted correctly and feed the test execution """ @@ -68,7 +72,7 @@ def test_steps(self): system_reset = yield if self.reset == False: - raise RuntimeError('Platform did not auto-reboot as expected.') + raise RuntimeError('Platform did not auto-reboot as expected. This is likely due to failing to auto-reboot after a reset, or failing to preserve the contents of crash data RAM across resets.') # The sequence is correct -- test passed. yield True diff --git a/storage/blockdevice/COMPONENT_DATAFLASH/source/DataFlashBlockDevice.cpp b/storage/blockdevice/COMPONENT_DATAFLASH/source/DataFlashBlockDevice.cpp index cddcc146c4b..82b30168faa 100644 --- a/storage/blockdevice/COMPONENT_DATAFLASH/source/DataFlashBlockDevice.cpp +++ b/storage/blockdevice/COMPONENT_DATAFLASH/source/DataFlashBlockDevice.cpp @@ -26,7 +26,8 @@ using namespace mbed; #define DATAFLASH_READ_SIZE 1 #define DATAFLASH_PROG_SIZE 1 #define DATAFLASH_TIMEOUT 10000 -#define DATAFLASH_ID_MATCH 0x1F20 +#define DATAFLASH_ID_MASK 0xFFE0 // Matches Manufacturer ID and Family Code +#define DATAFLASH_ID_MATCH 0x1F20 // Matches Adesto/Renesas AT45Dxxx family #define DATAFLASH_ID_DENSITY_MASK 0x001F #define DATAFLASH_PAGE_SIZE_256 0x0100 #define DATAFLASH_PAGE_SIZE_264 0x0108 @@ -186,13 +187,13 @@ int DataFlashBlockDevice::init() /* read ID register to validate model and set dimensions */ uint16_t id = _get_register(DATAFLASH_OP_ID); - DEBUG_PRINTF("id: %04X\r\n", id & DATAFLASH_ID_MATCH); + DEBUG_PRINTF("id: %04X\r\n", id); /* get status register to verify the page size mode */ uint16_t status = _get_register(DATAFLASH_OP_STATUS); /* manufacture ID match */ - if ((id & DATAFLASH_ID_MATCH) == DATAFLASH_ID_MATCH) { + if ((id & DATAFLASH_ID_MASK) == DATAFLASH_ID_MATCH) { /* calculate density */ _device_size = 0x8000 << (id & DATAFLASH_ID_DENSITY_MASK); @@ -656,7 +657,7 @@ int DataFlashBlockDevice::_sync(void) /* wait the typical write period before trying again */ } else { DEBUG_PRINTF("sleep_for: %d\r\n", DATAFLASH_TIMING_ERASE_PROGRAM_PAGE); - rtos::ThisThread::sleep_for(DATAFLASH_TIMING_ERASE_PROGRAM_PAGE); + rtos::ThisThread::sleep_for(std::chrono::milliseconds(DATAFLASH_TIMING_ERASE_PROGRAM_PAGE)); } } diff --git a/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json b/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json index 9bf7388b0f3..a5093d85a1c 100644 --- a/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json +++ b/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json @@ -50,7 +50,7 @@ "SPI_CS": "PB_12", "SPI_FREQ": "20000000" }, - "UHURU_RAVEN": { + "UHURU_RAVEN": { "SPI_MOSI": "PE_14", "SPI_MISO": "PE_13", "SPI_CLK": "PE_12", @@ -68,8 +68,8 @@ "SPI_CLK": "SPI3_SCK", "SPI_CS": "SPI_CS1" }, - "ARDUINO_NICLA_SENSE_ME": { + "ARDUINO_NICLA_SENSE_ME": { "SPI_CS": "CS_FLASH" - } + } } } diff --git a/targets/TARGET_NUVOTON/TARGET_M460/pinmap.c b/targets/TARGET_NUVOTON/TARGET_M460/pinmap.c index 7474c0aed89..3bae10d9e7e 100644 --- a/targets/TARGET_NUVOTON/TARGET_M460/pinmap.c +++ b/targets/TARGET_NUVOTON/TARGET_M460/pinmap.c @@ -84,27 +84,6 @@ void pin_mode(PinName pin, PinMode mode) */ } -/* List of pins excluded from testing */ -const PinList *pinmap_restricted_pins() -{ - static const PinName pins[] = { - CONSOLE_TX, CONSOLE_RX, // Dedicated to USB VCOM -#if MBED_CONF_TARGET_EXCLUDE_UNO_SPI_FROM_FPGA_CI_TEST_SHIELD_TEST - ARDUINO_UNO_D8, // Dedicated to on-board SPI flash - ARDUINO_UNO_D9, - ARDUINO_UNO_D10, - ARDUINO_UNO_D11, - ARDUINO_UNO_D12, - ARDUINO_UNO_D13, -#endif - }; - static const PinList pin_list = { - sizeof(pins) / sizeof(pins[0]), - pins - }; - return &pin_list; -} - /* List of UART peripherals excluded from testing */ #if DEVICE_SERIAL const PeripheralList *pinmap_uart_restricted_peripherals() diff --git a/targets/TARGET_NUVOTON/TARGET_M480/pinmap.c b/targets/TARGET_NUVOTON/TARGET_M480/pinmap.c index bb5d1d23055..2eb3490f744 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/pinmap.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/pinmap.c @@ -84,22 +84,6 @@ void pin_mode(PinName pin, PinMode mode) */ } -/* List of pins excluded from testing */ -const PinList *pinmap_restricted_pins() -{ - static const PinName pins[] = { - CONSOLE_TX, CONSOLE_RX, // Dedicated to USB VCOM -#if defined(TARGET_NUMAKER_IOT_M487) - A2, A3, // Dedicated to on-board ESP8266 WiFi module RTS/CTS -#endif - }; - static const PinList pin_list = { - sizeof(pins) / sizeof(pins[0]), - pins - }; - return &pin_list; -} - /* List of UART peripherals excluded from testing */ #if DEVICE_SERIAL const PeripheralList *pinmap_uart_restricted_peripherals() diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/i2c_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/i2c_api.c index 68c3b050428..2cfcffd166f 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/i2c_api.c @@ -314,7 +314,7 @@ int i2c_slave_receive(i2c_t *obj) uint32_t status_flags = I2C_GetStatusFlags(i2c_addrs[obj->instance]); if (status_flags & kI2C_SlaveSelected) { - if (((status_flags >> I2C_STAT_SLVSTATE_SHIFT) & I2C_STAT_SLVSTATE_MASK) == 0x1) { + if (((status_flags & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == 0x1) { // read addressed return 1; } else { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/CMakeLists.txt b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/CMakeLists.txt index 0144b79ad97..bb9ab1607f6 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/CMakeLists.txt +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/CMakeLists.txt @@ -6,13 +6,9 @@ include(mbed_set_post_build_nxp) add_subdirectory(TARGET_FF_LPC546XX EXCLUDE_FROM_ALL) add_subdirectory(TARGET_LPCXpresso EXCLUDE_FROM_ALL) -if(${MBED_TOOLCHAIN} STREQUAL "ARM") - set(STARTUP_FILE device/TOOLCHAIN_ARM_STD/startup_LPC54628.S) - set(LINKER_FILE device/TOOLCHAIN_ARM_STD/LPC54628J512.sct) - set(LIB_POWER device/TOOLCHAIN_ARM_STD/lib_power.ar) -elseif(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") - set(STARTUP_FILE device/TOOLCHAIN_GCC_ARM/startup_LPC54628.S) - set(LINKER_FILE device/TOOLCHAIN_GCC_ARM/LPC54628J512.ld) +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE device/TOOLCHAIN_GCC_ARM/startup_LPC546xx.S) + set(LINKER_FILE device/TOOLCHAIN_GCC_ARM/LPC546xx.ld) set(LIB_POWER device/TOOLCHAIN_GCC_ARM/libpower.a) endif() @@ -35,6 +31,8 @@ target_sources(mbed-mcu-lpc546xx INTERFACE flash_api.c trng_api.c + mbed_overrides.cpp + mbed_mpu_lpc546xx.c device/system_LPC54628.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/CMakeLists.txt b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/CMakeLists.txt index 0f377214e4d..3331e98f550 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/CMakeLists.txt +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/CMakeLists.txt @@ -12,7 +12,6 @@ target_sources(mbed-ff-lpc546xx INTERFACE PeripheralPins.c clock_config.c - mbed_overrides.c ) target_link_libraries(mbed-ff-lpc546xx INTERFACE mbed-mcu-lpc546xx) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c index 00eae41497f..e1353c9a175 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c @@ -97,14 +97,12 @@ const PinMap PinMap_SPI_SCLK[] = { const PinMap PinMap_SPI_MOSI[] = { {P1_5, SPI_0, 1}, {P1_24, SPI_2, 1}, - {P0_8, SPI_3, 1}, {NC , NC , 0} }; const PinMap PinMap_SPI_MISO[] = { {P1_6, SPI_0, 1}, {P1_25, SPI_2, 1}, - {P0_9, SPI_3, 1}, {NC , NC , 0} }; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/PinNames.h index 69bd3055eac..44b7e5934b9 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/PinNames.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/PinNames.h @@ -184,15 +184,6 @@ typedef enum { P4_15 = (4 << PORT_SHIFT | 15), P4_16 = (4 << PORT_SHIFT | 16), - - - // mbed original LED naming - LED1 = P1_3, - LED2 = P1_27, - LED3 = P1_26, - LED4 = P1_28, - - // USB Pins CONSOLE_TX = P0_30, CONSOLE_RX = P0_29, @@ -233,19 +224,20 @@ typedef enum { p29 = P0_0, p30 = P0_1, - - I2C_SCL2 = P0_27, - I2C_SDA2 = P0_26, - I2C_SCL7 = P1_30, - I2C_SDA7 = P1_29, - I2C_SCL = I2C_SCL2, - I2C_SDA = I2C_SDA2, - - // Not connected NC = (int)0xFFFFFFFF } PinName; +#define LED1 P1_3 +#define LED2 P1_27 +#define LED3 P1_22 +#define LED4 P1_28 + +#define I2C_SCL0 P0_27 +#define I2C_SDA0 P0_26 + +#define I2C_SCL1 P1_30 +#define I2C_SDA1 P1_29 typedef enum { PullNone = 0, diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/CMakeLists.txt b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/CMakeLists.txt index a21bedbcb28..0fd7f028789 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/CMakeLists.txt +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/CMakeLists.txt @@ -13,5 +13,5 @@ target_sources(mbed-lpc546xx-xpresso PeripheralPins.c clock_config.c crc.c - mbed_overrides.c + overrides.c ) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c deleted file mode 100644 index 5be3bfef1fe..00000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c +++ /dev/null @@ -1,205 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "gpio_api.h" -#include "clock_config.h" -#include "fsl_emc.h" -#include "fsl_power.h" -#include "fsl_flashiap.h" -#include "hal/pinmap.h" - -#define CRC16 -#include "crc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* The SDRAM timing. */ -#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */ -#define SDRAM_TRP_NS (18u) -#define SDRAM_TRAS_NS (42u) -#define SDRAM_TSREX_NS (67u) -#define SDRAM_TAPR_NS (18u) -#define SDRAM_TWRDELT_NS (6u) -#define SDRAM_TRC_NS (60u) -#define SDRAM_RFC_NS (60u) -#define SDRAM_XSR_NS (67u) -#define SDRAM_RRD_NS (12u) -#define SDRAM_MRD_NCLK (2u) -#define SDRAM_RAS_NCLK (2u) -#define SDRAM_MODEREG_VALUE (0x23u) -#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/ - -uint32_t FLASHIAP_ReadUid(uint32_t *addr) -{ - uint32_t command[5], result[5]; - - command[0] = kIapCmd_FLASHIAP_ReadUid; - iap_entry(command, result); - - memcpy(addr, &result[1], (sizeof(uint32_t) * 4)); - - return result[0]; -} - -// called before main -void mbed_sdk_init() -{ - if (SYSCON->DEVICE_ID0 == 0xFFF54628) { - BOARD_BootClockFROHF96M(); /* Boot up FROHF96M for SPIFI to use*/ - /* LPC54628 runs at a higher core speed */ - BOARD_BootClockPLL220M(); - } else { - BOARD_BootClockFROHF96M(); /* Boot up FROHF96M for SPIFI to use*/ - BOARD_BootClockPLL180M(); - } -} - -// Change the NMI pin to an input. This allows NMI pin to -// be used as a low power mode wakeup. The application will -// need to change the pin back to NMI_b or wakeup only occurs once! -void NMI_Handler(void) -{ - //gpio_t gpio; - //gpio_init_in(&gpio, PTA4); -} - -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(void) -{ - /* Enable the RTC 32K Oscillator */ - SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK; -} - -uint32_t us_ticker_get_clock() -{ - return CLOCK_GetFreq(kCLOCK_BusClk);; -} - -// Provide ethernet devices with a semi-unique MAC address from the UUID -void mbed_mac_address(char *mac) -{ - uint16_t MAC[3]; // 3 16 bits words for the MAC - uint32_t UID[4]; - - // get UID via ISP commands - FLASHIAP_ReadUid(UID); - - // generate three CRC16's using different slices of the UUID - MAC[0] = crcSlow((const uint8_t *)UID, 8); // most significant half-word - MAC[1] = crcSlow((const uint8_t *)UID, 12); - MAC[2] = crcSlow((const uint8_t *)UID, 16); // least significant half word - - // The network stack expects an array of 6 bytes - // so we copy, and shift and copy from the half-word array to the byte array - mac[0] = MAC[0] >> 8; - mac[1] = MAC[0]; - mac[2] = MAC[1] >> 8; - mac[3] = MAC[1]; - mac[4] = MAC[2] >> 8; - mac[5] = MAC[2]; - - // We want to force bits [1:0] of the most significant byte [0] - // to be "10" - // http://en.wikipedia.org/wiki/MAC_address - - mac[0] |= 0x02; // force bit 1 to a "1" = "Locally Administered" - mac[0] &= 0xFE; // force bit 0 to a "0" = Unicast - -} - -void ADC_ClockPower_Configuration(void) -{ - /* SYSCON power. */ - POWER_DisablePD(kPDRUNCFG_PD_VDDA); /* Power on VDDA. */ - POWER_DisablePD(kPDRUNCFG_PD_ADC0); /* Power on the ADC converter. */ - POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); /* Power on the analog power supply. */ - POWER_DisablePD(kPDRUNCFG_PD_VREFP); /* Power on the reference voltage source. */ - POWER_DisablePD(kPDRUNCFG_PD_TS); /* Power on the temperature sensor. */ - - - /* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */ - /* Sync clock source is not used. Using sync clock source and would be divided by 2. - * The divider would be set when configuring the converter. - */ - CLOCK_EnableClock(kCLOCK_Adc0); /* SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_ADC0_MASK; */ - RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); -} - -/* Initialize the external memory. */ -void BOARD_InitSDRAM(void) -{ - emc_basic_config_t basicConfig; - emc_dynamic_timing_config_t dynTiming; - emc_dynamic_chip_config_t dynChipConfig; - - /* Basic configuration. */ - basicConfig.endian = kEMC_LittleEndian; - basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk; - /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M. - * If you change the divide to 0 and EMC clock is larger than 100M - * please take refer to emc.dox to adjust EMC clock delay. - */ - basicConfig.emcClkDiv = 1; - /* Dynamic memory timing configuration. */ - dynTiming.readConfig = kEMC_Cmddelay; - dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS; - dynTiming.tRp_Ns = SDRAM_TRP_NS; - dynTiming.tRas_Ns = SDRAM_TRAS_NS; - dynTiming.tSrex_Ns = SDRAM_TSREX_NS; - dynTiming.tApr_Ns = SDRAM_TAPR_NS; - dynTiming.tWr_Ns = (1000000000 / CLOCK_GetFreq(kCLOCK_EMC) + SDRAM_TWRDELT_NS); /* one clk + 6ns */ - dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns; - dynTiming.tRc_Ns = SDRAM_TRC_NS; - dynTiming.tRfc_Ns = SDRAM_RFC_NS; - dynTiming.tXsr_Ns = SDRAM_XSR_NS; - dynTiming.tRrd_Ns = SDRAM_RRD_NS; - dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK; - /* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */ - dynChipConfig.chipIndex = 0; - dynChipConfig.dynamicDevice = kEMC_Sdram; - dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK; - dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE; - dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */ - dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP; - /* EMC Basic configuration. */ - EMC_Init(EMC, &basicConfig); - /* EMC Dynamc memory configuration. */ - EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1); -} - -// Get the QSPI clock frequency -uint32_t qspi_get_freq(void) -{ - CLOCK_AttachClk(kFRO_HF_to_SPIFI_CLK); - - return CLOCK_GetFroHfFreq(); -} - -const PinList *pinmap_restricted_pins() -{ - /* D6 pin is used by the LCD - A4 pin is used by the accelerometer */ - static const PinName pins[] = { - D6, A4 - }; - static const PinList pin_list = { - sizeof(pins) / sizeof(pins[0]), - pins - }; - return &pin_list; -} - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/overrides.c similarity index 71% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/overrides.c index 9876f8290f5..d003c231766 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/overrides.c @@ -18,6 +18,8 @@ #include "clock_config.h" #include "fsl_emc.h" #include "fsl_power.h" +#include "fsl_flashiap.h" +#include "hal/pinmap.h" /******************************************************************************* * Definitions @@ -38,19 +40,6 @@ #define SDRAM_MODEREG_VALUE (0x23u) #define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/ -// called before main -void mbed_sdk_init() -{ - if (SYSCON->DEVICE_ID0 == 0xFFF54628) { - BOARD_BootClockFROHF96M(); /* Boot up FROHF96M for SPIFI to use*/ - /* LPC54628 runs at a higher core speed */ - BOARD_BootClockPLL220M(); - } else { - BOARD_BootClockFROHF96M(); /* Boot up FROHF96M for SPIFI to use*/ - BOARD_BootClockPLL180M(); - } -} - // Change the NMI pin to an input. This allows NMI pin to // be used as a low power mode wakeup. The application will // need to change the pin back to NMI_b or wakeup only occurs once! @@ -60,34 +49,6 @@ void NMI_Handler(void) //gpio_init_in(&gpio, PTA4); } -// Enable the RTC oscillator if available on the board -void rtc_setup_oscillator(void) -{ - /* Enable the RTC 32K Oscillator */ - SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK; -} - -uint32_t us_ticker_get_clock() -{ - return CLOCK_GetFreq(kCLOCK_BusClk);; -} - -void ADC_ClockPower_Configuration(void) -{ - /* SYSCON power. */ - POWER_DisablePD(kPDRUNCFG_PD_VDDA); /* Power on VDDA. */ - POWER_DisablePD(kPDRUNCFG_PD_ADC0); /* Power on the ADC converter. */ - POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); /* Power on the analog power supply. */ - POWER_DisablePD(kPDRUNCFG_PD_VREFP); /* Power on the reference voltage source. */ - POWER_DisablePD(kPDRUNCFG_PD_TS); /* Power on the temperature sensor. */ - - - /* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */ - /* Sync clock source is not used. Using sync clock source and would be divided by 2. - * The divider would be set when configuring the converter. - */ - CLOCK_EnableClock(kCLOCK_Adc0); /* SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_ADC0_MASK; */ -} /* Initialize the external memory. */ void BOARD_InitSDRAM(void) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54628J512.ld b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC546xx.ld similarity index 77% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54628J512.ld rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC546xx.ld index 7ab0dc2573f..83852b990c8 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54628J512.ld +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC546xx.ld @@ -55,16 +55,26 @@ __ram_vector_table__ = 1; __stack_size__ = MBED_CONF_TARGET_BOOT_STACK_SIZE; STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x400 : 0x0; +M_CRASH_DATA_RAM_SIZE = 0x100; +/* Specify the ELF segments (program headers) */ +PHDRS +{ + text PT_LOAD FLAGS(5); /* read + execute */ + ram_vector_table PT_LOAD FLAGS(6); /* read + write */ + ram_noinit PT_LOAD FLAGS(6); /* read + write */ + ram_init PT_LOAD FLAGS(6); /* read + write */ + sram_x PT_LOAD FLAGS(6); /* read + write */ + sram_usb PT_LOAD FLAGS(6); /* read + write */ +} /* Specify the memory areas */ MEMORY { - m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0007FC00 - m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00028000 - m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00008000 - m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00002000 + m_text (RX) : ORIGIN = MBED_CONFIGURED_ROM_BANK_PROGRAM_FLASH_START, LENGTH = MBED_CONFIGURED_ROM_BANK_PROGRAM_FLASH_SIZE + m_data (RW) : ORIGIN = MBED_RAM_BANK_SRAM_UPPER_START, LENGTH = MBED_RAM_BANK_SRAM_UPPER_SIZE + m_sramx (RW) : ORIGIN = MBED_RAM_BANK_SRAMX_START, LENGTH = MBED_RAM_BANK_SRAMX_SIZE + m_usb_sram (RW) : ORIGIN = MBED_RAM_BANK_USB_RAM_START, LENGTH = MBED_RAM_BANK_USB_RAM_SIZE } /* Define output sections */ @@ -74,10 +84,8 @@ SECTIONS .interrupts : { __VECTOR_TABLE = .; - . = ALIGN(8); KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(8); - } > m_interrupts + } > m_text :text /* The program code and other data goes into internal flash */ .text : @@ -93,19 +101,19 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) . = ALIGN(8); - } > m_text + } > m_text :text .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) - } > m_text + } > m_text :text .ARM : { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; - } > m_text + } > m_text :text .ctors : { @@ -129,7 +137,7 @@ SECTIONS KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) __CTOR_END__ = .; - } > m_text + } > m_text :text .dtors : { @@ -140,14 +148,14 @@ SECTIONS KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) __DTOR_END__ = .; - } > m_text + } > m_text :text .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); - } > m_text + } > m_text :text .init_array : { @@ -155,7 +163,7 @@ SECTIONS KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); - } > m_text + } > m_text :text .fini_array : { @@ -163,7 +171,7 @@ SECTIONS KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); - } > m_text + } > m_text :text __etext = .; /* define a global symbol at end of code */ __DATA_ROM = .; /* Symbol is used by startup for data initialization */ @@ -177,7 +185,7 @@ SECTIONS . += M_VECTOR_RAM_SIZE; . = ALIGN(8); __interrupts_ram_end__ = .; /* Define a global symbol at data end */ - } > m_data + } > m_data :ram_vector_table __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; @@ -193,14 +201,14 @@ SECTIONS KEEP(*(.jcr*)) . = ALIGN(8); __data_end__ = .; /* define a global symbol at data end */ - } > m_data + } > m_data :ram_init __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); text_end = ORIGIN(m_text) + LENGTH(m_text); ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") /* Uninitialized data section */ - .bss : + .bss (NOLOAD): { /* This is used by the startup in order to initialize the .bss section */ . = ALIGN(8); @@ -212,43 +220,64 @@ SECTIONS . = ALIGN(8); __bss_end__ = .; __END_BSS = .; - } > m_data + } > m_data :ram_noinit + + ASSERT(__bss_end__ <= ORIGIN(m_data) + LENGTH(m_data) - STACK_SIZE, "Size of globals + stack exceeds size of combined SRAM!") - .heap : + .heap (NOLOAD): { . = ALIGN(8); __end__ = .; - PROVIDE(end = .); - __HeapBase = .; + __mbed_sbrk_start = .; . = ORIGIN(m_data) + LENGTH(m_data) - STACK_SIZE; - __HeapLimit = .; - __heap_limit = .; /* Add for _sbrk */ - } > m_data + __mbed_krbs_start = .; + } > m_data :ram_noinit .stack : { . = ALIGN(8); . += STACK_SIZE; - } > m_data + } > m_data :ram_noinit + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); m_usb_bdt (NOLOAD) : { . = ALIGN(512); *(m_usb_bdt) - } > m_usb_sram + } > m_usb_sram :sram_usb m_usb_global (NOLOAD) : { *(m_usb_global) - } > m_usb_sram + } > m_usb_sram :sram_usb - /* Initializes stack on the end of block */ - __StackTop = ORIGIN(m_data) + LENGTH(m_data); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); +#if MBED_CONF_PLATFORM_CRASH_CAPTURE_ENABLED + /* Stick the crash data ram at the start of SRAMX */ + .crash_data_ram (NOLOAD): ALIGN(8) + { + __CRASH_DATA_RAM__ = .; + __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ + KEEP(*(.keep.crash_data_ram)) + *(.m_crash_data_ram) /* This is a user defined section */ + . += M_CRASH_DATA_RAM_SIZE; + . = ALIGN(8); + __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ + } > m_sramx :sram_x +#endif - .ARM.attributes 0 : { *(.ARM.attributes) } + /* Use SRAMX for additional heap */ + .heap_0 (NOLOAD): + { + . = ALIGN(8); + __mbed_sbrk_start_0 = .; + . = ORIGIN(m_sramx) + LENGTH(m_sramx); + __mbed_krbs_start_0 = .; + } > m_sramx :sram_x - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") + .ARM.attributes 0 : { *(.ARM.attributes) } } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC54628.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC546xx.S similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC54628.S rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC546xx.S diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/system_LPC54628.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/system_LPC54628.c index 1477bf8e220..b26c0e13c9d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/system_LPC54628.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/system_LPC54628.c @@ -272,6 +272,9 @@ void SystemInit (void) { SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + // Enable BusFault and MemManage faults so that they don't get raised as HardFaults + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk; + #if defined(__MCUXPRESSO) extern void(*const g_pfnVectors[]) (void); SCB->VTOR = (uint32_t) &g_pfnVectors; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/mbed_mpu_lpc546xx.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/mbed_mpu_lpc546xx.c new file mode 100644 index 00000000000..e4811750f84 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/mbed_mpu_lpc546xx.c @@ -0,0 +1,223 @@ +/* mbed Microcontroller Library + * Copyright (c) 2025 Jamie Smith + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/mpu_api.h" +#include "platform/mbed_assert.h" +#include "cmsis.h" + +enum { + REGION_CODE, + REGION_BOOTROM, + REGION_SRAMX, + REGION_SPIF, + REGION_SRAM, + REGION_PERIPHERAL, + REGION_USB_SRAM, // Note: this needs to be higher numbered than PERIPHERAL because it overlaps the peripheral mem space and needs to take priority + REGION_EXT_RAM +}; + +// Custom MPU init function for LPC546xx MCUs. +// This is needed because it has a memory bank (SRAMX) at an address lower than 0x2000 0000, which the default +// Mbed MPU configuration cannot handle. +void mbed_mpu_init() +{ + // Disable the MPU + ARM_MPU_Disable(); + + /* + * MPU region map: + * + * Start End Name Mbed MPU protection + * 0x0000 0000 - 0x0007 FFFF Code Write disabled + * 0x0300 0000 - 0x0300 FFFF Boot ROM Write disabled + * 0x0400 0000 - 0x0400 7FFF SRAMX Execute disabled + * 0x1000 0000 - 0x17FF FFFF SPIF Mem Mapped Write disabled + * 0x2000 0000 - 0x23FF FFFF SRAM Execute disabled + * 0x4000 0000 - 0x7FFF FFFF Peripheral + * 0x4010 0000 - 0x4010 1FFF USB SRAM Execute disabled + * 0x8000 0000 - 0xDFFF FFFF External RAM Execute disabled + */ + + // Code regions + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + REGION_CODE, // Region + 0x00000000), // Base + ARM_MPU_RASR( + 0, // DisableExec + ARM_MPU_AP_RO, // AccessPermission + 0, // TypeExtField + 0, // IsShareable + 1, // IsCacheable + 0, // IsBufferable + 0, // SubRegionDisable + ARM_MPU_REGION_SIZE_512KB) // Size + ); + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + REGION_BOOTROM, // Region + 0x03000000), // Base + ARM_MPU_RASR( + 0, // DisableExec + ARM_MPU_AP_RO, // AccessPermission + 0, // TypeExtField + 0, // IsShareable + 1, // IsCacheable + 0, // IsBufferable + 0, // SubRegionDisable + ARM_MPU_REGION_SIZE_64KB) // Size + ); + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + REGION_SPIF, // Region + 0x10000000), // Base + ARM_MPU_RASR( + 0, // DisableExec + ARM_MPU_AP_RO, // AccessPermission + 0, // TypeExtField + 0, // IsShareable + 1, // IsCacheable + 0, // IsBufferable + 0, // SubRegionDisable + ARM_MPU_REGION_SIZE_128MB) // Size + ); + + // Peripheral region + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + REGION_PERIPHERAL, // Region + 0x40000000), // Base + ARM_MPU_RASR( + 0, // DisableExec + ARM_MPU_AP_FULL, // AccessPermission + 2, // TypeExtField + 0, // IsShareable + 0, // IsCacheable + 0, // IsBufferable + 0, // SubRegionDisable + ARM_MPU_REGION_SIZE_1GB) // Size + ); + + // SRAMs + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + REGION_SRAMX, // Region + 0x04000000), // Base + ARM_MPU_RASR( + 1, // DisableExec + ARM_MPU_AP_FULL, // AccessPermission + 0, // TypeExtField + 0, // IsShareable + 1, // IsCacheable + 1, // IsBufferable + 0, // SubRegionDisable + ARM_MPU_REGION_SIZE_32KB) // Size + ); + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + REGION_SRAM, // Region + 0x20000000), // Base + ARM_MPU_RASR( + 1, // DisableExec + ARM_MPU_AP_FULL, // AccessPermission + 0, // TypeExtField + 0, // IsShareable + 1, // IsCacheable + 1, // IsBufferable + 0, // SubRegionDisable + ARM_MPU_REGION_SIZE_64MB) // Size + ); + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + REGION_USB_SRAM, // Region + 0x40100000), // Base + ARM_MPU_RASR( + 1, // DisableExec + ARM_MPU_AP_FULL, // AccessPermission + 0, // TypeExtField + 0, // IsShareable + 1, // IsCacheable + 1, // IsBufferable + 0, // SubRegionDisable + ARM_MPU_REGION_SIZE_8KB) // Size + ); + ARM_MPU_SetRegion( + ARM_MPU_RBAR( + REGION_EXT_RAM, // Region + 0x80000000), // Base + ARM_MPU_RASR( + 1, // DisableExec + ARM_MPU_AP_FULL, // AccessPermission + 0, // TypeExtField + 0, // IsShareable + 1, // IsCacheable + 1, // IsBufferable + (1 << 7) | (1 << 6), // SubRegionDisable + ARM_MPU_REGION_SIZE_2GB) // Size + ); + + // Enable the MPU + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Pos); +} + +void mbed_mpu_free() +{ + // Flush memory writes before configuring the MPU. + __DMB(); + + // Disable the MPU + MPU->CTRL = 0; + + // Ensure changes take effect + __DSB(); + __ISB(); +} + +static void enable_region(bool enable, uint32_t region) +{ + MPU->RNR = region; + MPU->RASR = (MPU->RASR & ~MPU_RASR_ENABLE_Msk) | (enable << MPU_RASR_ENABLE_Pos); +} + +void mbed_mpu_enable_rom_wn(bool enable) +{ + // Flush memory writes before configuring the MPU. + __DMB(); + + enable_region(enable, REGION_CODE); + enable_region(enable, REGION_BOOTROM); + enable_region(enable, REGION_SPIF); + + // Ensure changes take effect + __DSB(); + __ISB(); +} + +void mbed_mpu_enable_ram_xn(bool enable) +{ + // Flush memory writes before configuring the MPU. + __DMB(); + + enable_region(enable, REGION_SRAMX); + enable_region(enable, REGION_SRAM); + enable_region(enable, REGION_USB_SRAM); + enable_region(enable, REGION_EXT_RAM); + + // Ensure changes take effect + __DSB(); + __ISB(); +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/mbed_overrides.cpp b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/mbed_overrides.cpp new file mode 100644 index 00000000000..8bcb3153c00 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/mbed_overrides.cpp @@ -0,0 +1,111 @@ +/* mbed Microcontroller Library + * Copyright (c) 2025 Jamie Smith + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_boot.h" +#include "clock_config.h" +#include "fsl_flashiap.h" +#include "fsl_power.h" + +#include "MbedCRC.h" + +// called before main +void mbed_sdk_init() +{ + if (SYSCON->DEVICE_ID0 == 0xFFF54628) { + BOARD_BootClockFROHF96M(); /* Boot up FROHF96M for SPIFI to use*/ + /* LPC54628 runs at a higher core speed */ + BOARD_BootClockPLL220M(); + } else { + BOARD_BootClockFROHF96M(); /* Boot up FROHF96M for SPIFI to use*/ + BOARD_BootClockPLL180M(); + } +} + +// Get the QSPI clock frequency +extern "C" uint32_t qspi_get_freq(void) +{ + CLOCK_AttachClk(kFRO_HF_to_SPIFI_CLK); + + return CLOCK_GetFroHfFreq(); +} + +uint32_t FLASHIAP_ReadUid(uint32_t *addr) +{ + uint32_t command[5], result[5]; + + command[0] = kIapCmd_FLASHIAP_ReadUid; + iap_entry(command, result); + + memcpy(addr, &result[1], (sizeof(uint32_t) * 4)); + + return result[0]; +} + +// Provide ethernet devices with a semi-unique MAC address from the UUID +void mbed_mac_address(char *mac) +{ + uint32_t UID[4]; + + // get UID via ISP commands + FLASHIAP_ReadUid(UID); + + // generate two 32-bit words using two slices of the 16-byte UID + mbed::MbedCRC crcGenerator; + uint32_t word1, word2; + crcGenerator.compute(UID, 8, &word1); + crcGenerator.compute(&UID[2], 8, &word2); + + // Copy the words into the MAC address + memcpy(mac, &word1, 4); + memcpy(mac + 4, &word2, 2); + + // We want to force bits [1:0] of the most significant byte [0] + // to be "10" + // http://en.wikipedia.org/wiki/MAC_address + mac[0] |= 0x02; // force bit 1 to a "1" = "Locally Administered" + mac[0] &= 0xFE; // force bit 0 to a "0" = Unicast +} + +// Enable the RTC oscillator if available on the board +extern "C" void rtc_setup_oscillator(void) +{ + /* Enable the RTC 32K Oscillator */ + SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK; +} + +extern "C" uint32_t us_ticker_get_clock() +{ + return CLOCK_GetFreq(kCLOCK_BusClk); +} + +extern "C" void ADC_ClockPower_Configuration(void) +{ + /* SYSCON power. */ + POWER_DisablePD(kPDRUNCFG_PD_VDDA); /* Power on VDDA. */ + POWER_DisablePD(kPDRUNCFG_PD_ADC0); /* Power on the ADC converter. */ + POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); /* Power on the analog power supply. */ + POWER_DisablePD(kPDRUNCFG_PD_VREFP); /* Power on the reference voltage source. */ + POWER_DisablePD(kPDRUNCFG_PD_TS); /* Power on the temperature sensor. */ + + + /* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */ + /* Sync clock source is not used. Using sync clock source and would be divided by 2. + * The divider would be set when configuring the converter. + */ + CLOCK_EnableClock(kCLOCK_Adc0); /* SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_ADC0_MASK; */ + RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); +} \ No newline at end of file diff --git a/targets/cmsis_mcu_descriptions.json5 b/targets/cmsis_mcu_descriptions.json5 index 9122b6d93cc..ed7e936c871 100644 --- a/targets/cmsis_mcu_descriptions.json5 +++ b/targets/cmsis_mcu_descriptions.json5 @@ -1731,7 +1731,7 @@ "version": "11.0.0" }, "memories": { - "EEPROM": { + "PROGRAM_FLASH": { "access": { "execute": true, "non_secure": false, @@ -1741,12 +1741,12 @@ "secure": false, "write": false }, - "default": false, - "size": 16384, - "start": 1074823168, - "startup": false + "default": true, + "size": 524288, + "start": 0, + "startup": true }, - "PROGRAM_FLASH": { + "EEPROM": { "access": { "execute": true, "non_secure": false, @@ -1756,10 +1756,10 @@ "secure": false, "write": false }, - "default": true, - "size": 524288, - "start": 0, - "startup": true + "default": false, + "size": 16384, + "start": 1074823168, + "startup": false }, "SRAMX": { "access": { @@ -1825,6 +1825,135 @@ "sub_family": null, "vendor": "NXP:11" }, + "LPC54606J512BD100": { + "algorithms": [ + { + "default": true, + "file_name": "devices/LPC54606/arm/LPC5460x_512.FLM", + "ram_size": 8192, + "ram_start": 536870912, + "size": 524288, + "start": 0, + "style": "Keil" + }, + { + "default": true, + "file_name": "devices/LPC54606/arm/LPC5460x_MT25QL128.FLM", + "ram_size": 8192, + "ram_start": 536870912, + "size": 134217728, + "start": 268435456, + "style": "Keil" + } + ], + "family": "LPC54606", + "from_pack": { + "pack": "LPC54606_DFP", + "url": "https://mcuxpresso.nxp.com/cmsis_pack/repo/", + "vendor": "NXP", + "version": "25.03.00" + }, + "memories": { + "PROGRAM_FLASH": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "p_name": null, + "size": 524288, + "start": 0, + "startup": true + }, + "EEPROM": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "p_name": null, + "size": 16384, + "start": 1074823168, + "startup": false + }, + "SRAMX": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "p_name": null, + "size": 32768, + "start": 67108864, + "startup": false + }, + "SRAM_UPPER": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "p_name": null, + "size": 163840, + "start": 536870912, + "startup": false + }, + "USB_RAM": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "p_name": null, + "size": 8192, + "start": 1074790400, + "startup": false + } + }, + "name": "LPC54606J512BD100", + "processors": [ + { + "address": null, + "ap": 0, + "apid": null, + "core": "CortexM4", + "default_reset_sequence": null, + "dp": 0, + "fpu": "SinglePrecision", + "mpu": "Present", + "name": null, + "svd": "devices/LPC54606/LPC54606.xml", + "unit": 0 + } + ], + "sub_family": null, + "vendor": "NXP:11" + }, "M2354KJFAE": { "algorithms": [ { diff --git a/targets/targets.json5 b/targets/targets.json5 index 63f27f850fb..62d293cf617 100644 --- a/targets/targets.json5 +++ b/targets/targets.json5 @@ -5606,7 +5606,9 @@ mode is recommended for target MCUs with small amounts of flash and RAM.", "macros": [ "CPU_LPC54628J512ET180", "FSL_RTOS_MBED", - "MBED_TICKLESS" + "MBED_TICKLESS", + "MBED_SPLIT_HEAP", + "MBED_MPU_CUSTOM" ], "inherits": [ "Target" @@ -5636,7 +5638,6 @@ mode is recommended for target MCUs with small amounts of flash and RAM.", "init-us-ticker-at-boot": true, "network-default-interface-type": "ETHERNET" }, - "device_name": "LPC54628J512ET180", "post_binary_hook": { "function": "LPCTargetCode.lpc_patch" }, @@ -5672,6 +5673,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.", "components_add": [ "QSPIF" ], + "device_name": "LPC54628J512ET180", "image_url": "https://www.nxp.com/assets/images/en/dev-board-image/LPCXpresso54608_back.png" }, "FF_LPC546XX": { @@ -5687,6 +5689,10 @@ mode is recommended for target MCUs with small amounts of flash and RAM.", "release_versions": [ "5" ], + // Note: this target has a DataFlash flash on the board, BUT they actually pinned it out wrong: + // SCLK is connected to SPI3, while MOSI and MISO are connected to SPI5. So, the flash is + // impossible to use, at least without bodge wires! + "device_name": "LPC54606J512BD100", "image_url": "https://os.mbed.com/media/cache/platforms/t17_VBxJMp4.png.250x250_q85.png" }, diff --git a/targets/upload_method_cfg/FF_LPC546XX.cmake b/targets/upload_method_cfg/FF_LPC546XX.cmake new file mode 100644 index 00000000000..efa5c33ba79 --- /dev/null +++ b/targets/upload_method_cfg/FF_LPC546XX.cmake @@ -0,0 +1,32 @@ +# Mbed OS upload method configuration file for target FF_LPC546XX. +# To change any of these parameters from their default values, set them in your build script between where you +# include app.cmake and where you add mbed os as a subdirectory. +# +# Notes: +# 1. PyOCD support for this device requires installing a pack: +# source the Mbed OS venv, then run +# $ pyocd pack install LPC54606J512BD100 +# 2. PyOCD support for this device is glitchy. Flashing and debugging work, but trying to flash +# or reset while in a debug session appears to crash the debug session. This means you have to +# edit the generated Mbed debug scripts to disable loading the code when starting a debug session. + +# General config parameters +# ------------------------------------------------------------- +set(UPLOAD_METHOD_DEFAULT MBED) + +# Config options for MBED +# ------------------------------------------------------------- + +set(MBED_UPLOAD_ENABLED TRUE) +set(MBED_RESET_BAUDRATE 115200) + +# Config options for PYOCD +# ------------------------------------------------------------- +set(PYOCD_UPLOAD_ENABLED TRUE) +set(PYOCD_TARGET_NAME LPC54606J512BD100) +set(PYOCD_CLOCK_SPEED 4000k) + +# Config options for LINKSERVER +# ------------------------------------------------------------- +set(LINKSERVER_UPLOAD_ENABLED TRUE) +set(LINKSERVER_DEVICE ${CMAKE_CURRENT_LIST_DIR}/linkserver_devices/FF_LPC546XX.json) diff --git a/targets/upload_method_cfg/linkserver_devices/FF_LPC546XX.json b/targets/upload_method_cfg/linkserver_devices/FF_LPC546XX.json new file mode 100644 index 00000000000..3d7e97aa17f --- /dev/null +++ b/targets/upload_method_cfg/linkserver_devices/FF_LPC546XX.json @@ -0,0 +1,54 @@ +{ + "copyright": "Copyright 2023-2024 NXP", + "license": "SPDX-License-Identifier: BSD-3-Clause", + "version": "1.1.0", + "vendor": "NXP", + "devices": [ + { + "board": "FF_LPC546XX", + "device": { + "id": "LPC54605J512", + "name": "LPC54606", + "family": "LPC546xx", + "memory": [ + { + "location": "0x00000000", + "size": "0x00080000", + "type": "Flash", + "flash-driver": "LPC5460x_512K.cfx" + }, + { + "location": "0x20000000", + "size": "0x00028000", + "type": "RAM" + }, + { + "location": "0x04000000", + "size": "0x00008000", + "type": "RAM" + }, + { + "location": "0x40100000", + "size": "0x00002000", + "type": "RAM" + }, + { + "location": "0x40000000", + "size": "0x000c0000", + "type": "RAM" + } + ], + "cores": [ + { + "type": "cm4", + "name": "cm4" + } + ] + }, + "debug": { + "protocol": "swd", + "swo": true + } + } + ] +} \ No newline at end of file diff --git a/tools/cmake/upload_methods/UploadMethodLINKSERVER.cmake b/tools/cmake/upload_methods/UploadMethodLINKSERVER.cmake index 5ee41ed2765..21b258de6e6 100644 --- a/tools/cmake/upload_methods/UploadMethodLINKSERVER.cmake +++ b/tools/cmake/upload_methods/UploadMethodLINKSERVER.cmake @@ -3,7 +3,8 @@ ### NXP LinkServer Upload Method # This method needs the following parameters: -# LINKSERVER_DEVICE - Chip name and board to connect to, separated by a colon. +# LINKSERVER_DEVICE - Chip name and board to connect to, separated by a colon, or path to custom +# device JSON file. set(UPLOAD_SUPPORTS_DEBUG TRUE) @@ -41,7 +42,9 @@ function(gen_upload_target TARGET_NAME BINARY_FILE) ${LINKSERVER_DEVICE} load --addr ${MBED_UPLOAD_BASE_ADDR} - ${BINARY_FILE}) + ${BINARY_FILE} + USES_TERMINAL + VERBATIM) endfunction(gen_upload_target) diff --git a/tools/cmake/upload_methods/UploadMethodPYOCD.cmake b/tools/cmake/upload_methods/UploadMethodPYOCD.cmake index f1a06dcf4a5..e08f564649d 100644 --- a/tools/cmake/upload_methods/UploadMethodPYOCD.cmake +++ b/tools/cmake/upload_methods/UploadMethodPYOCD.cmake @@ -34,7 +34,9 @@ function(gen_upload_target TARGET_NAME BINARY_FILE) ${PYOCD_PROBE_ARGS} --base-address ${MBED_UPLOAD_BASE_ADDR} ${PYOCD_EXTRA_OPTIONS} - ${BINARY_FILE}) + ${BINARY_FILE} + VERBATIM + USES_TERMINAL) endfunction(gen_upload_target) diff --git a/tools/python/mbed_os_tools/test/host_tests/base_host_test.py b/tools/python/mbed_os_tools/test/host_tests/base_host_test.py index 8c574f7b3b3..7691ac752e1 100644 --- a/tools/python/mbed_os_tools/test/host_tests/base_host_test.py +++ b/tools/python/mbed_os_tools/test/host_tests/base_host_test.py @@ -189,6 +189,7 @@ def __assign_default_callbacks(self): self.register_callback("mbed_error_module", self.__callback_default) self.register_callback("mbed_error_code", self.__callback_default) self.register_callback("mbed_error_message", self.__callback_default) + self.register_callback("mbed_error_location", self.__callback_default) def __assign_decorated_callbacks(self): """