Enable ICACHE, TRNG and WATCHDOG for STM32H5

targets/TARGET_STM/TARGET_STM32H5/CMakeLists.txt

@@ -17,6 +17,7 @@ target_sources(mbed-stm32h5
     serial_device.c
     spi_api.c
     pwmout_device.c
+    cache.c
 )
 
 target_include_directories(mbed-stm32h5

targets/TARGET_STM/TARGET_STM32H5/cache.c

@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ *
+ * Copyright (c) 2015-2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+#include "stm32h5xx.h"
+#include "mbed_error.h"
+
+/**
+  * @brief  Enable ICACHE and define a MPU region to avoid HardFaults when accessing OTP and RO regions
+  * @param  None
+  * @retval None
+  */
+
+void Cache_Init()
+{
+    MPU_Attributes_InitTypeDef   attr;
+    MPU_Region_InitTypeDef       region;
+
+    /* Disable MPU before perloading and config update */
+    HAL_MPU_Disable();
+
+    /* Configurate 0x00000000-0x08FFF7FF as Read Only, Executable and Cacheable */
+    region.Enable           = MPU_REGION_ENABLE;
+    region.Number           = MPU_REGION_NUMBER0;
+    region.AttributesIndex  = MPU_ATTRIBUTES_NUMBER0;
+    region.BaseAddress      = 0x00000000;
+    region.LimitAddress     = 0x08FFF7FF;
+    region.AccessPermission = MPU_REGION_ALL_RO;
+    region.DisableExec      = MPU_INSTRUCTION_ACCESS_ENABLE;
+    region.IsShareable      = MPU_ACCESS_NOT_SHAREABLE;
+    HAL_MPU_ConfigRegion(&region);
+
+    /* Define cacheable memory via MPU */
+    attr.Number             = MPU_ATTRIBUTES_NUMBER5;
+    attr.Attributes         = INNER_OUTER(MPU_NOT_CACHEABLE);
+    HAL_MPU_ConfigMemoryAttributes(&attr);
+
+    /* Configurate 0x08FFF800-0X0FFFFFFF as Read Only, Not Executable and Non-cacheable */
+    region.Enable           = MPU_REGION_ENABLE;
+    region.Number           = MPU_REGION_NUMBER5;
+    region.AttributesIndex  = MPU_ATTRIBUTES_NUMBER5;
+    region.BaseAddress      = 0x08FFF800;
+    region.LimitAddress     = MBED_CONF_TARGET_MPU_ROM_END;
+    region.AccessPermission = MPU_REGION_ALL_RO;
+    region.DisableExec      = MPU_INSTRUCTION_ACCESS_DISABLE;
+    region.IsShareable      = MPU_ACCESS_NOT_SHAREABLE;
+    HAL_MPU_ConfigRegion(&region);
+
+    /* Enable the MPU */
+    HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+
+    /* Enable ICACHE */
+    HAL_ICACHE_Enable();
+}

targets/TARGET_STM/TARGET_STM32H5/clock_cfg/system_clock.c

@@ -16,7 +16,7 @@
 /**
   * This file configures the system clock as follows:
   *--------------------------------------------------------------------
-  * System clock source   | 1- USE_PLL_HSE_EXTC 
+  * System clock source   | 1- USE_PLL_HSE_EXTC
   *                       | 2- USE_PLL_HSE_XTAL
   *                       | 3- USE_PLL_HSI (internal 64 MHz clock)
   *--------------------------------------------------------------------
@@ -45,6 +45,43 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
 uint8_t SetSysClock_PLL_HSI(void);
 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
 
+/**
+  * @brief  Enable ICACHE
+  * @param  None
+  * @retval None
+  */
+
+static void EnableICache()
+{
+    MPU_Attributes_InitTypeDef   attr;
+    MPU_Region_InitTypeDef       region;
+
+    /* Disable MPU before perloading and config update */
+    HAL_MPU_Disable();
+
+    /* Define cacheable memory via MPU */
+    attr.Number             = MPU_ATTRIBUTES_NUMBER5;
+    attr.Attributes         = INNER_OUTER(MPU_NOT_CACHEABLE);
+    HAL_MPU_ConfigMemoryAttributes(&attr);
+
+    /* BaseAddress-LimitAddress configuration */
+    region.Enable           = MPU_REGION_ENABLE;
+    region.Number           = MPU_REGION_NUMBER5;
+    region.AttributesIndex  = MPU_ATTRIBUTES_NUMBER5;
+    region.BaseAddress      = 0x08FFF800;
+    region.LimitAddress     = 0x08FFFFFF;
+    region.AccessPermission = MPU_REGION_ALL_RW;
+    region.DisableExec      = MPU_INSTRUCTION_ACCESS_DISABLE;
+    region.IsShareable      = MPU_ACCESS_NOT_SHAREABLE;
+    HAL_MPU_ConfigRegion(&region);
+
+    /* Enable the MPU */
+    HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+
+    /* Enable ICACHE */
+    HAL_ICACHE_Enable();
+}
+
 /**
   * @brief  Configures the System clock source
   * @note   This function should be called only once the RCC clock configuration
@@ -74,6 +111,7 @@ void SetSysClock(void)
             }
         }
     }
+    EnableICache();
 }
 
 
@@ -108,7 +146,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 #endif
 if(HSE_VALUE % 2000000 == 0)
 {
-    RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 2000000; // Divide down input clock to 2MHz 
+    RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 2000000; // Divide down input clock to 2MHz
     RCC_OscInitStruct.PLL.PLLN = 250; // Multiply up to 500MHz VCO clock
     RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1;
 }

targets/TARGET_STM/TARGET_STM32U5/CMakeLists.txt

@@ -26,6 +26,7 @@ target_sources(mbed-stm32u5
         i2c_device.c
         serial_device.c
         spi_api.c
+        cache.c
 )
 
 target_link_libraries(mbed-stm32u5 INTERFACE mbed-stm mbed-stm32u5cube-fw)

targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U545xE/system_clock.c

@@ -156,11 +156,6 @@ uint8_t SetSysClock_PLL_HSI(void)
         return 0; // FAIL
     }
 
-    /** Enable ICACHE
-     */
-    HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
-    HAL_ICACHE_Enable();
-
     return 1; // OK
 }
 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
@@ -224,11 +219,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
     HAL_RCCEx_EnableMSIPLLModeSelection(RCC_MSIKPLL_MODE_SEL);
     HAL_RCCEx_EnableMSIPLLMode();
 
-    /** Enable ICACHE
-     */
-    HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
-    HAL_ICACHE_Enable();
-
     return 1; // OK
 }
 #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/system_clock.c

@@ -274,9 +274,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
         return 0; // FAIL
     }
 
-    HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
-    HAL_ICACHE_Enable();
-
     return 1; // OK
 }
 #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/system_clock.c

@@ -167,8 +167,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
         return 0; // FAIL
     }
 
-    HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
-    HAL_ICACHE_Enable();
 
     return 1; // OK
 }

targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/system_clock.c

@@ -167,9 +167,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
         return 0; // FAIL
     }
 
-    HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
-    HAL_ICACHE_Enable();
-
     return 1; // OK
 }
 #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U5A5xJ/system_clock.c

@@ -156,11 +156,6 @@ uint8_t SetSysClock_PLL_HSI(void)
         return 0; // FAIL
     }
 
-    /** Enable ICACHE
-     */
-    HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
-    HAL_ICACHE_Enable();
-
     return 1; // OK
 }
 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
@@ -225,11 +220,6 @@ MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
     HAL_RCCEx_EnableMSIPLLModeSelection(RCC_MSIKPLL_MODE_SEL);
     HAL_RCCEx_EnableMSIPLLMode();
 
-    /** Enable ICACHE
-     */
-    HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
-    HAL_ICACHE_Enable();
-
     return 1; // OK
 }
 #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

targets/TARGET_STM/TARGET_STM32U5/cache.c

@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ *
+ * Copyright (c) 2015-2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+#include "stm32u5xx.h"
+#include "mbed_error.h"
+
+/**
+  * @brief  Enable ICACHE
+  * @param  None
+  * @retval None
+  */
+
+void Cache_Init()
+{
+    HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
+    HAL_ICACHE_Enable();
+}

targets/TARGET_STM/lp_ticker.c

@@ -266,7 +266,7 @@ void lp_ticker_init(void)
 #if defined (LPTIM_ACTIVEEDGE_FALLING)
     LptimHandle.Init.Trigger.ActiveEdge = LPTIM_ACTIVEEDGE_FALLING;
 #endif
-#if defined(TARGET_STM32U5) || defined(TARGET_STM32U0)
+#if defined(TARGET_STM32U5) || defined(TARGET_STM32H5) || defined(TARGET_STM32U0)
     LptimHandle.Init.Period = 0xFFFF;
 #endif
 #if defined (LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION)

targets/TARGET_STM/mbed_overrides.c

@@ -85,6 +85,31 @@ MBED_WEAK void TargetBSP_Init(void)
     /** Do nothing */
 }
 
+/**
+ * @brief Enable cache if the target CPU has cache
+ *
+ * @note The default implementation works on STM32F7/H7 series with L1 cache.
+ * This declaration is weak so it may be overridden for other STM32 series
+ *
+ * @param None
+ * @retval None
+ */
+MBED_WEAK void Cache_Init(void)
+{
+#if defined(__ICACHE_PRESENT) /* STM32F7/H7 */
+    // This function can be called either during cold boot or during
+    // application boot after bootloader has been executed.
+    // In case the bootloader has already enabled the cache,
+    // is is needed to not enable it again.
+    if ((SCB->CCR & (uint32_t)SCB_CCR_IC_Msk) == 0) { // If ICache is disabled
+        SCB_EnableICache();
+    }
+    if ((SCB->CCR & (uint32_t)SCB_CCR_DC_Msk) == 0) { // If DCache is disabled
+        SCB_EnableDCache();
+    }
+#endif /* __ICACHE_PRESENT */
+}
+
 #ifndef MBED_DEBUG
 #if MBED_CONF_TARGET_GPIO_RESET_AT_INIT
 void GPIO_Full_Init(void)
@@ -160,18 +185,7 @@ void GPIO_Full_Init(void)
 // This function is called after RAM initialization and before main.
 void mbed_sdk_init()
 {
-#if defined(__ICACHE_PRESENT) /* STM32F7 */
-    // The mbed_sdk_init can be called either during cold boot or during
-    // application boot after bootloader has been executed.
-    // In case the bootloader has already enabled the cache,
-    // is is needed to not enable it again.
-    if ((SCB->CCR & (uint32_t)SCB_CCR_IC_Msk) == 0) { // If ICache is disabled
-        SCB_EnableICache();
-    }
-    if ((SCB->CCR & (uint32_t)SCB_CCR_DC_Msk) == 0) { // If DCache is disabled
-        SCB_EnableDCache();
-    }
-#endif /* __ICACHE_PRESENT */
+    Cache_Init();
 
 #if defined(DUAL_CORE) && (TARGET_STM32H7)
     /* HW semaphore Clock enable*/

targets/TARGET_STM/trng_api.c

@@ -88,7 +88,7 @@ void trng_init(trng_t *obj)
         }
     }
 
-#elif defined(TARGET_STM32G4) || defined(TARGET_STM32U0)
+#elif defined(TARGET_STM32G4) || defined(TARGET_STM32H5) || defined(TARGET_STM32U0)
     /* RNG and USB clocks have the same HSI48 source which has been enabled in SetSysClock */
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
 

targets/TARGET_STM/watchdog_api.c

@@ -137,7 +137,7 @@ watchdog_features_t hal_watchdog_get_platform_features(void)
     features.clock_max_frequency = 47000;
 #elif defined(STM32F0) || defined(STM32F3)
     features.clock_max_frequency = 50000;
-#elif defined(STM32H7) || defined(STM32L4) || defined(STM32U5)
+#elif defined(STM32H7) || defined(STM32L4) || defined(STM32U5) || defined(STM32H5)
     features.clock_max_frequency = 33600;
 #elif defined(STM32G0) || defined(STM32L5) || defined(STM32G4) || defined(STM32WB) || defined(STM32WL) || defined(STM32U0)
     features.clock_max_frequency = 34000;

targets/targets.json5

@@ -3060,7 +3060,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
             "STM32G4A1xx"
         ]
     },
-	
+
     // STM32H5 Targets -------------------------------------------------------------------------------------------------
 	"MCU_STM32H5": {
         "inherits": [
@@ -3104,14 +3104,13 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
         "device_has_add": [
             "MPU",
             "ANALOGOUT",
-            "SPI_32BIT_WORDS"
+            "SPI_32BIT_WORDS",
+            "TRNG"
         ],
         "device_has_remove": [
             "FLASH",
-            "LPTICKER",
             "CAN",
-			"SERIAL_FC",
-            "WATCHDOG"
+			"SERIAL_FC"
         ],
         "is_mcu_family_target": true
     },
@@ -3193,7 +3192,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
         "device_name": "STM32H563ZITx",
         "image_url": "https://www.st.com/bin/ecommerce/api/image.PF274337.en.feature-description-include-personalized-no-cpn-medium.jpg"
     },
-	
+
     // STM32H7 Targets -------------------------------------------------------------------------------------------------
     "MCU_STM32H7": {
         "inherits": [
@@ -3435,7 +3434,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
         ],
         "device_name": "STM32H745ZITx"
     },
-	
+
 	// These targets contain the extra bits to add to the MCU_STM32H745xI target to set it for the
 	// CM4 or CM7 core.
     "MCU_STM32H745xI_CM4": {
@@ -4894,7 +4893,7 @@ mode is recommended for target MCUs with small amounts of flash and RAM.",
         ],
         "image_url": "https://www.st.com/bin/ecommerce/api/image.PF273876.en.feature-description-include-personalized-no-cpn-large.jpg"
     },
-  
+
     // STM32U5 Targets -------------------------------------------------------------------------------------------------
     "MCU_STM32U5": {
         "inherits": [