From acc6f7e9d7f63c478e1693c9d9523cd8da84c080 Mon Sep 17 00:00:00 2001 From: wdx04 <25487439@qq.com> Date: Wed, 27 Aug 2025 16:28:32 +0800 Subject: [PATCH 01/15] add QSPI support (with DMA) for STM32H5 --- .../TARGET_STM32H5/PeripheralNames.h | 6 + targets/TARGET_STM/TARGET_STM32H5/objects.h | 26 +- .../TARGET_STM/TARGET_STM32H5/stm_dma_info.h | 14 +- targets/TARGET_STM/qspi_api.c | 30 +- targets/TARGET_STM/stm_dma_ip_v3.h | 11 +- targets/TARGET_STM/stm_dma_utils.c | 284 ++++++++++++++++++ targets/TARGET_STM/xspi_compat.h | 133 ++++++++ 7 files changed, 490 insertions(+), 14 deletions(-) create mode 100644 targets/TARGET_STM/xspi_compat.h diff --git a/targets/TARGET_STM/TARGET_STM32H5/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32H5/PeripheralNames.h index d173f618825..6de87ce2593 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32H5/PeripheralNames.h @@ -173,6 +173,12 @@ typedef enum { #endif } CANName; +#if defined OCTOSPI1_R_BASE +typedef enum { + QSPI_1 = (int)OCTOSPI1_R_BASE, +} QSPIName; +#endif + #if defined OCTOSPI1_R_BASE typedef enum { OSPI_1 = (int)OCTOSPI1_R_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32H5/objects.h b/targets/TARGET_STM/TARGET_STM32H5/objects.h index 881d4d5fe4a..ecacb21672a 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/objects.h +++ b/targets/TARGET_STM/TARGET_STM32H5/objects.h @@ -28,6 +28,12 @@ #include "stm32h5xx_ll_pwr.h" #include "stm32h5xx_ll_system.h" +#include "stm_dma_info.h" +#if MBED_CONF_RTOS_PRESENT +#include "cmsis_os.h" +#include "cmsis_os2.h" +#endif + #ifdef __cplusplus extern "C" { #endif @@ -79,11 +85,8 @@ struct analogin_s { #if DEVICE_QSPI struct qspi_s { -#if defined(OCTOSPI1) - OSPI_HandleTypeDef handle; -#else - QSPI_HandleTypeDef handle; -#endif + XSPI_HandleTypeDef handle; + IRQn_Type qspiIRQ; QSPIName qspi; PinName io0; PinName io1; @@ -91,12 +94,18 @@ struct qspi_s { PinName io3; PinName sclk; PinName ssel; + bool dmaInitialized; +#if MBED_CONF_RTOS_PRESENT + osSemaphoreId_t semaphoreId; + osRtxSemaphore_t semaphoreMem; +#endif }; #endif #if DEVICE_OSPI struct ospi_s { - OSPI_HandleTypeDef handle; + XSPI_HandleTypeDef handle; + IRQn_Type ospiIRQ; OSPIName ospi; PinName io0; PinName io1; @@ -109,6 +118,11 @@ struct ospi_s { PinName sclk; PinName ssel; PinName dqs; + bool dmaInitialized; +#if MBED_CONF_RTOS_PRESENT + osSemaphoreId_t semaphoreId; + osRtxSemaphore_t semaphoreMem; +#endif }; #endif diff --git a/targets/TARGET_STM/TARGET_STM32H5/stm_dma_info.h b/targets/TARGET_STM/TARGET_STM32H5/stm_dma_info.h index 05c3aa67896..521387dfcd6 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/stm_dma_info.h +++ b/targets/TARGET_STM/TARGET_STM32H5/stm_dma_info.h @@ -33,10 +33,10 @@ static const DMALinkInfo SPITxDMALinks[] = { ,{1, 6, GPDMA1_REQUEST_SPI4_TX} #endif #if defined (SPI5) - ,{2, 0, GPDMA1_REQUEST_SPI5_TX} + ,{2, 0, GPDMA2_REQUEST_SPI5_TX} #endif #if defined (SPI6) - ,{2, 2, GPDMA1_REQUEST_SPI6_TX} + ,{2, 2, GPDMA2_REQUEST_SPI6_TX} #endif }; @@ -49,13 +49,17 @@ static const DMALinkInfo SPIRxDMALinks[] = { ,{1, 7, GPDMA1_REQUEST_SPI4_RX} #endif #if defined (SPI5) - ,{2, 1, GPDMA1_REQUEST_SPI5_RX} + ,{2, 1, GPDMA2_REQUEST_SPI5_RX} #endif #if defined (SPI6) - ,{2, 3, GPDMA1_REQUEST_SPI6_RX} + ,{2, 3, GPDMA2_REQUEST_SPI6_RX} #endif }; - +/// Mapping from OSPI index to DMA link info +static const DMALinkInfo OSPIDMALinks[] = { + {2, 4, GPDMA2_REQUEST_OCTOSPI1}, + {2, 5, GPDMA2_REQUEST_OCTOSPI1}, +}; #endif //MBED_OS_STM_DMA_INFO_H diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c index c6a4d322719..7d2d819ded6 100644 --- a/targets/TARGET_STM/qspi_api.c +++ b/targets/TARGET_STM/qspi_api.c @@ -34,6 +34,7 @@ #endif /* OCTOSPI1 */ #include "stm_dma_info.h" +#include "xspi_compat.h" // activate / de-activate extra debug #define qspi_api_c_debug 0 @@ -195,9 +196,14 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCm { debug_if(qspi_api_c_debug, "qspi_prepare_command In: instruction.value %x dummy_count %x address.bus_width %x address.disabled %x address.value %x address.size %x\n", command->instruction.value, command->dummy_count, command->address.bus_width, command->address.disabled, command->address.value, command->address.size); - +#if defined(HAL_OSPI_DUALQUAD_DISABLE) st_command->FlashId = HAL_OSPI_FLASH_ID_1; - +#endif +#if defined(QSPI_OSPIM_IOPORT_HIGH) + st_command->IOSelect = HAL_XSPI_SELECT_IO_7_4; +#else + st_command->IOSelect = HAL_XSPI_SELECT_IO_3_0; +#endif if (command->instruction.disabled == true) { st_command->InstructionMode = HAL_OSPI_INSTRUCTION_NONE; st_command->Instruction = 0; @@ -528,8 +534,21 @@ static void qspi_init_dma(struct qspi_s * obj) } #if defined(MDMA) __HAL_LINKDMA(&obj->handle, hmdma, *dmaHandle.hmdma); +#elif defined(TARGET_STM32H5) + __HAL_LINKDMA(&obj->handle, hdmarx, *dmaHandle.hdma); #else __HAL_LINKDMA(&obj->handle, hdma, *dmaHandle.hdma); +#endif +#if defined(TARGET_STM32H5) + // STM32H5 has only one OCTOSPI instance, but it requires separate DMA channels for RX and TX + DMALinkInfo const *dmaLinkTX = &OSPIDMALinks[1]; + // Initialize DMA channel + DMAHandlePointer dmaHandleTX = stm_init_dma_link(dmaLinkTX, DMA_MEMORY_TO_PERIPH, false, true, 1, 1, DMA_NORMAL); + if(dmaHandleTX.hdma == NULL) + { + mbed_error(MBED_ERROR_ALREADY_IN_USE, "DMA channel already used by something else!", 0, MBED_FILENAME, __LINE__); + } + __HAL_LINKDMA(&obj->handle, hdmatx, *dmaHandleTX.hdma); #endif obj->dmaInitialized = true; #if MBED_CONF_RTOS_PRESENT @@ -555,7 +574,10 @@ static qspi_status_t _qspi_init_direct(qspi_t *obj, const qspi_pinmap_t *pinmap, obj->handle.State = HAL_OSPI_STATE_RESET; // Set default OCTOSPI handle values +#if defined(HAL_OSPI_DUALQUAD_DISABLE) obj->handle.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE; +#endif + obj->handle.Init.MemoryMode = HAL_XSPI_SINGLE_MEM; #if defined(TARGET_MX25LM51245G) obj->handle.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX; // Read sequence in DTR mode: D1-D0-D3-D2 #else @@ -869,6 +891,10 @@ qspi_status_t qspi_free(qspi_t *obj) dmaLink = &OSPIDMALinks[0]; #endif stm_free_dma_link(dmaLink); +#if defined(STM32H5) + // Free TX DMA handle for STM32H5 + stm_free_dma_link(&OSPIDMALinks[1]); +#endif } if (HAL_OSPI_DeInit(&obj->handle) != HAL_OK) { diff --git a/targets/TARGET_STM/stm_dma_ip_v3.h b/targets/TARGET_STM/stm_dma_ip_v3.h index 9de43774ea9..94af6a4ff83 100644 --- a/targets/TARGET_STM/stm_dma_ip_v3.h +++ b/targets/TARGET_STM/stm_dma_ip_v3.h @@ -26,11 +26,20 @@ #ifndef MBED_OS_STM_DMA_IP_V3_H #define MBED_OS_STM_DMA_IP_V3_H -// Devices with DMA IP v3 have at most 16 channels per controller. +#if defined(TARGET_STM32H5) +// STM32H5 have 2 GPDMA controllers each with 8 channels +#define MAX_DMA_CHANNELS_PER_CONTROLLER 8 + +#define NUM_DMA_CONTROLLERS 2 + +#else +// Other devices with DMA IP v3 have at most 16 channels per controller. #define MAX_DMA_CHANNELS_PER_CONTROLLER 16 #define NUM_DMA_CONTROLLERS 1 +#endif + // Currently all known IPv3 devices have source selection #define STM_DEVICE_HAS_DMA_SOURCE_SELECTION 1 diff --git a/targets/TARGET_STM/stm_dma_utils.c b/targets/TARGET_STM/stm_dma_utils.c index 68a4f4f1a35..e1fde93e5a7 100644 --- a/targets/TARGET_STM/stm_dma_utils.c +++ b/targets/TARGET_STM/stm_dma_utils.c @@ -47,6 +47,11 @@ DMAInstancePointer stm_get_dma_instance(DMALinkInfo const * dmaLink) dma_instance.dma = GPDMA1; break; #endif +#ifdef GPDMA2 + case 2: + dma_instance.dma = GPDMA2; + break; +#endif #ifdef BDMA case 3: dma_instance.bdma = BDMA; @@ -325,6 +330,95 @@ DMAChannelPointer stm_get_dma_channel(const DMALinkInfo *dmaLink) } break; #endif +#ifdef GPDMA2 + case 2: + switch(dmaLink->channelIdx) + { +#ifdef GPDMA2_Channel0 + case 0: + channel_pointer.channel = GPDMA2_Channel0; + break; +#endif +#ifdef GPDMA2_Channel1 + case 1: + channel_pointer.channel = GPDMA2_Channel1; + break; +#endif +#ifdef GPDMA2_Channel2 + case 2: + channel_pointer.channel = GPDMA2_Channel2; + break; +#endif +#ifdef GPDMA2_Channel3 + case 3: + channel_pointer.channel = GPDMA2_Channel3; + break; +#endif +#ifdef GPDMA2_Channel4 + case 4: + channel_pointer.channel = GPDMA2_Channel4; + break; +#endif +#ifdef GPDMA2_Channel5 + case 5: + channel_pointer.channel = GPDMA2_Channel5; + break; +#endif +#ifdef GPDMA2_Channel6 + case 6: + channel_pointer.channel = GPDMA2_Channel6; + break; +#endif +#ifdef GPDMA2_Channel7 + case 7: + channel_pointer.channel = GPDMA2_Channel7; + break; +#endif +#ifdef GPDMA2_Channel8 + case 8: + channel_pointer.channel = GPDMA2_Channel8; + break; +#endif +#ifdef GPDMA2_Channel9 + case 9: + channel_pointer.channel = GPDMA2_Channel9; + break; +#endif +#ifdef GPDMA2_Channel10 + case 10: + channel_pointer.channel = GPDMA2_Channel10; + break; +#endif +#ifdef GPDMA2_Channel11 + case 11: + channel_pointer.channel = GPDMA2_Channel11; + break; +#endif +#ifdef GPDMA2_Channel12 + case 12: + channel_pointer.channel = GPDMA2_Channel12; + break; +#endif +#ifdef GPDMA2_Channel13 + case 13: + channel_pointer.channel = GPDMA2_Channel13; + break; +#endif +#ifdef GPDMA2_Channel14 + case 14: + channel_pointer.channel = GPDMA2_Channel14; + break; +#endif +#ifdef GPDMA2_Channel15 + case 15: + channel_pointer.channel = GPDMA2_Channel15; + break; +#endif + default: + mbed_error(MBED_ERROR_ITEM_NOT_FOUND, "Invalid DMA channel", dmaLink->channelIdx, MBED_FILENAME, __LINE__); + } + break; +#endif #ifdef BDMA case 3: switch(dmaLink->channelIdx) @@ -722,6 +816,79 @@ IRQn_Type stm_get_dma_irqn(const DMALinkInfo *dmaLink) } #endif +#ifdef GPDMA2 + case 2: + switch(dmaLink->channelIdx) + { +#ifdef GPDMA2_Channel0 + case 0: + return GPDMA2_Channel0_IRQn; +#endif +#ifdef GPDMA2_Channel1 + case 1: + return GPDMA2_Channel1_IRQn; +#endif +#ifdef GPDMA2_Channel2 + case 2: + return GPDMA2_Channel2_IRQn; +#endif +#ifdef GPDMA2_Channel3 + case 3: + return GPDMA2_Channel3_IRQn; +#endif +#ifdef GPDMA2_Channel4 + case 4: + return GPDMA2_Channel4_IRQn; +#endif +#ifdef GPDMA2_Channel5 + case 5: + return GPDMA2_Channel5_IRQn; +#endif +#ifdef GPDMA2_Channel6 + case 6: + return GPDMA2_Channel6_IRQn; +#endif +#ifdef GPDMA2_Channel7 + case 7: + return GPDMA2_Channel7_IRQn; +#endif +#ifdef GPDMA2_Channel8 + case 8: + return GPDMA2_Channel8_IRQn; +#endif +#ifdef GPDMA2_Channel9 + case 9: + return GPDMA2_Channel9_IRQn; +#endif +#ifdef GPDMA2_Channel10 + case 10: + return GPDMA2_Channel10_IRQn; +#endif +#ifdef GPDMA2_Channel11 + case 11: + return GPDMA2_Channel11_IRQn; +#endif +#ifdef GPDMA2_Channel12 + case 12: + return GPDMA2_Channel12_IRQn; +#endif +#ifdef GPDMA2_Channel13 + case 13: + return GPDMA2_Channel13_IRQn; +#endif +#ifdef GPDMA2_Channel14 + case 14: + return GPDMA2_Channel14_IRQn; +#endif +#ifdef GPDMA2_Channel15 + case 15: + return GPDMA2_Channel15_IRQn; +#endif + default: + mbed_error(MBED_ERROR_ITEM_NOT_FOUND, "Invalid DMA channel", dmaLink->channelIdx, MBED_FILENAME, __LINE__); + } +#endif + #ifdef MDMA case 4: return MDMA_IRQn; @@ -800,6 +967,11 @@ DMAHandlePointer stm_init_dma_link(const DMALinkInfo *dmaLink, uint32_t directio __HAL_RCC_GPDMA1_CLK_ENABLE(); break; #endif +#ifdef GPDMA2 + case 2: + __HAL_RCC_GPDMA2_CLK_ENABLE(); + break; +#endif #ifdef BDMA case 3: __HAL_RCC_BDMA_CLK_ENABLE(); @@ -1644,6 +1816,118 @@ void GPDMA1_Channel15_IRQHandler(void) } #endif +#ifdef GPDMA2_Channel0 +void GPDMA2_Channel0_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][0].hdma); +} +#endif + +#ifdef GPDMA2_Channel1 +void GPDMA2_Channel1_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][1].hdma); +} +#endif + +#ifdef GPDMA2_Channel2 +void GPDMA2_Channel2_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][2].hdma); +} +#endif + +#ifdef GPDMA2_Channel3 +void GPDMA2_Channel3_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][3].hdma); +} +#endif + +#ifdef GPDMA2_Channel4 +void GPDMA2_Channel4_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][4].hdma); +} +#endif + +#ifdef GPDMA2_Channel5 +void GPDMA2_Channel5_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][5].hdma); +} +#endif + +#ifdef GPDMA2_Channel6 +void GPDMA2_Channel6_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][6].hdma); +} +#endif + +#ifdef GPDMA2_Channel7 +void GPDMA2_Channel7_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][7].hdma); +} +#endif + +#ifdef GPDMA2_Channel8 +void GPDMA2_Channel8_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][8].hdma); +} +#endif + +#ifdef GPDMA2_Channel9 +void GPDMA2_Channel9_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][9].hdma); +} +#endif + +#ifdef GPDMA2_Channel10 +void GPDMA2_Channel10_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][10].hdma); +} +#endif + +#ifdef GPDMA2_Channel11 +void GPDMA2_Channel11_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][11].hdma); +} +#endif + +#ifdef GPDMA2_Channel12 +void GPDMA2_Channel12_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][12].hdma); +} +#endif + +#ifdef GPDMA2_Channel13 +void GPDMA2_Channel13_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][13].hdma); +} +#endif + +#ifdef GPDMA2_Channel14 +void GPDMA2_Channel14_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][14].hdma); +} +#endif + +#ifdef GPDMA2_Channel15 +void GPDMA2_Channel15_IRQHandler(void) +{ + HAL_DMA_IRQHandler(stmDMAHandles[1][15].hdma); +} +#endif + #endif // DMA_IP_VERSION_V3 #ifdef MDMA diff --git a/targets/TARGET_STM/xspi_compat.h b/targets/TARGET_STM/xspi_compat.h new file mode 100644 index 00000000000..4f67d21024b --- /dev/null +++ b/targets/TARGET_STM/xspi_compat.h @@ -0,0 +1,133 @@ +/* mbed Microcontroller Library +******************************************************************************* +* Copyright (c) 2018, STMicroelectronics +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* 3. Neither the name of STMicroelectronics nor the names of its contributors +* may be used to endorse or promote products derived from this software +* without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +******************************************************************************* +*/ + +#ifndef XSPI_COMAPT_H +#define XSPI_COMAPT_H + +// XSPI compatibility layer: emulate XSPI API as OSPI API + +#if defined(HAL_XSPI_MODULE_ENABLED) + +// Types +#define OSPI_HandleTypeDef XSPI_HandleTypeDef +#define OSPI_RegularCmdTypeDef XSPI_RegularCmdTypeDef + +// Members +#define ChipSelectHighTime ChipSelectHighTimeCycle +#define FifoThreshold FifoThresholdByte +#define DeviceSize MemorySize +#define InstructionSize InstructionWidth +#define AddressSize AddressWidth +#define AlternateBytesSize AlternateBytesWidth +#define NbData DataLength +#define InstructionDtrMode InstructionDTRMode +#define DataDtrMode DataDTRMode +#define AddressDtrMode AddressDTRMode +#define AlternateBytesDtrMode AlternateBytesDTRMode + +// Enumeration Values +#define HAL_OSPI_ALTERNATE_BYTES_NONE HAL_XSPI_ALT_BYTES_NONE +#define HAL_OSPI_ALTERNATE_BYTES_8_BITS HAL_XSPI_ALT_BYTES_8_BITS +#define HAL_OSPI_ALTERNATE_BYTES_16_BITS HAL_XSPI_ALT_BYTES_16_BITS +#define HAL_OSPI_ALTERNATE_BYTES_24_BITS HAL_XSPI_ALT_BYTES_24_BITS +#define HAL_OSPI_ALTERNATE_BYTES_32_BITS HAL_XSPI_ALT_BYTES_32_BITS +#define HAL_OSPI_ALTERNATE_BYTES_1_LINE HAL_XSPI_ALT_BYTES_1_LINE +#define HAL_OSPI_ALTERNATE_BYTES_2_LINES HAL_XSPI_ALT_BYTES_2_LINES +#define HAL_OSPI_ALTERNATE_BYTES_4_LINES HAL_XSPI_ALT_BYTES_4_LINES +#define HAL_OSPI_ALTERNATE_BYTES_8_LINES HAL_XSPI_ALT_BYTES_8_LINES +#define HAL_OSPI_STATE_ERROR HAL_XSPI_STATE_ERROR +#define HAL_OSPI_STATE_RESET HAL_XSPI_STATE_RESET +#define HAL_OSPI_STATE_BUSY_TX HAL_XSPI_STATE_BUSY_TX +#define HAL_OSPI_STATE_BUSY_RX HAL_XSPI_STATE_BUSY_RX +#define HAL_OSPI_STATE_READY HAL_XSPI_STATE_READY +#define HAL_OSPI_TIMEOUT_DEFAULT_VALUE HAL_XSPI_TIMEOUT_DEFAULT_VALUE +#define HAL_OSPI_INSTRUCTION_NONE HAL_XSPI_INSTRUCTION_NONE +#define HAL_OSPI_INSTRUCTION_1_LINE HAL_XSPI_INSTRUCTION_1_LINE +#define HAL_OSPI_INSTRUCTION_2_LINES HAL_XSPI_INSTRUCTION_2_LINES +#define HAL_OSPI_INSTRUCTION_4_LINES HAL_XSPI_INSTRUCTION_4_LINES +#define HAL_OSPI_INSTRUCTION_8_LINES HAL_XSPI_INSTRUCTION_8_LINES +#define HAL_OSPI_DATA_NONE HAL_XSPI_DATA_NONE +#define HAL_OSPI_DATA_1_LINE HAL_XSPI_DATA_1_LINE +#define HAL_OSPI_DATA_2_LINES HAL_XSPI_DATA_2_LINES +#define HAL_OSPI_DATA_4_LINES HAL_XSPI_DATA_4_LINES +#define HAL_OSPI_DATA_8_LINES HAL_XSPI_DATA_8_LINES +#define HAL_OSPI_INSTRUCTION_8_BITS HAL_XSPI_INSTRUCTION_8_BITS +#define HAL_OSPI_INSTRUCTION_DTR_DISABLE HAL_XSPI_INSTRUCTION_DTR_DISABLE +#define HAL_OSPI_SIOO_INST_EVERY_CMD HAL_XSPI_SIOO_INST_EVERY_CMD +#define HAL_OSPI_DATA_DTR_DISABLE HAL_XSPI_DATA_DTR_DISABLE +#define HAL_OSPI_ADDRESS_DTR_DISABLE HAL_XSPI_ADDRESS_DTR_DISABLE +#define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE HAL_XSPI_ALT_BYTES_DTR_DISABLE +#define HAL_OSPI_DQS_DISABLE HAL_XSPI_DQS_DISABLE +#define HAL_OSPI_OPTYPE_COMMON_CFG HAL_XSPI_OPTYPE_COMMON_CFG +#define HAL_OSPI_ADDRESS_NONE HAL_XSPI_ADDRESS_NONE +#define HAL_OSPI_FREERUNCLK_DISABLE HAL_XSPI_FREERUNCLK_DISABLE +#define HAL_OSPI_ADDRESS_1_LINE HAL_XSPI_ADDRESS_1_LINE +#define HAL_OSPI_ADDRESS_2_LINES HAL_XSPI_ADDRESS_2_LINES +#define HAL_OSPI_ADDRESS_4_LINES HAL_XSPI_ADDRESS_4_LINES +#define HAL_OSPI_ADDRESS_8_LINES HAL_XSPI_ADDRESS_8_LINES +#define HAL_OSPI_ADDRESS_8_BITS HAL_XSPI_ADDRESS_8_BITS +#define HAL_OSPI_ADDRESS_16_BITS HAL_XSPI_ADDRESS_16_BITS +#define HAL_OSPI_ADDRESS_24_BITS HAL_XSPI_ADDRESS_24_BITS +#define HAL_OSPI_ADDRESS_32_BITS HAL_XSPI_ADDRESS_32_BITS +#define HAL_OSPI_MEMTYPE_MACRONIX HAL_XSPI_MEMTYPE_MACRONIX +#define HAL_OSPI_MEMTYPE_MICRON HAL_XSPI_MEMTYPE_MICRON +#define HAL_OSPI_MEMTYPE_APMEM HAL_XSPI_MEMTYPE_APMEM +#define HAL_OSPI_SAMPLE_SHIFTING_NONE HAL_XSPI_SAMPLE_SHIFT_NONE +#define HAL_OSPI_CLOCK_MODE_0 HAL_XSPI_CLOCK_MODE_0 +#define HAL_OSPI_CLOCK_MODE_3 HAL_XSPI_CLOCK_MODE_3 +#define HAL_OSPI_DHQC_ENABLE HAL_XSPI_DHQC_ENABLE + +// API Functions +#define HAL_OSPI_Init HAL_XSPI_Init +#define HAL_OSPI_DeInit HAL_XSPI_DeInit +#define HAL_OSPI_Command HAL_XSPI_Command +#define HAL_OSPI_Transmit HAL_XSPI_Transmit +#define HAL_OSPI_Receive HAL_XSPI_Receive +#define HAL_OSPI_Transmit_DMA HAL_XSPI_Transmit_DMA +#define HAL_OSPI_Receive_DMA HAL_XSPI_Receive_DMA +#define HAL_OSPI_IRQHandler HAL_XSPI_IRQHandler + +// Callback Functions +#define HAL_OSPI_ErrorCallback HAL_XSPI_ErrorCallback +#define HAL_OSPI_AbortCpltCallback HAL_XSPI_AbortCpltCallback +#define HAL_OSPI_FifoThresholdCallback HAL_XSPI_FifoThresholdCallback +#define HAL_OSPI_CmdCpltCallback HAL_XSPI_CmdCpltCallback +#define HAL_OSPI_RxCpltCallback HAL_XSPI_RxCpltCallback +#define HAL_OSPI_TxCpltCallback HAL_XSPI_TxCpltCallback +#define HAL_OSPI_RxHalfCpltCallback HAL_XSPI_RxHalfCpltCallback +#define HAL_OSPI_TxHalfCpltCallback HAL_XSPI_TxHalfCpltCallback +#define HAL_OSPI_StatusMatchCallback HAL_XSPI_StatusMatchCallback +#define HAL_OSPI_TimeOutCallback HAL_XSPI_TimeOutCallback +#define HAL_OSPI_WRAP_NOT_SUPPORTED HAL_XSPI_WRAP_NOT_SUPPORTED +#define HAL_OSPI_DELAY_BLOCK_USED HAL_XSPI_DELAY_BLOCK_BYPASS + +#endif + +#endif From e921aaf320b721fa0edfe13adc5808681fed3500 Mon Sep 17 00:00:00 2001 From: wdx04 <25487439@qq.com> Date: Wed, 27 Aug 2025 17:20:17 +0800 Subject: [PATCH 02/15] add basic files for STM32H573I-DISCO(STM32H573I-DK) --- .../TARGET_STM/TARGET_STM32H5/CMakeLists.txt | 1 + .../TARGET_STM32H573xI/CMakeLists.txt | 25 + .../TARGET_DISCO_H573I/CMakeLists.txt | 16 + .../TARGET_DISCO_H573I/PeripheralPins.c | 666 +++++++++++++++++ .../TARGET_DISCO_H573I/PinNames.h | 374 ++++++++++ .../TOOLCHAIN_GCC_ARM/STM32H573xI.ld | 197 +++++ .../TOOLCHAIN_GCC_ARM/startup_stm32h573xx.S | 691 ++++++++++++++++++ .../TARGET_STM32H573xI/cmsis_nvic.h | 52 ++ targets/cmsis_mcu_descriptions.json5 | 97 +++ targets/targets.json5 | 41 ++ 10 files changed, 2160 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/PinNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/STM32H573xI.ld create mode 100644 targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/startup_stm32h573xx.S create mode 100644 targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/cmsis_nvic.h diff --git a/targets/TARGET_STM/TARGET_STM32H5/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H5/CMakeLists.txt index 382ca946e68..43280770fb0 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H5/CMakeLists.txt @@ -4,6 +4,7 @@ add_subdirectory(STM32Cube_FW EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32H503xB EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32H563xI EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32H573xI EXCLUDE_FROM_ALL) add_library(mbed-stm32h5 INTERFACE) diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/CMakeLists.txt new file mode 100644 index 00000000000..7409ab9d94c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/CMakeLists.txt @@ -0,0 +1,25 @@ +# Copyright (c) 2023 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(TARGET_DISCO_H573I EXCLUDE_FROM_ALL) + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h573xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/STM32H573xI.ld) +endif() + +add_library(mbed-stm32h573xi INTERFACE) + +target_sources(mbed-stm32h573xi + INTERFACE + ${STARTUP_FILE} +) + +target_include_directories(mbed-stm32h573xi + INTERFACE + . +) + +mbed_set_linker_script(mbed-stm32h573xi ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32h573xi INTERFACE mbed-stm32h5) diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/CMakeLists.txt new file mode 100644 index 00000000000..cc19e7aad17 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/CMakeLists.txt @@ -0,0 +1,16 @@ +# Copyright (c) 2023 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-disco-h573i INTERFACE) + +target_sources(mbed-disco-h573i + INTERFACE + PeripheralPins.c +) + +target_include_directories(mbed-disco-h573i + INTERFACE + . +) + +target_link_libraries(mbed-disco-h573i INTERFACE mbed-stm32h573xi) diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/PeripheralPins.c new file mode 100644 index 00000000000..2f0a6074ffb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/PeripheralPins.c @@ -0,0 +1,666 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2025 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32H573IIKxQ.xml + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {PF_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {NC, NC, 0} +}; + +// !!! SECTION TO BE CHECKED WITH DEVICE REFERENCE MANUAL +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { +// {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, +// {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, +// {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_12, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_6, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_5, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_7, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_11, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +// (update us_ticker_data.h file if another timer is chosen) +MBED_WEAK const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_2, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PC_2_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PC_4, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PC_5, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 1)}, // TIM8_CH4N + {PD_5, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PE_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM1, 4, 1)}, // TIM1_CH4N + {PF_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PH_6, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PH_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PH_6_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PH_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PH_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PH_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PH_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PH_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_9_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PH_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PH_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PH_10_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PH_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 +// {PH_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PH_11_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PH_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_12, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_TIM8, 4, 1)}, // TIM8_CH4N + {PH_13, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, UART_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_9_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_15, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_3, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_10, UART_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_2, UART_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_3, UART_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_1, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_3, UART_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_12, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_13, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PH_13_ALT0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART8)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_7, UART_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_15_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_14, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART10)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PE_9, UART_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_4, UART_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_5, UART_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_0, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_2, UART_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_11, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PH_14, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PI_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_1, UART_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_5, UART_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_11, UART_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_14, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART1)}, + {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_3, UART_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART12)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_15_ALT0, UART_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_0, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART12)}, + {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_5, UART_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART11)}, + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_13_ALT0, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART10)}, + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_7_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, + {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, + {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PH_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_6_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_9, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PH_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_5_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_3_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PC_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PH_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PA_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI6)}, + {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PG_10, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PH_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PH_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_9, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PE_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_14, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PI_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PI_10, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_10, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_7, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_5, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PE_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { + {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { + {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { + {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { + {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS + {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NC, 0} +}; + +//*** OCTOSPI *** + +MBED_WEAK const PinMap PinMap_OSPI_DATA0[] = { + {PB_1, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_3, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PC_9, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PD_11, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO0 + {PF_8, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA1[] = { + {PB_0, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO1 + {PC_10, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PD_12, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO1 + {PF_9, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA2[] = { + {PA_7, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {PC_2, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PE_2, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO2 + {PF_7, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA3[] = { + {PA_1, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PA_6, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO3 + {PD_13, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO3 + {PF_6, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA4[] = { + {PC_1, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PD_4, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PE_7, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {PH_2, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA5[] = { + {PC_2, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO5 + {PC_6, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO5 + {PD_5, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PE_8, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {PH_3, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA6[] = { + {PC_3, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_IO6 + {PC_7, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPI1)}, // OCTOSPI1_IO6 + {PD_6, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PE_9, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {PG_9, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA7[] = { + {PC_0, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PD_7, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PE_10, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO7 + {PG_14, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DQS[] = { + {PA_1, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_DQS + {PB_2, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_DQS + {PC_5, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_DQS + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_SCLK[] = { + {PA_3, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_2, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_4, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_CLK + {PB_15, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {PF_10, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_SSEL[] = { + {PB_6, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {PB_10, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PC_11, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPI1)}, // OCTOSPI1_NCS + {PE_11, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPI1)}, // OCTOSPI1_NCS + {PG_6, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_FS[] = { +// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB)}, // USB_SOF + {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/PinNames.h b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/PinNames.h new file mode 100644 index 00000000000..d74fc02d078 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/PinNames.h @@ -0,0 +1,374 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2025 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32H573IIKxQ.xml + */ + +/* MBED TARGET LIST: */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_0_ALT0 = PA_0 | ALT0, // same pin used for alternate HW + PA_1 = 0x01, + PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW + PA_4_ALT1 = PA_4 | ALT1, // same pin used for alternate HW + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, // same pin used for alternate HW + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW + PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW + PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW + PA_8 = 0x08, + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, // same pin used for alternate HW + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, // same pin used for alternate HW + PA_11 = 0x0B, + PA_11_ALT0 = PA_11 | ALT0, // same pin used for alternate HW + PA_12 = 0x0C, + PA_12_ALT0 = PA_12 | ALT0, // same pin used for alternate HW + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW + PA_15_ALT1 = PA_15 | ALT1, // same pin used for alternate HW + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW + PB_0_ALT1 = PB_0 | ALT1, // same pin used for alternate HW + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW + PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW + PB_3_ALT1 = PB_3 | ALT1, // same pin used for alternate HW + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW + PB_4_ALT1 = PB_4 | ALT1, // same pin used for alternate HW + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW + PB_5_ALT1 = PB_5 | ALT1, // same pin used for alternate HW + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW + PB_6_ALT1 = PB_6 | ALT1, // same pin used for alternate HW + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, // same pin used for alternate HW + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW + PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW + PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW + PC_2 = 0x22, + PC_2_ALT0 = PC_2 | ALT0, // same pin used for alternate HW + PC_3 = 0x23, + PC_3_ALT0 = PC_3 | ALT0, // same pin used for alternate HW + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, // same pin used for alternate HW + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, // same pin used for alternate HW + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_5 = 0x55, + PF_6 = 0x56, + PF_7 = 0x57, + PF_8 = 0x58, + PF_8_ALT0 = PF_8 | ALT0, // same pin used for alternate HW + PF_9 = 0x59, + PF_9_ALT0 = PF_9 | ALT0, // same pin used for alternate HW + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_15 = 0x5F, + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_13_ALT0 = PG_13 | ALT0, // same pin used for alternate HW + PG_14 = 0x6E, + PG_15 = 0x6F, + PH_0 = 0x70, + PH_1 = 0x71, + PH_2 = 0x72, + PH_3 = 0x73, + PH_4 = 0x74, + PH_5 = 0x75, + PH_6 = 0x76, + PH_6_ALT0 = PH_6 | ALT0, // same pin used for alternate HW + PH_6_ALT1 = PH_6 | ALT1, // same pin used for alternate HW + PH_7 = 0x77, + PH_7_ALT0 = PH_7 | ALT0, // same pin used for alternate HW + PH_8 = 0x78, + PH_8_ALT0 = PH_8 | ALT0, // same pin used for alternate HW + PH_9 = 0x79, + PH_9_ALT0 = PH_9 | ALT0, // same pin used for alternate HW + PH_9_ALT1 = PH_9 | ALT1, // same pin used for alternate HW + PH_10 = 0x7A, + PH_10_ALT0 = PH_10 | ALT0, // same pin used for alternate HW + PH_11 = 0x7B, + PH_11_ALT0 = PH_11 | ALT0, // same pin used for alternate HW + PH_12 = 0x7C, + PH_13 = 0x7D, + PH_13_ALT0 = PH_13 | ALT0, // same pin used for alternate HW + PH_14 = 0x7E, + PH_15 = 0x7F, + PI_1 = 0x81, + PI_2 = 0x82, + PI_3 = 0x83, + PI_4 = 0x84, + PI_5 = 0x85, + PI_6 = 0x86, + PI_7 = 0x87, + PI_8 = 0x88, + PI_9 = 0x89, + PI_10 = 0x8A, + PI_11 = 0x8B, + + /**** ADC internal channels ****/ + + ADC_TEMP = 0xF0, // Internal pin virtual value + ADC_VREF = 0xF1, // Internal pin virtual value + ADC_VBAT = 0xF2, // Internal pin virtual value + +#ifdef TARGET_FF_ARDUINO_UNO + // Arduino Uno (Rev3) pins + ARDUINO_UNO_A0 = PB_0, + ARDUINO_UNO_A1 = PA_4, + ARDUINO_UNO_A2 = PA_0, + ARDUINO_UNO_A3 = PA_5, + ARDUINO_UNO_A4 = PA_6, + ARDUINO_UNO_A5 = PF_12, + + ARDUINO_UNO_D0 = PB_11, + ARDUINO_UNO_D1 = PB_10, + ARDUINO_UNO_D2 = PG_15, + ARDUINO_UNO_D3 = PB_5, + ARDUINO_UNO_D4 = PG_4, + ARDUINO_UNO_D5 = PH_11, + ARDUINO_UNO_D6 = PH_10, + ARDUINO_UNO_D7 = PG_5, + ARDUINO_UNO_D8 = PG_8, + ARDUINO_UNO_D9 = PA_8, + ARDUINO_UNO_D10 = PA_3, + ARDUINO_UNO_D11 = PB_15, + ARDUINO_UNO_D12 = PI_2, + ARDUINO_UNO_D13 = PI_1, + ARDUINO_UNO_D14 = PB_7, + ARDUINO_UNO_D15 = PB_6, +#endif + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + CONSOLE_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + CONSOLE_RX = PA_10, +#endif + + /**** USB pins ****/ + USB_DM = PA_11, + USB_DP = PA_12, + USB_SOF = PA_8, + + /**** ETHERNET pins ****/ + ETH_COL = PA_3, + ETH_COL_ALT0 = PH_3, + ETH_CRS = PA_0, + ETH_CRS_ALT0 = PH_2, + ETH_CRS_DV = PA_7, + ETH_MDC = PC_1, + ETH_MDIO = PA_2, + ETH_PPS_OUT = PB_5, + ETH_PPS_OUT_ALT0 = PG_8, + ETH_REF_CLK = PA_1, + ETH_RXD0 = PC_4, + ETH_RXD1 = PC_5, + ETH_RXD2 = PH_6, + ETH_RXD2_ALT0 = PB_0, + ETH_RXD3 = PB_1, + ETH_RXD3_ALT0 = PH_7, + ETH_RX_CLK = PA_1, + ETH_RX_DV = PA_7, + ETH_RX_ER = PI_10, + ETH_RX_ER_ALT0 = PB_10, + ETH_TXD0 = PG_13, + ETH_TXD0_ALT0 = PC_10, + ETH_TXD0_ALT1 = PB_12, + ETH_TXD1 = PG_14, + ETH_TXD1_ALT0 = PG_12, + ETH_TXD1_ALT1 = PB_15, + ETH_TXD2 = PC_2, + ETH_TXD3 = PB_8, + ETH_TXD3_ALT0 = PE_2, + ETH_TX_CLK = PC_3, + ETH_TX_EN = PG_11, + ETH_TX_EN_ALT0 = PB_11, + ETH_TX_EN_ALT1 = PA_5, + ETH_TX_ER = PA_9, + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_IN = PH_0, + RCC_OSC_OUT = PH_1, + + /**** DEBUG pins ****/ + DEBUG_JTCK_SWCLK = PA_14, + DEBUG_JTDI = PA_15, + DEBUG_JTDO_SWO = PB_3, + DEBUG_JTMS_SWDIO = PA_13, + DEBUG_NJTRST = PB_4, + DEBUG_TRACECLK = PE_2, + DEBUG_TRACED0 = PE_3, + DEBUG_TRACED0_ALT0 = PG_13, + DEBUG_TRACED0_ALT1 = PC_1, + DEBUG_TRACED1 = PG_14, + DEBUG_TRACED1_ALT0 = PE_4, + DEBUG_TRACED1_ALT1 = PC_8, + DEBUG_TRACED2 = PD_2, + DEBUG_TRACED2_ALT0 = PE_5, + DEBUG_TRACED3 = PE_6, + DEBUG_TRACED3_ALT0 = PC_12, + DEBUG_TRGIO = PC_7, + PWR_CSLEEP = PC_2, + PWR_CSTOP = PC_3, + PWR_PVD_IN = PB_15, + SYS_PWR_WKUP1 = PA_0, + SYS_PWR_WKUP2 = PA_2, + SYS_PWR_WKUP3 = PI_8, + SYS_PWR_WKUP4 = PC_13, + SYS_PWR_WKUP5 = PB_7, + SYS_PWR_WKUP6 = PC_1, + SYS_PWR_WKUP7 = PD_2, + SYS_PWR_WKUP8 = PD_3, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +// Standardized LED and button names +#define LED1 PI_9 +#define LED2 PI_8 +#define LED3 PF_1 +#define LED4 PF_4 +#define BUTTON1 PC_13 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/STM32H573xI.ld b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/STM32H573xI.ld new file mode 100644 index 00000000000..0418ceaba8a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/STM32H573xI.ld @@ -0,0 +1,197 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H573ZITx Device from STM32H5 series +** 2Mbytes FLASH +** 640Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +M_CRASH_DATA_RAM_SIZE = 0x100; + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = (MBED_RAM_START + VECTORS_SIZE), LENGTH = (MBED_RAM_SIZE - VECTORS_SIZE) + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE +} + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Sections */ +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .crash_data_ram : + { + . = ALIGN(8); + __CRASH_DATA_RAM__ = .; + __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ + KEEP(*(.keep.crash_data_ram)) + *(.m_crash_data_ram) /* This is a user defined section */ + . += M_CRASH_DATA_RAM_SIZE; + . = ALIGN(8); + __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ + } > RAM + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/startup_stm32h573xx.S b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/startup_stm32h573xx.S new file mode 100644 index 00000000000..2e2443b28f9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/startup_stm32h573xx.S @@ -0,0 +1,691 @@ +/** + ****************************************************************************** + * @file startup_stm32h573xx.s + * @author MCD Application Team + * @brief STM32H573xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None + */ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl _start + bx lr + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32H573xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_AVD_IRQHandler + .word RTC_IRQHandler + .word RTC_S_IRQHandler + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word FLASH_S_IRQHandler + .word GTZC_IRQHandler + .word RCC_IRQHandler + .word RCC_S_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word IWDG_IRQHandler + .word 0 + .word ADC1_IRQHandler + .word DAC1_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word TIM5_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word SPI3_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC2_IRQHandler + .word LPTIM2_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word USB_DRD_FS_IRQHandler + .word CRS_IRQHandler + .word UCPD1_IRQHandler + .word FMC_IRQHandler + .word OCTOSPI1_IRQHandler + .word SDMMC1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SPI4_IRQHandler + .word SPI5_IRQHandler + .word SPI6_IRQHandler + .word USART6_IRQHandler + .word USART10_IRQHandler + .word USART11_IRQHandler + .word SAI1_IRQHandler + .word SAI2_IRQHandler + .word GPDMA2_Channel0_IRQHandler + .word GPDMA2_Channel1_IRQHandler + .word GPDMA2_Channel2_IRQHandler + .word GPDMA2_Channel3_IRQHandler + .word GPDMA2_Channel4_IRQHandler + .word GPDMA2_Channel5_IRQHandler + .word GPDMA2_Channel6_IRQHandler + .word GPDMA2_Channel7_IRQHandler + .word UART7_IRQHandler + .word UART8_IRQHandler + .word UART9_IRQHandler + .word UART12_IRQHandler + .word SDMMC2_IRQHandler + .word FPU_IRQHandler + .word ICACHE_IRQHandler + .word DCACHE1_IRQHandler + .word ETH_IRQHandler + .word ETH_WKUP_IRQHandler + .word DCMI_PSSI_IRQHandler + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word CORDIC_IRQHandler + .word FMAC_IRQHandler + .word DTS_IRQHandler + .word RNG_IRQHandler + .word 0 + .word 0 + .word HASH_IRQHandler + .word 0 + .word CEC_IRQHandler + .word TIM12_IRQHandler + .word TIM13_IRQHandler + .word TIM14_IRQHandler + .word I3C1_EV_IRQHandler + .word I3C1_ER_IRQHandler + .word I2C4_EV_IRQHandler + .word I2C4_ER_IRQHandler + .word LPTIM3_IRQHandler + .word LPTIM4_IRQHandler + .word LPTIM5_IRQHandler + .word LPTIM6_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak FLASH_S_IRQHandler + .thumb_set FLASH_S_IRQHandler,Default_Handler + + .weak GTZC_IRQHandler + .thumb_set GTZC_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak DAC1_IRQHandler + .thumb_set DAC1_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak USB_DRD_FS_IRQHandler + .thumb_set USB_DRD_FS_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak USART10_IRQHandler + .thumb_set USART10_IRQHandler,Default_Handler + + .weak USART11_IRQHandler + .thumb_set USART11_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak GPDMA2_Channel0_IRQHandler + .thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler + + .weak GPDMA2_Channel1_IRQHandler + .thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler + + .weak GPDMA2_Channel2_IRQHandler + .thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler + + .weak GPDMA2_Channel3_IRQHandler + .thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler + + .weak GPDMA2_Channel4_IRQHandler + .thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler + + .weak GPDMA2_Channel5_IRQHandler + .thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler + + .weak GPDMA2_Channel6_IRQHandler + .thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler + + .weak GPDMA2_Channel7_IRQHandler + .thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak UART12_IRQHandler + .thumb_set UART12_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak DCACHE1_IRQHandler + .thumb_set DCACHE1_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak LPTIM6_IRQHandler + .thumb_set LPTIM6_IRQHandler,Default_Handler diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/cmsis_nvic.h new file mode 100644 index 00000000000..cca89047222 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/cmsis_nvic.h @@ -0,0 +1,52 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(TRUST_ZONE) +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif +#else +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0xC000000 +#endif +#endif //TRUST_ZONE + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x200000 // 2.0 MB +#endif + +#if !defined(TRUST_ZONE) +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif +#else +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x30000000 +#endif +#endif //TRUST_ZONE + +#if !defined(MBED_RAM_SIZE) +//256K SRAM1 + 64K SRAM2 + 320K SRAM3 = 640KB +#define MBED_RAM_SIZE 0xA0000 +#endif + +#define NVIC_NUM_VECTORS 147 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/cmsis_mcu_descriptions.json5 b/targets/cmsis_mcu_descriptions.json5 index 621a3c0d457..25e998d3ca3 100644 --- a/targets/cmsis_mcu_descriptions.json5 +++ b/targets/cmsis_mcu_descriptions.json5 @@ -7974,6 +7974,103 @@ "sub_family": "STM32H563", "vendor": "STMicroelectronics:13" }, + "STM32H573IIKxQ": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32H5xx_2M_0800.FLM", + "ram_size": 32768, + "ram_start": 536870912, + "size": 2097152, + "start": 134217728, + "style": "Keil" + }, + { + "default": true, + "file_name": "CMSIS/Flash/STM32H5xx_2M_0C00.FLM", + "ram_size": 32768, + "ram_start": 536870912, + "size": 2097152, + "start": 201326592, + "style": "Keil" + } + ], + "family": "STM32H5 Series", + "from_pack": { + "pack": "STM32H5xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "2.0.0" + }, + "memories": { + "Flash": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "p_name": null, + "size": 2097152, + "start": 134217728, + "startup": true + }, + "SRAM1_2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "p_name": null, + "size": 327680, + "start": 536870912, + "startup": false + }, + "SRAM3": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "p_name": null, + "size": 327680, + "start": 537198592, + "startup": false + } + }, + "name": "STM32H573IIKxQ", + "processors": [ + { + "address": null, + "ap": 1, + "apid": null, + "core": "CortexM33", + "default_reset_sequence": null, + "dp": 0, + "fpu": "SinglePrecision", + "mpu": "Present", + "name": null, + "svd": "CMSIS/SVD/STM32H573.svd", + "unit": 0 + } + ], + "sub_family": "STM32H573", + "vendor": "STMicroelectronics:13" + }, "STM32H723ZGTx": { "algorithms": [ { diff --git a/targets/targets.json5 b/targets/targets.json5 index 20c795df20f..423fac3dad6 100644 --- a/targets/targets.json5 +++ b/targets/targets.json5 @@ -3212,6 +3212,47 @@ mode is recommended for target MCUs with small amounts of flash and RAM.", "device_name": "STM32H563ZITx", "image_url": "https://www.st.com/bin/ecommerce/api/image.PF274337.en.feature-description-include-personalized-no-cpn-medium.jpg" }, + "MCU_STM32H573xI": { + "inherits": [ + "MCU_STM32H5" + ], + "public": false, + "core": "Cortex-M33", + "extra_labels_add": [ + "STM32H573xI" + ], + "macros_add": [ + "STM32H573xx" + ], + "overrides": { + "network-default-interface-type": "ETHERNET" + }, + "device_has_add": [ + "EMAC" + ] + }, + "DISCO_H573I": { + "inherits": [ + "MCU_STM32H573xI" + ], + "overrides": { + "hse_value": 25000000, + "lse_available": 1, + "clock_source": "USE_PLL_HSE_XTAL|USE_PLL_HSI", + + // ADC reference voltage is same as MCU VDD. + // MCU VDD defaults to 3.3V though can be changed to 1.8V based on JP2 setting. + "default-adc-vref": 3.3 + }, + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "detect_code": [ + "0831" + ], + "device_name": "STM32H573IIKxQ", + "image_url": "https://www.st.com/bin/ecommerce/api/image.PF272542.en.feature-description-include-personalized-no-cpn-large.jpg" + }, // STM32H7 Targets ------------------------------------------------------------------------------------------------- "MCU_STM32H7": { From 2c10c8ef06c6e7eac7d729f6d64a8390cda2abe9 Mon Sep 17 00:00:00 2001 From: wdx04 <25487439@qq.com> Date: Thu, 28 Aug 2025 09:14:01 +0800 Subject: [PATCH 03/15] add USB support for STM32H563/STM32H573 --- targets/TARGET_STM/TARGET_STM32H5/clock_cfg/system_clock.c | 6 ++++++ targets/TARGET_STM/USBPhyHw.h | 2 +- targets/TARGET_STM/USBPhy_STM32.cpp | 2 +- targets/targets.json5 | 6 ++++-- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H5/clock_cfg/system_clock.c b/targets/TARGET_STM/TARGET_STM32H5/clock_cfg/system_clock.c index 39d664ce182..db57b01b4d6 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/clock_cfg/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32H5/clock_cfg/system_clock.c @@ -159,6 +159,9 @@ else // Divisible by 5MHz if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { return 0; // FAIL } + + /* Enable VDDUSB */ + HAL_PWREx_EnableVddUSB(); #endif /* DEVICE_USBDEVICE */ return 1; // OK @@ -229,6 +232,9 @@ uint8_t SetSysClock_PLL_HSI(void) if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { return 0; // FAIL } + + /* Enable VDDUSB */ + HAL_PWREx_EnableVddUSB(); #endif /* DEVICE_USBDEVICE */ return 1; // OK diff --git a/targets/TARGET_STM/USBPhyHw.h b/targets/TARGET_STM/USBPhyHw.h index 33e48f7f84a..fe0d6fd4e7c 100644 --- a/targets/TARGET_STM/USBPhyHw.h +++ b/targets/TARGET_STM/USBPhyHw.h @@ -49,7 +49,7 @@ #define USBHAL_IRQn USB_LP_CAN_RX0_IRQn #elif defined(TARGET_STM32L5) #define USBHAL_IRQn USB_FS_IRQn -#elif defined(TARGET_STM32U0) +#elif defined(TARGET_STM32U0) || defined(TARGET_STM32H5) #define USBHAL_IRQn USB_DRD_FS_IRQn #else #define USBHAL_IRQn USB_IRQn diff --git a/targets/TARGET_STM/USBPhy_STM32.cpp b/targets/TARGET_STM/USBPhy_STM32.cpp index 4c6d1283562..d183f6924c0 100644 --- a/targets/TARGET_STM/USBPhy_STM32.cpp +++ b/targets/TARGET_STM/USBPhy_STM32.cpp @@ -335,7 +335,7 @@ void USBPhyHw::init(USBPhyEvents *events) __HAL_RCC_PWR_CLK_ENABLE(); #endif -#if !defined(TARGET_STM32WB) +#if !defined(TARGET_STM32WB) && !defined(TARGET_STM32H5) __HAL_RCC_SYSCFG_CLK_ENABLE(); #endif diff --git a/targets/targets.json5 b/targets/targets.json5 index 423fac3dad6..e9fd2386617 100644 --- a/targets/targets.json5 +++ b/targets/targets.json5 @@ -3188,7 +3188,8 @@ mode is recommended for target MCUs with small amounts of flash and RAM.", "network-default-interface-type": "ETHERNET" }, "device_has_add": [ - "EMAC" + "EMAC", + "USBDEVICE" ] }, "NUCLEO_H563ZI": { @@ -3228,7 +3229,8 @@ mode is recommended for target MCUs with small amounts of flash and RAM.", "network-default-interface-type": "ETHERNET" }, "device_has_add": [ - "EMAC" + "EMAC", + "USBDEVICE" ] }, "DISCO_H573I": { From fa647b20e957434b37a559ee4a27397cb945c3ee Mon Sep 17 00:00:00 2001 From: wdx04 <25487439@qq.com> Date: Thu, 28 Aug 2025 10:55:10 +0800 Subject: [PATCH 04/15] add STMOD and PMOD pins add OCTOSPI Flash (to be tested) --- .../TARGET_DISCO_H573I/PinNames.h | 57 +++++++++++++++++++ .../TOOLCHAIN_GCC_ARM/startup_stm32h573xx.S | 20 +++++-- targets/TARGET_STM/ospi_api.c | 24 ++++++-- targets/TARGET_STM/qspi_api.c | 4 ++ targets/TARGET_STM/xspi_compat.h | 7 +++ targets/targets.json5 | 14 ++++- 6 files changed, 115 insertions(+), 11 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/PinNames.h b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/PinNames.h index d74fc02d078..017f08c2f94 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TARGET_DISCO_H573I/PinNames.h @@ -356,6 +356,63 @@ typedef enum { SYS_PWR_WKUP7 = PD_2, SYS_PWR_WKUP8 = PD_3, + /**** STMOD+ pins ****/ + STMOD_1 = PF_6, + STMOD_2 = PF_9, + STMOD_3 = PF_8, + STMOD_4 = PF_7, +// STMOD_5 is connected to GND +// STMOD_6 is connected to +5V + STMOD_7 = PB_6, + STMOD_8 = PH_8, + STMOD_9 = PH_7, + STMOD_10 = PB_7, + STMOD_11 = PH_9, + STMOD_12 = PH_6, + STMOD_13 = PF_11, + STMOD_14 = PH_12, +// STMOD_15 is connected to +5V +// STMOD_16 is connected to GND + STMOD_17 = PF_3, + STMOD_18 = PB_12, + STMOD_19 = PH_4, + STMOD_20 = PH_5, + + /**** PMOD pins ****/ + PMOD_1 = STMOD_1, + PMOD_2 = STMOD_2, + PMOD_3 = STMOD_3, + PMOD_4 = STMOD_4, +// PMOD_5 is connected to GND +// PMOD_6 is connected to +3V3 + PMOD_7 = STMOD_11, + PMOD_8 = STMOD_12, +// PMOD_9 is not connected +// PMOD_10 is not connected +// PMOD_11 is connected to GND +// PMOD_12 is connected to +3V3 + + /**** OSPI FLASH pins ****/ + OSPI_FLASH1_IO0 = PB_1, + OSPI_FLASH1_IO1 = PD_12, + OSPI_FLASH1_IO2 = PC_2, + OSPI_FLASH1_IO3 = PD_13, + OSPI_FLASH1_IO4 = PH_2, + OSPI_FLASH1_IO5 = PH_3, + OSPI_FLASH1_IO6 = PG_9, + OSPI_FLASH1_IO7 = PC_0, + OSPI_FLASH1_DQS = PB_2, + OSPI_FLASH1_SCK = PF_10, + OSPI_FLASH1_CSN = PG_6, + + /**** QSPI FLASH pins ****/ + QSPI_FLASH1_IO0 = OSPI_FLASH1_IO0, + QSPI_FLASH1_IO1 = OSPI_FLASH1_IO1, + QSPI_FLASH1_IO2 = OSPI_FLASH1_IO2, + QSPI_FLASH1_IO3 = OSPI_FLASH1_IO3, + QSPI_FLASH1_SCK = OSPI_FLASH1_SCK, + QSPI_FLASH1_CSN = OSPI_FLASH1_CSN, + // Not connected NC = (int)0xFFFFFFFF } PinName; diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/startup_stm32h573xx.S b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/startup_stm32h573xx.S index 2e2443b28f9..3ca6d2c8a39 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/startup_stm32h573xx.S +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/startup_stm32h573xx.S @@ -175,7 +175,7 @@ g_pfnVectors: .word GPDMA1_Channel6_IRQHandler .word GPDMA1_Channel7_IRQHandler .word IWDG_IRQHandler - .word 0 + .word SAES_IRQHandler .word ADC1_IRQHandler .word DAC1_IRQHandler .word FDCAN1_IT0_IRQHandler @@ -254,10 +254,10 @@ g_pfnVectors: .word FMAC_IRQHandler .word DTS_IRQHandler .word RNG_IRQHandler - .word 0 - .word 0 + .word OTFDEC1_IRQHandler + .word AES_IRQHandler .word HASH_IRQHandler - .word 0 + .word PKA_IRQHandler .word CEC_IRQHandler .word TIM12_IRQHandler .word TIM13_IRQHandler @@ -417,6 +417,9 @@ g_pfnVectors: .weak IWDG_IRQHandler .thumb_set IWDG_IRQHandler,Default_Handler + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + .weak ADC1_IRQHandler .thumb_set ADC1_IRQHandler,Default_Handler @@ -651,9 +654,18 @@ g_pfnVectors: .weak RNG_IRQHandler .thumb_set RNG_IRQHandler,Default_Handler + .weak OTFDEC1_IRQHandler + .thumb_set OTFDEC1_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + .weak HASH_IRQHandler .thumb_set HASH_IRQHandler,Default_Handler + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + .weak CEC_IRQHandler .thumb_set CEC_IRQHandler,Default_Handler diff --git a/targets/TARGET_STM/ospi_api.c b/targets/TARGET_STM/ospi_api.c index 1b0e8863bc0..a82185929c6 100644 --- a/targets/TARGET_STM/ospi_api.c +++ b/targets/TARGET_STM/ospi_api.c @@ -29,6 +29,9 @@ #define TRACE_GROUP "STOS" +#include "stm_dma_info.h" +#include "xspi_compat.h" + // activate / de-activate debug #define ospi_api_c_debug 0 @@ -58,8 +61,12 @@ ospi_status_t ospi_prepare_command(const ospi_command_t *command, OSPI_RegularCm debug_if(ospi_api_c_debug, "ospi_prepare_command In: instruction.value %x dummy_count %u address.bus_width %x address.disabled %x address.value %x address.size %x\n", command->instruction.value, command->dummy_count, command->address.bus_width, command->address.disabled, command->address.value, command->address.size); +#if defined(HAL_OSPI_DUALQUAD_DISABLE) st_command->FlashId = HAL_OSPI_FLASH_ID_1; - +#endif +#if defined(HAL_XSPI_MODULE_ENABLED) + st_command->IOSelect = HAL_XSPI_SELECT_IO_7_0; +#endif if (command->instruction.disabled == true) { st_command->InstructionMode = HAL_OSPI_INSTRUCTION_NONE; st_command->Instruction = 0; @@ -243,12 +250,17 @@ static ospi_status_t _ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap, obj->handle.State = HAL_OSPI_STATE_RESET; // Set default OCTOSPI handle values +#if defined(HAL_OSPI_DUALQUAD_DISABLE) obj->handle.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE; -//#if defined(TARGET_MX25LM512451G) -// obj->handle.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX; // Read sequence in DTR mode: D1-D0-D3-D2 -//#else +#endif +#if defined(HAL_XSPI_MODULE_ENABLED) + obj->handle.Init.MemoryMode = HAL_XSPI_SINGLE_MEM; +#endif +#if defined(TARGET_MX25LM51245G) + obj->handle.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX; // Read sequence in DTR mode: D1-D0-D3-D2 +#else obj->handle.Init.MemoryType = HAL_OSPI_MEMTYPE_MICRON; // Read sequence in DTR mode: D0-D1-D2-D3 -//#endif +#endif obj->handle.Init.ClockPrescaler = 4; // default value, will be overwritten in ospi_frequency obj->handle.Init.FifoThreshold = 4; obj->handle.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE; @@ -264,7 +276,7 @@ static ospi_status_t _ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap, #if defined(HAL_OSPI_DELAY_BLOCK_USED) obj->handle.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_USED; #endif -#if defined(TARGET_STM32L5) || defined(TARGET_STM32U5) +#if defined(TARGET_STM32L5) || defined(TARGET_STM32U5) || defined(TARGET_STM32H5) obj->handle.Init.Refresh = 0; #endif #if defined(OCTOSPI_DCR3_MAXTRAN) diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c index 7d2d819ded6..177113feff9 100644 --- a/targets/TARGET_STM/qspi_api.c +++ b/targets/TARGET_STM/qspi_api.c @@ -199,10 +199,12 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCm #if defined(HAL_OSPI_DUALQUAD_DISABLE) st_command->FlashId = HAL_OSPI_FLASH_ID_1; #endif +#if defined(HAL_XSPI_MODULE_ENABLED) #if defined(QSPI_OSPIM_IOPORT_HIGH) st_command->IOSelect = HAL_XSPI_SELECT_IO_7_4; #else st_command->IOSelect = HAL_XSPI_SELECT_IO_3_0; +#endif #endif if (command->instruction.disabled == true) { st_command->InstructionMode = HAL_OSPI_INSTRUCTION_NONE; @@ -577,7 +579,9 @@ static qspi_status_t _qspi_init_direct(qspi_t *obj, const qspi_pinmap_t *pinmap, #if defined(HAL_OSPI_DUALQUAD_DISABLE) obj->handle.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE; #endif +#if defined(HAL_XSPI_MODULE_ENABLED) obj->handle.Init.MemoryMode = HAL_XSPI_SINGLE_MEM; +#endif #if defined(TARGET_MX25LM51245G) obj->handle.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX; // Read sequence in DTR mode: D1-D0-D3-D2 #else diff --git a/targets/TARGET_STM/xspi_compat.h b/targets/TARGET_STM/xspi_compat.h index 4f67d21024b..cbcd53e614e 100644 --- a/targets/TARGET_STM/xspi_compat.h +++ b/targets/TARGET_STM/xspi_compat.h @@ -79,14 +79,21 @@ #define HAL_OSPI_DATA_4_LINES HAL_XSPI_DATA_4_LINES #define HAL_OSPI_DATA_8_LINES HAL_XSPI_DATA_8_LINES #define HAL_OSPI_INSTRUCTION_8_BITS HAL_XSPI_INSTRUCTION_8_BITS +#define HAL_OSPI_INSTRUCTION_16_BITS HAL_XSPI_INSTRUCTION_16_BITS +#define HAL_OSPI_INSTRUCTION_DTR_ENABLE HAL_XSPI_INSTRUCTION_DTR_ENABLE #define HAL_OSPI_INSTRUCTION_DTR_DISABLE HAL_XSPI_INSTRUCTION_DTR_DISABLE #define HAL_OSPI_SIOO_INST_EVERY_CMD HAL_XSPI_SIOO_INST_EVERY_CMD +#define HAL_OSPI_DATA_DTR_ENABLE HAL_XSPI_DATA_DTR_ENABLE #define HAL_OSPI_DATA_DTR_DISABLE HAL_XSPI_DATA_DTR_DISABLE +#define HAL_OSPI_ADDRESS_DTR_ENABLE HAL_XSPI_ADDRESS_DTR_ENABLE #define HAL_OSPI_ADDRESS_DTR_DISABLE HAL_XSPI_ADDRESS_DTR_DISABLE +#define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE HAL_XSPI_ALT_BYTES_DTR_ENABLE #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE HAL_XSPI_ALT_BYTES_DTR_DISABLE +#define HAL_OSPI_DQS_ENABLE HAL_XSPI_DQS_ENABLE #define HAL_OSPI_DQS_DISABLE HAL_XSPI_DQS_DISABLE #define HAL_OSPI_OPTYPE_COMMON_CFG HAL_XSPI_OPTYPE_COMMON_CFG #define HAL_OSPI_ADDRESS_NONE HAL_XSPI_ADDRESS_NONE +#define HAL_OSPI_FREERUNCLK_ENABLE HAL_XSPI_FREERUNCLK_ENABLE #define HAL_OSPI_FREERUNCLK_DISABLE HAL_XSPI_FREERUNCLK_DISABLE #define HAL_OSPI_ADDRESS_1_LINE HAL_XSPI_ADDRESS_1_LINE #define HAL_OSPI_ADDRESS_2_LINES HAL_XSPI_ADDRESS_2_LINES diff --git a/targets/targets.json5 b/targets/targets.json5 index e9fd2386617..079619bd819 100644 --- a/targets/targets.json5 +++ b/targets/targets.json5 @@ -3247,11 +3247,23 @@ mode is recommended for target MCUs with small amounts of flash and RAM.", "default-adc-vref": 3.3 }, "supported_form_factors": [ - "ARDUINO_UNO" + "ARDUINO_UNO", + "STMOD", + "PMOD" + ], + "components_add": [ + "OSPIF" + ], + "extra_labels_add": [ + "MX25LM51245G" ], "detect_code": [ "0831" ], + "device_has_add": [ + "QSPI", + "OSPI" + ], "device_name": "STM32H573IIKxQ", "image_url": "https://www.st.com/bin/ecommerce/api/image.PF272542.en.feature-description-include-personalized-no-cpn-large.jpg" }, From b826f0b87ce172b42798351e6da3c4cd1a1a33de Mon Sep 17 00:00:00 2001 From: wdx04 <25487439@qq.com> Date: Fri, 29 Aug 2025 11:50:37 +0800 Subject: [PATCH 05/15] verified OSPI Flash can work without DMA --- targets/TARGET_STM/ospi_api.c | 4 ++++ targets/TARGET_STM/xspi_compat.h | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/ospi_api.c b/targets/TARGET_STM/ospi_api.c index a82185929c6..808ed9cc8ce 100644 --- a/targets/TARGET_STM/ospi_api.c +++ b/targets/TARGET_STM/ospi_api.c @@ -264,7 +264,11 @@ static ospi_status_t _ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap, obj->handle.Init.ClockPrescaler = 4; // default value, will be overwritten in ospi_frequency obj->handle.Init.FifoThreshold = 4; obj->handle.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE; +#if defined(HAL_XSPI_MODULE_ENABLED) + obj->handle.Init.DeviceSize = HAL_XSPI_SIZE_32GB; +#else obj->handle.Init.DeviceSize = 32; +#endif obj->handle.Init.ChipSelectHighTime = 3; obj->handle.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE; #if defined(HAL_OSPI_WRAP_NOT_SUPPORTED) diff --git a/targets/TARGET_STM/xspi_compat.h b/targets/TARGET_STM/xspi_compat.h index cbcd53e614e..c6c90ab6a95 100644 --- a/targets/TARGET_STM/xspi_compat.h +++ b/targets/TARGET_STM/xspi_compat.h @@ -110,6 +110,7 @@ #define HAL_OSPI_CLOCK_MODE_0 HAL_XSPI_CLOCK_MODE_0 #define HAL_OSPI_CLOCK_MODE_3 HAL_XSPI_CLOCK_MODE_3 #define HAL_OSPI_DHQC_ENABLE HAL_XSPI_DHQC_ENABLE +#define HAL_OSPI_DHQC_DISABLE HAL_XSPI_DHQC_DISABLE // API Functions #define HAL_OSPI_Init HAL_XSPI_Init @@ -133,7 +134,8 @@ #define HAL_OSPI_StatusMatchCallback HAL_XSPI_StatusMatchCallback #define HAL_OSPI_TimeOutCallback HAL_XSPI_TimeOutCallback #define HAL_OSPI_WRAP_NOT_SUPPORTED HAL_XSPI_WRAP_NOT_SUPPORTED -#define HAL_OSPI_DELAY_BLOCK_USED HAL_XSPI_DELAY_BLOCK_BYPASS +#define HAL_OSPI_DELAY_BLOCK_USED HAL_XSPI_DELAY_BLOCK_ON +#define HAL_OSPI_DELAY_BLOCK_BYPASS HAL_OSPI_DELAY_BLOCK_BYPASSED #endif From 6644237308328a85e8a6e2a238cc2bc17c3cccbb Mon Sep 17 00:00:00 2001 From: wdx04 <25487439@qq.com> Date: Fri, 29 Aug 2025 14:18:27 +0800 Subject: [PATCH 06/15] added DMA support for OCTOSPI --- targets/TARGET_STM/ospi_api.c | 244 +++++++++++++++++++++++++++++++++- targets/TARGET_STM/qspi_api.c | 29 +++- 2 files changed, 260 insertions(+), 13 deletions(-) diff --git a/targets/TARGET_STM/ospi_api.c b/targets/TARGET_STM/ospi_api.c index 808ed9cc8ce..d958ce67157 100644 --- a/targets/TARGET_STM/ospi_api.c +++ b/targets/TARGET_STM/ospi_api.c @@ -39,6 +39,23 @@ /* hence 2^(31+1), then FLASH_SIZE_DEFAULT = 1<<31 */ #define OSPI_FLASH_SIZE_DEFAULT 0x4000000 //512Mbits +/* Minimum number of bytes to be transferred using DMA, when DCACHE is not available */ +/* When less than 32 bytes of data is transferred at a time, using DMA may actually be slower than polling */ +/* When DACHE is available, DMA will be used when the buffer contains at least one cache-aligned block */ +#define OSPI_DMA_THRESHOLD_BYTES 32 + +// Stored pointer inside OSPI handle is ospi_s* +#define OSPI_POINTER_FLAG 2 + +// Store the ospi_s * inside an OSPI handle, for later retrieval in callbacks +static inline void store_ospi_pointer(OSPI_HandleTypeDef * ospiHandle, struct ospi_s * ospis) { + // Annoyingly, STM neglected to provide any sort of "user data" pointer inside OSPI_HandleTypeDef for use + // in callbacks. However, there are some variables in the Init struct that are never accessed after HAL_OSPI_Init(). + // So, we can reuse those to store our pointer. + ospiHandle->Init.ChipSelectHighTime = (uint32_t)ospis; + ospiHandle->Init.FreeRunningClock = OSPI_POINTER_FLAG; +} + static uint32_t get_alt_bytes_size(const uint32_t num_bytes) { switch (num_bytes) { @@ -235,6 +252,61 @@ ospi_status_t ospi_prepare_command(const ospi_command_t *command, OSPI_RegularCm return OSPI_STATUS_OK; } +/** + * Initialize the DMA for an OSPI object + * Does nothing if DMA is already initialized. + */ +static void ospi_init_dma(struct ospi_s * obj) +{ + if(!obj->dmaInitialized) + { + // Get DMA handle + DMALinkInfo const *dmaLink; +#if defined(OCTOSPI2) + if(obj->ospi == (OSPIName) OSPI_1) + { + dmaLink = &OSPIDMALinks[0]; + } + else + { + dmaLink = &OSPIDMALinks[1]; + } +#else + dmaLink = &OSPIDMALinks[0]; +#endif + // Initialize DMA channel + DMAHandlePointer dmaHandle = stm_init_dma_link(dmaLink, DMA_PERIPH_TO_MEMORY, false, true, 1, 1, DMA_NORMAL); + if(dmaHandle.hdma == NULL) + { + mbed_error(MBED_ERROR_ALREADY_IN_USE, "DMA channel already used by something else!", 0, MBED_FILENAME, __LINE__); + } +#if defined(MDMA) + __HAL_LINKDMA(&obj->handle, hmdma, *dmaHandle.hmdma); +#elif defined(TARGET_STM32H5) + __HAL_LINKDMA(&obj->handle, hdmarx, *dmaHandle.hdma); +#else + __HAL_LINKDMA(&obj->handle, hdma, *dmaHandle.hdma); +#endif +#if defined(TARGET_STM32H5) + // STM32H5 has only one OCTOSPI instance, but it requires separate DMA channels for RX and TX + DMALinkInfo const *dmaLinkTX = &OSPIDMALinks[1]; + // Initialize DMA channel + DMAHandlePointer dmaHandleTX = stm_init_dma_link(dmaLinkTX, DMA_MEMORY_TO_PERIPH, false, true, 1, 1, DMA_NORMAL); + if(dmaHandleTX.hdma == NULL) + { + mbed_error(MBED_ERROR_ALREADY_IN_USE, "DMA channel already used by something else!", 0, MBED_FILENAME, __LINE__); + } + __HAL_LINKDMA(&obj->handle, hdmatx, *dmaHandleTX.hdma); +#endif + obj->dmaInitialized = true; +#if MBED_CONF_RTOS_PRESENT + osSemaphoreAttr_t attr = { 0 }; + attr.cb_mem = &obj->semaphoreMem; + attr.cb_size = sizeof(osRtxSemaphore_t); + obj->semaphoreId = osSemaphoreNew(1, 0, &attr); +#endif + } +} #if STATIC_PINMAP_READY #define OSPI_INIT_DIRECT ospi_init_direct @@ -289,15 +361,22 @@ static ospi_status_t _ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap, // tested all combinations, take first obj->ospi = pinmap->peripheral; + obj->dmaInitialized = false; #if defined(OCTOSPI1) if (obj->ospi == OSPI_1) { obj->handle.Instance = OCTOSPI1; + obj->ospiIRQ = OCTOSPI1_IRQn; + extern OSPI_HandleTypeDef * ospiHandle1; + ospiHandle1 = &obj->handle; } #endif #if defined(OCTOSPI2) if (obj->ospi == OSPI_2) { obj->handle.Instance = OCTOSPI2; + obj->ospiIRQ = OCTOSPI2_IRQn; + extern OSPI_HandleTypeDef * ospiHandle2; + ospiHandle2 = &obj->handle; } #endif @@ -436,6 +515,30 @@ ospi_status_t ospi_init(ospi_t *obj, PinName io0, PinName io1, PinName io2, PinN ospi_status_t ospi_free(ospi_t *obj) { tr_debug("ospi_free"); + + if(obj->dmaInitialized) + { + // Get DMA handle + DMALinkInfo const *dmaLink; +#if defined(OCTOSPI2) + if(obj->ospi == (OSPIName) OSPI_1) + { + dmaLink = &OSPIDMALinks[0]; + } + else + { + dmaLink = &OSPIDMALinks[1]; + } +#else + dmaLink = &OSPIDMALinks[0]; +#endif + stm_free_dma_link(dmaLink); +#if defined(STM32H5) + // Free TX DMA handle for STM32H5 + stm_free_dma_link(&OSPIDMALinks[1]); +#endif + } + if (HAL_OSPI_DeInit(&obj->handle) != HAL_OK) { return OSPI_STATUS_ERROR; } @@ -475,6 +578,10 @@ ospi_status_t ospi_frequency(ospi_t *obj, int hz) { ospi_status_t status = OSPI_STATUS_OK; + // Reset flag used by store_ospi_pointer() + obj->handle.Init.ChipSelectHighTime = 3; + obj->handle.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE; + /* OSPI clock depends on prescaler value: * 0: Freq = HCLK * 1: Freq = HCLK/2 @@ -505,6 +612,8 @@ ospi_status_t ospi_frequency(ospi_t *obj, int hz) status = OSPI_STATUS_ERROR; } + store_ospi_pointer(&obj->handle, obj); + return status; } @@ -525,9 +634,39 @@ ospi_status_t ospi_write(ospi_t *obj, const ospi_command_t *command, const void tr_error("HAL_OSPI_Command error"); status = OSPI_STATUS_ERROR; } else { - if (HAL_OSPI_Transmit(&obj->handle, (uint8_t *)data, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - tr_error("HAL_OSPI_Transmit error"); - status = OSPI_STATUS_ERROR; + if(st_command.NbData >= OSPI_DMA_THRESHOLD_BYTES) { + ospi_init_dma(obj); + NVIC_ClearPendingIRQ(obj->ospiIRQ); + NVIC_SetPriority(obj->ospiIRQ, 1); + NVIC_EnableIRQ(obj->ospiIRQ); +#if defined(__DCACHE_PRESENT) + // For chips with a cache (e.g. Cortex-M7), we need to evict the Tx fill data from cache to main memory. + // This ensures that the DMA controller can see the most up-to-date copy of the data. + SCB_CleanDCache_by_Addr((volatile void *)data, *length); +#endif + if (HAL_OSPI_Transmit_DMA(&obj->handle, (uint8_t *)data) != HAL_OK) { + tr_error("HAL_OSPI_Transmit error"); + status = OSPI_STATUS_ERROR; + } + else { + // wait until transfer complete or timeout +#if MBED_CONF_RTOS_PRESENT + osSemaphoreAcquire(obj->semaphoreId, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); +#else + while(obj->handle.State == HAL_OSPI_STATE_BUSY_TX); +#endif + if(obj->handle.State != HAL_OSPI_STATE_READY) { + status = OSPI_STATUS_ERROR; + obj->handle.State = HAL_OSPI_STATE_READY; + } + } + NVIC_DisableIRQ(obj->ospiIRQ); + } + else { + if (HAL_OSPI_Transmit(&obj->handle, (uint8_t *)data, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { + tr_error("HAL_OSPI_Transmit error"); + status = OSPI_STATUS_ERROR; + } } } @@ -542,17 +681,108 @@ ospi_status_t ospi_read(ospi_t *obj, const ospi_command_t *command, void *data, return status; } +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + size_t pre_aligned_size, aligned_size, post_aligned_size; + split_buffer_by_cacheline(data, length, &pre_aligned_size, &aligned_size, &post_aligned_size); + if(pre_aligned_size > 0) + { + st_command.NbData = pre_aligned_size; + if (HAL_OSPI_Command(&obj->handle, &st_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { + tr_error("HAL_OSPI_Command error"); + status = OSPI_STATUS_ERROR; + } else { + if (HAL_OSPI_Receive(&obj->handle, data, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { + tr_error("HAL_OSPI_Receive error %d", obj->handle.ErrorCode); + status = OSPI_STATUS_ERROR; + } + } + st_command.Address += pre_aligned_size; + data += pre_aligned_size; + } + if(status == OSPI_STATUS_OK && aligned_size > 0) + { + st_command.NbData = aligned_size; + if (HAL_OSPI_Command(&obj->handle, &st_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { + tr_error("HAL_OSPI_Command error"); + status = OSPI_STATUS_ERROR; + } else { + ospi_init_dma(obj); + NVIC_ClearPendingIRQ(obj->ospiIRQ); + NVIC_SetPriority(obj->ospiIRQ, 1); + NVIC_EnableIRQ(obj->ospiIRQ); + SCB_CleanInvalidateDCache_by_Addr((volatile void *)data, *length); + if (HAL_OSPI_Receive_DMA(&obj->handle, data) != HAL_OK) { + tr_error("HAL_OSPI_Receive error %d", obj->handle.ErrorCode); + status = OSPI_STATUS_ERROR; + } + else { + // wait until transfer complete or timeout +#if MBED_CONF_RTOS_PRESENT + osSemaphoreAcquire(obj->semaphoreId, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); +#else + while(obj->handle.State == HAL_OSPI_STATE_BUSY_RX); +#endif + if(obj->handle.State != HAL_OSPI_STATE_READY) { + status = OSPI_STATUS_ERROR; + obj->handle.State = HAL_OSPI_STATE_READY; + } + } + NVIC_DisableIRQ(obj->ospiIRQ); + } + st_command.Address += aligned_size; + data += aligned_size; + } + if(status == OSPI_STATUS_OK && post_aligned_size > 0) + { + st_command.NbData = post_aligned_size; + if (HAL_OSPI_Command(&obj->handle, &st_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { + tr_error("HAL_OSPI_Command error"); + status = OSPI_STATUS_ERROR; + } else { + if (HAL_OSPI_Receive(&obj->handle, data, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { + tr_error("HAL_OSPI_Receive error %d", obj->handle.ErrorCode); + status = OSPI_STATUS_ERROR; + } + } + } +#else st_command.NbData = *length; if (HAL_OSPI_Command(&obj->handle, &st_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { tr_error("HAL_OSPI_Command error"); status = OSPI_STATUS_ERROR; } else { - if (HAL_OSPI_Receive(&obj->handle, data, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { - tr_error("HAL_OSPI_Receive error %d", obj->handle.ErrorCode); - status = OSPI_STATUS_ERROR; + if(st_command.NbData >= OSPI_DMA_THRESHOLD_BYTES) { + ospi_init_dma(obj); + NVIC_ClearPendingIRQ(obj->ospiIRQ); + NVIC_SetPriority(obj->ospiIRQ, 1); + NVIC_EnableIRQ(obj->ospiIRQ); + if (HAL_OSPI_Receive_DMA(&obj->handle, data) != HAL_OK) { + tr_error("HAL_OSPI_Receive error %d", obj->handle.ErrorCode); + status = OSPI_STATUS_ERROR; + } + else { + // wait until transfer complete or timeout +#if MBED_CONF_RTOS_PRESENT + osSemaphoreAcquire(obj->semaphoreId, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); +#else + while(obj->handle.State == HAL_OSPI_STATE_BUSY_RX); +#endif + if(obj->handle.State != HAL_OSPI_STATE_READY) { + status = OSPI_STATUS_ERROR; + obj->handle.State = HAL_OSPI_STATE_READY; + } + } + NVIC_DisableIRQ(obj->ospiIRQ); + } + else { + if (HAL_OSPI_Receive(&obj->handle, data, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { + tr_error("HAL_OSPI_Receive error %d", obj->handle.ErrorCode); + status = OSPI_STATUS_ERROR; + } } } +#endif debug_if(ospi_api_c_debug, "ospi_read size %u\n", *length); @@ -585,7 +815,7 @@ ospi_status_t ospi_command_transfer(ospi_t *obj, const ospi_command_t *command, size_t tx_length = tx_size; status = ospi_write(obj, command, tx_data, &tx_length); if (status != OSPI_STATUS_OK) { - tr_error("qspi_write error"); + tr_error("ospi_write error"); return status; } } diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c index 177113feff9..ac5d75854bd 100644 --- a/targets/TARGET_STM/qspi_api.c +++ b/targets/TARGET_STM/qspi_api.c @@ -99,7 +99,11 @@ void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef * handle) #endif #if defined(OCTOSPI1) -static OSPI_HandleTypeDef * ospiHandle1; + +// Stored pointer inside OSPI handle is qspi_s* +#define QSPI_POINTER_FLAG 1 + +OSPI_HandleTypeDef * ospiHandle1; // Store the qspi_s * inside an OSPI handle, for later retrieval in callbacks static inline void store_qspi_pointer(OSPI_HandleTypeDef * ospiHandle, struct qspi_s * qspis) { @@ -107,6 +111,7 @@ static inline void store_qspi_pointer(OSPI_HandleTypeDef * ospiHandle, struct qs // in callbacks. However, there are some variables in the Init struct that are never accessed after HAL_OSPI_Init(). // So, we can reuse those to store our pointer. ospiHandle->Init.ChipSelectHighTime = (uint32_t)qspis; + ospiHandle->Init.FreeRunningClock = QSPI_POINTER_FLAG; } // Get qspi_s * from OSPI_HandleTypeDef @@ -114,20 +119,31 @@ static inline struct qspi_s * get_qspi_pointer(OSPI_HandleTypeDef * ospiHandle) return (struct qspi_s *) ospiHandle->Init.ChipSelectHighTime; } +// Get ospi_s * from OSPI_HandleTypeDef +static inline struct ospi_s * get_ospi_pointer(OSPI_HandleTypeDef * ospiHandle) { + return (struct ospi_s *) ospiHandle->Init.ChipSelectHighTime; +} + void OCTOSPI1_IRQHandler() { HAL_OSPI_IRQHandler(ospiHandle1); } #if MBED_CONF_RTOS_PRESENT +static inline osSemaphoreId_t get_semaphore_id(OSPI_HandleTypeDef * handle) { + osSemaphoreId_t semaphoreId = handle->Init.FreeRunningClock == QSPI_POINTER_FLAG ? + get_qspi_pointer(handle)->semaphoreId: get_ospi_pointer(handle)->semaphoreId; + return semaphoreId; +} + void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef * handle) { - osSemaphoreRelease(get_qspi_pointer(handle)->semaphoreId); + osSemaphoreRelease(get_semaphore_id(handle)); } void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef * handle) { - osSemaphoreRelease(get_qspi_pointer(handle)->semaphoreId); + osSemaphoreRelease(get_semaphore_id(handle)); } #endif @@ -135,7 +151,7 @@ void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef * handle) { handle->State = HAL_OSPI_STATE_ERROR; #if MBED_CONF_RTOS_PRESENT - osSemaphoreRelease(get_qspi_pointer(handle)->semaphoreId); + osSemaphoreRelease(get_semaphore_id(handle)); #endif } @@ -143,13 +159,13 @@ void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef * handle) { handle->State = HAL_OSPI_STATE_ERROR; #if MBED_CONF_RTOS_PRESENT - osSemaphoreRelease(get_qspi_pointer(handle)->semaphoreId); + osSemaphoreRelease(get_semaphore_id(handle)); #endif } #endif #if defined(OCTOSPI2) -static OSPI_HandleTypeDef * ospiHandle2; +OSPI_HandleTypeDef * ospiHandle2; void OCTOSPI2_IRQHandler() { @@ -986,6 +1002,7 @@ qspi_status_t qspi_frequency(qspi_t *obj, int hz) // Reset flag used by store_qspi_pointer() obj->handle.Init.ChipSelectHighTime = 3; + obj->handle.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE; /* HCLK drives QSPI. QSPI clock depends on prescaler value: * 0: Freq = HCLK From e1e2419967385cb9c9a7b715918faaa4e6f088a6 Mon Sep 17 00:00:00 2001 From: wdx04 <25487439@qq.com> Date: Sat, 30 Aug 2025 15:55:56 +0800 Subject: [PATCH 07/15] add ethernet files --- .../TARGET_STM/TARGET_STM32H5/CMakeLists.txt | 5 +- .../TARGET_DISCO_H573I/CMakeLists.txt | 7 ++ .../TARGET_DISCO_H573I/stm32h5_eth_init.c | 117 ++++++++++++++++++ targets/cmsis_mcu_descriptions.json5 | 20 +-- 4 files changed, 139 insertions(+), 10 deletions(-) create mode 100644 connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/TARGET_DISCO_H573I/CMakeLists.txt create mode 100644 connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/TARGET_DISCO_H573I/stm32h5_eth_init.c diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/CMakeLists.txt b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/CMakeLists.txt index 4d5bb6aeb92..5b7f97a2792 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/CMakeLists.txt +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/CMakeLists.txt @@ -3,4 +3,7 @@ if("NUCLEO_H563ZI" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_NUCLEO_H563ZI) -endif() \ No newline at end of file +endif() +if("DISCO_H573I" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_DISCO_H573I) +endif() diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/TARGET_DISCO_H573I/CMakeLists.txt b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/TARGET_DISCO_H573I/CMakeLists.txt new file mode 100644 index 00000000000..48a8fc06595 --- /dev/null +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/TARGET_DISCO_H573I/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2025 Jamie Smith +# SPDX-License-Identifier: Apache-2.0 + +target_sources(mbed-emac + PRIVATE + stm32h5_eth_init.c +) diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/TARGET_DISCO_H573I/stm32h5_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/TARGET_DISCO_H573I/stm32h5_eth_init.c new file mode 100644 index 00000000000..532b41e5d98 --- /dev/null +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/TARGET_DISCO_H573I/stm32h5_eth_init.c @@ -0,0 +1,117 @@ +/* mbed Microcontroller Library + * Copyright (c) 2025, STMicroelectronics + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "stm32h5xx_hal.h" +#include "platform/mbed_critical.h" +#include "PinNames.h" + +/** + * Override HAL Eth Init function. + * + * Note: This was copied from HAL_ETH_MspInit() in a project for the NUCLEO-H563ZI in STM32CubeIDE + */ +void EthInitPinmappings(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* Peripheral clock enable */ + __HAL_RCC_ETH_CLK_ENABLE(); + __HAL_RCC_ETHTX_CLK_ENABLE(); + __HAL_RCC_ETHRX_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PG12 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); +} + +/** + * Override HAL Eth DeInit function + */ +void EthDeinitPinmappings() +{ + /* Peripheral clock disable */ + __HAL_RCC_ETH_CLK_DISABLE(); + __HAL_RCC_ETHTX_CLK_DISABLE(); + __HAL_RCC_ETHRX_CLK_DISABLE(); + + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB15 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13); +} + +// Get Ethernet PHY reset pin +PinName EthGetPhyResetPin(void) +{ + return NC; // Not connected on this board +} diff --git a/targets/cmsis_mcu_descriptions.json5 b/targets/cmsis_mcu_descriptions.json5 index 25e998d3ca3..7bad3d684b4 100644 --- a/targets/cmsis_mcu_descriptions.json5 +++ b/targets/cmsis_mcu_descriptions.json5 @@ -8019,7 +8019,8 @@ "start": 134217728, "startup": true }, - "SRAM1_2": { + // Combined SRAMs 1, 2, and 3 + "SRAM1_2_3": { "access": { "execute": true, "non_secure": false, @@ -8031,13 +8032,16 @@ }, "default": true, "p_name": null, - "size": 327680, - "start": 536870912, + "size": 0xA0000, // 640 kiB + "start": 0x20000000, "startup": false }, - "SRAM3": { + // Backup SRAM. This is mentioned in the datasheet but neither the reference manual nor the CMSIS pack + // gives its address... + // Got this info from a forum post: https://community.st.com/t5/stm32-mcus-products/backup-sram-on-stm32h563/td-p/580633 + "SRAM_BKUP": { "access": { - "execute": true, + "execute": false, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -8045,10 +8049,8 @@ "secure": false, "write": true }, - "default": false, - "p_name": null, - "size": 327680, - "start": 537198592, + "size": 0x1000, + "start": 0x40036400, "startup": false } }, From 64d965bf213a1fcfa0ec490473fad0e05e37d3eb Mon Sep 17 00:00:00 2001 From: wdx04 Date: Sun, 31 Aug 2025 11:05:05 +0800 Subject: [PATCH 08/15] fix crash during FlashIAP by temporarily increase Flash latency fix init-deinit-init sequence of OSPIFBlockDevice by performing a soft reset at deinit --- .../include/OSPIF/OSPIFBlockDevice.h | 15 +++ .../source/OSPIFBlockDevice.cpp | 116 ++++++++---------- targets/TARGET_STM/TARGET_STM32H5/flash_api.c | 36 ++++-- 3 files changed, 92 insertions(+), 75 deletions(-) diff --git a/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h index 853901ec90c..63908d04040 100644 --- a/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h +++ b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h @@ -104,6 +104,16 @@ enum ospif_polarity_mode { OSPIF_POLARITY_MODE_1 /* CPOL=1, CPHA=1 */ }; +/** Enum ospif soft reset modes + * + * @enum ospif_soft_reset_mode + */ +enum ospif_soft_reset_mode { + OSPIF_SOFT_RESET_UNSUPPORTED = 0, /* Soft reset not supported */ + OSPIF_DIERCT_SOFT_RESET, /* Direct soft reset mode */ + OSPIF_ENABLE_AND_SOFT_RESET /* Enable and soft reset mode */ +}; + #define OSPIF_MAX_ACTIVE_FLASH_DEVICES 10 /** BlockDevice for SFDP based flash devices over OSPI bus @@ -389,6 +399,9 @@ class OSPIFBlockDevice : public mbed::BlockDevice { // Enable Quad mode if supported (1-1-4, 1-4-4, 4-4-4 bus modes) int _sfdp_set_quad_enabled(uint8_t *basic_param_table_ptr); + // Perform soft reset if supported - returns error if soft reset is not supported + int _soft_reset(); + // Enable QPI mode (4-4-4) int _sfdp_set_qpi_enabled(uint8_t *basic_param_table_ptr); @@ -461,6 +474,8 @@ class OSPIFBlockDevice : public mbed::BlockDevice { uint8_t _dummy_cycles; //Number of Dummy cycles required by Current Bus Mode ospi_bus_width_t _data_width; //Bus width for Data phase + ospif_soft_reset_mode _soft_reset_mode; // Soft Reset mode + uint32_t _init_ref_count; bool _is_initialized; #ifdef MX_FLASH_SUPPORT_RWW diff --git a/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp b/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp index 88f81b311a2..4905be5a65d 100644 --- a/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp +++ b/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp @@ -201,7 +201,8 @@ OSPIFBlockDevice::OSPIFBlockDevice(PinName io0, PinName io1, PinName io2, PinNam int clock_mode, int freq) : _ospi(io0, io1, io2, io3, io4, io5, io6, io7, sclk, csel, dqs, clock_mode), _csel(csel), _freq(freq), _init_ref_count(0), - _is_initialized(false) + _is_initialized(false), + _soft_reset_mode(OSPIF_SOFT_RESET_UNSUPPORTED) { _unique_device_status = add_new_csel_instance(csel); @@ -389,14 +390,7 @@ int OSPIFBlockDevice::deinit() _wait_flag = NOT_STARTED; #endif - change_mode(OSPIF_OPI_MODE_SPI); - - // Disable Device for Writing - ospi_status_t status = _ospi_send_general_command(OSPIF_INST_WRDI, OSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0); - if (status != OSPI_STATUS_OK) { - tr_error("Write Disable failed"); - result = OSPIF_BD_ERROR_DEVICE_ERROR; - } + result = _soft_reset(); _is_initialized = false; @@ -746,10 +740,6 @@ int OSPIFBlockDevice::change_mode(int mode) tr_error(" Writing Config Register2 Failed"); return -1; } - - // Configure BUS Mode to 1_1_1 - _ospi.configure_format(OSPI_CFG_BUS_SINGLE, OSPI_CFG_INST_SIZE_8, OSPI_CFG_BUS_SINGLE, OSPI_CFG_ADDR_SIZE_32, - OSPI_CFG_BUS_SINGLE, 0, OSPI_CFG_BUS_SINGLE, 0); } _ospi.configure_format(OSPI_CFG_BUS_SINGLE, OSPI_CFG_INST_SIZE_8, OSPI_CFG_BUS_SINGLE, OSPI_CFG_ADDR_SIZE_32, @@ -793,15 +783,11 @@ int OSPIFBlockDevice::change_mode(int mode) if (OSPI_STATUS_OK == _ospi_send_general_command(OSPIF_INST_WRCR2, OSPIF_CR2_OPI_EN_ADDR, &config_reg2, 1, NULL, 0)) { - tr_debug("OPI mode enable - Writing Config Register2 Success: value = 0x%x", config_reg2); + tr_debug("OPI mode disable - Writing Config Register2 Success: value = 0x%x", config_reg2); } else { - tr_error("OPI mode enable - Writing Config Register2 failed"); + tr_error("OPI mode disable - Writing Config Register2 failed"); return -1; } - - // Configure BUS Mode to 1_1_1 - _ospi.configure_format(OSPI_CFG_BUS_SINGLE, OSPI_CFG_INST_SIZE_8, OSPI_CFG_BUS_SINGLE, OSPI_CFG_ADDR_SIZE_32, - OSPI_CFG_BUS_SINGLE, 0, OSPI_CFG_BUS_SINGLE, 0); } _ospi.configure_format(OSPI_CFG_BUS_SINGLE, OSPI_CFG_INST_SIZE_8, OSPI_CFG_BUS_SINGLE, OSPI_CFG_ADDR_SIZE_32, @@ -834,32 +820,8 @@ int OSPIFBlockDevice::change_mode(int mode) _ospi.configure_format(_inst_width, _inst_size, _address_width, _address_size, OSPI_CFG_BUS_SINGLE, 0, _data_width, 0); } else if (mode == OSPIF_OPI_MODE_SPI) { - // Write new Status Register Setup - if (_set_write_enable() != 0) { - tr_error("Write Enabe failed"); - return -1; - } - - config_reg2 = 0x00; - - if (OSPI_STATUS_OK == _ospi_send_general_command(OSPIF_INST_WRCR2, OSPIF_CR2_OPI_EN_ADDR, &config_reg2, - 1, NULL, 0)) { - tr_debug("OPI mode enable - Writing Config Register2 Success: value = 0x%x", config_reg2); - } else { - tr_error("OPI mode enable - Writing Config Register2 failed"); - return -1; - } - _read_instruction = OSPIF_INST_READ_4B; - _dummy_cycles = 0; - - _inst_width = OSPI_CFG_BUS_SINGLE; - _inst_size = OSPI_CFG_INST_SIZE_8; - _address_width = OSPI_CFG_BUS_SINGLE; - _address_size = OSPI_CFG_ADDR_SIZE_32; - _data_width = OSPI_CFG_BUS_SINGLE; - - _ospi.configure_format(_inst_width, _inst_size, _address_width, _address_size, OSPI_CFG_BUS_SINGLE, - 0, _data_width, _dummy_cycles); + // Perform a soft reset to switch to SPI mode as suggested by Copilot + status = _soft_reset(); } return status; } @@ -1364,8 +1326,6 @@ int OSPIFBlockDevice::_sfdp_detect_and_enable_4byte_addressing(uint8_t *basic_pa int OSPIFBlockDevice::_sfdp_detect_reset_protocol_and_reset(uint8_t *basic_param_table_ptr) { - int status = OSPIF_BD_ERROR_OK; - #if RESET_SEQUENCE_FROM_SFDP uint8_t examined_byte = basic_param_table_ptr[OSPIF_BASIC_PARAM_TABLE_SOFT_RESET_BYTE]; @@ -1374,10 +1334,7 @@ int OSPIFBlockDevice::_sfdp_detect_reset_protocol_and_reset(uint8_t *basic_param #endif #if !MBED_CONF_OSPIF_ENABLE_AND_RESET // i.e. direct reset, or determined from SFDP - // Issue instruction 0xF0 to reset the device - ospi_status_t ospi_status = _ospi_send_general_command(0xF0, OSPI_NO_ADDRESS_COMMAND, // Send reset instruction - NULL, 0, NULL, 0); - status = (ospi_status == OSPI_STATUS_OK) ? OSPIF_BD_ERROR_OK : OSPIF_BD_ERROR_PARSING_FAILED; + _soft_reset_mode = OSPIF_DIERCT_SOFT_RESET; #endif #if RESET_SEQUENCE_FROM_SFDP @@ -1385,27 +1342,60 @@ int OSPIFBlockDevice::_sfdp_detect_reset_protocol_and_reset(uint8_t *basic_param #endif #if !MBED_CONF_OSPIF_DIRECT_RESET // i.e. enable and reset, or determined from SFDP - // Issue instruction 66h to enable resets on the device - // Then issue instruction 99h to reset the device - ospi_status_t ospi_status = _ospi_send_general_command(0x66, OSPI_NO_ADDRESS_COMMAND, // Send reset enable instruction - NULL, 0, NULL, 0); - if (ospi_status == OSPI_STATUS_OK) { - ospi_status = _ospi_send_general_command(0x99, OSPI_NO_ADDRESS_COMMAND, // Send reset instruction - NULL, 0, NULL, 0); - } - status = (ospi_status == OSPI_STATUS_OK) ? OSPIF_BD_ERROR_OK : OSPIF_BD_ERROR_PARSING_FAILED; + _soft_reset_mode = OSPIF_ENABLE_AND_SOFT_RESET; #endif #if RESET_SEQUENCE_FROM_SFDP } else { // Soft reset either is not supported or requires direct control over data lines - tr_error("Failed to determine soft reset sequence. If your device has a legacy SFDP table, please manually set enable-and-reset or direct-reset."); - - status = OSPIF_BD_ERROR_PARSING_FAILED; + _soft_reset_mode = OSPIF_SOFT_RESET_UNSUPPORTED; } #endif + return _soft_reset(); +} + +int OSPIFBlockDevice::_soft_reset() +{ + int status = OSPIF_BD_ERROR_OK; + ospi_status_t ospi_status = OSPI_STATUS_OK; + + switch(_soft_reset_mode) { + case OSPIF_SOFT_RESET_UNSUPPORTED: + status = OSPIF_BD_ERROR_PARSING_FAILED; + break; + case OSPIF_DIERCT_SOFT_RESET: + // Issue instruction 0xF0 to reset the device + ospi_status = _ospi_send_general_command(0xF0, OSPI_NO_ADDRESS_COMMAND, // Send reset instruction + NULL, 0, NULL, 0); + status = (ospi_status == OSPI_STATUS_OK) ? OSPIF_BD_ERROR_OK : OSPIF_BD_ERROR_PARSING_FAILED; + break; + case OSPIF_ENABLE_AND_SOFT_RESET: + // Issue instruction 66h to enable resets on the device + // Then issue instruction 99h to reset the device + ospi_status = _ospi_send_general_command(0x66, OSPI_NO_ADDRESS_COMMAND, // Send reset enable instruction + NULL, 0, NULL, 0); + if (ospi_status == OSPI_STATUS_OK) { + ospi_status = _ospi_send_general_command(0x99, OSPI_NO_ADDRESS_COMMAND, // Send reset instruction + NULL, 0, NULL, 0); + } + status = (ospi_status == OSPI_STATUS_OK) ? OSPIF_BD_ERROR_OK : OSPIF_BD_ERROR_PARSING_FAILED; + break; + } if (status == OSPIF_BD_ERROR_OK) { + // Set SPI format after soft reset + _read_instruction = OSPIF_INST_READ_4B; + _dummy_cycles = 0; + + _inst_width = OSPI_CFG_BUS_SINGLE; + _inst_size = OSPI_CFG_INST_SIZE_8; + _address_width = OSPI_CFG_BUS_SINGLE; + _address_size = OSPI_CFG_ADDR_SIZE_32; + _data_width = OSPI_CFG_BUS_SINGLE; + + _ospi.configure_format(_inst_width, _inst_size, _address_width, _address_size, OSPI_CFG_BUS_SINGLE, + 0, _data_width, _dummy_cycles); + if (false == _is_mem_ready()) { tr_error("Device not ready, reset failed"); status = OSPIF_BD_ERROR_READY_FAILED; diff --git a/targets/TARGET_STM/TARGET_STM32H5/flash_api.c b/targets/TARGET_STM/TARGET_STM32H5/flash_api.c index 6f0efce27ca..41f8c8975e0 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32H5/flash_api.c @@ -93,12 +93,12 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) return -1; } - if (HAL_FLASH_Unlock() != HAL_OK) { + if (HAL_ICACHE_Disable() != HAL_OK) + { return -1; } - if (HAL_ICACHE_Disable() != HAL_OK) - { + if (HAL_FLASH_Unlock() != HAL_OK) { return -1; } @@ -107,6 +107,9 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) /* Clear error programming flags */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); + /* Increase Flash latency while programming */ + __HAL_FLASH_SET_LATENCY(6); + /* MBED HAL erases 1 page / sector at a time */ /* Fill EraseInit structure*/ EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; @@ -118,14 +121,17 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) status = -1; } + /* Restore normal Flash latency */ + __HAL_FLASH_SET_LATENCY(5); + core_util_critical_section_exit(); - if (HAL_ICACHE_Enable() != HAL_OK) - { + if (HAL_FLASH_Lock() != HAL_OK) { return -1; } - if (HAL_FLASH_Lock() != HAL_OK) { + if (HAL_ICACHE_Enable() != HAL_OK) + { return -1; } @@ -158,18 +164,21 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, return -1; } - if (HAL_FLASH_Unlock() != HAL_OK) { + if (HAL_ICACHE_Disable() != HAL_OK) + { return -1; } - if (HAL_ICACHE_Disable() != HAL_OK) - { + if (HAL_FLASH_Unlock() != HAL_OK) { return -1; } /* Clear error programming flags */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); + /* Increase Flash latency while programming */ + __HAL_FLASH_SET_LATENCY(6); + /* Program the user Flash area word by word */ StartAddress = address; @@ -184,12 +193,15 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, } } - if (HAL_ICACHE_Enable() != HAL_OK) - { + /* Restore normal Flash latency */ + __HAL_FLASH_SET_LATENCY(5); + + if (HAL_FLASH_Lock() != HAL_OK) { return -1; } - if (HAL_FLASH_Lock() != HAL_OK) { + if (HAL_ICACHE_Enable() != HAL_OK) + { return -1; } From 3c40a211ad0dc75eb5f9eddf5e8c5aeed0d97956 Mon Sep 17 00:00:00 2001 From: wdx04 Date: Sun, 31 Aug 2025 13:03:41 +0800 Subject: [PATCH 09/15] do not use XSPI on STM32U5 fix style check errors --- .../COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h | 7 ++++--- .../COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp | 8 ++++---- targets/TARGET_STM/ospi_api.c | 6 +++--- targets/TARGET_STM/qspi_api.c | 4 ++-- targets/TARGET_STM/xspi_compat.h | 2 +- 5 files changed, 14 insertions(+), 13 deletions(-) diff --git a/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h index 63908d04040..20d4096e8a2 100644 --- a/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h +++ b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h @@ -474,11 +474,12 @@ class OSPIFBlockDevice : public mbed::BlockDevice { uint8_t _dummy_cycles; //Number of Dummy cycles required by Current Bus Mode ospi_bus_width_t _data_width; //Bus width for Data phase - ospif_soft_reset_mode _soft_reset_mode; // Soft Reset mode - uint32_t _init_ref_count; bool _is_initialized; -#ifdef MX_FLASH_SUPPORT_RWW + + ospif_soft_reset_mode _soft_reset_mode; // Soft Reset mode + + #ifdef MX_FLASH_SUPPORT_RWW enum wait_flag { NOT_STARTED, // no wait is started WRITE_WAIT_STARTED, // write wait is started diff --git a/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp b/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp index 4905be5a65d..846300e1ac8 100644 --- a/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp +++ b/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp @@ -1367,17 +1367,17 @@ int OSPIFBlockDevice::_soft_reset() case OSPIF_DIERCT_SOFT_RESET: // Issue instruction 0xF0 to reset the device ospi_status = _ospi_send_general_command(0xF0, OSPI_NO_ADDRESS_COMMAND, // Send reset instruction - NULL, 0, NULL, 0); + NULL, 0, NULL, 0); status = (ospi_status == OSPI_STATUS_OK) ? OSPIF_BD_ERROR_OK : OSPIF_BD_ERROR_PARSING_FAILED; break; case OSPIF_ENABLE_AND_SOFT_RESET: // Issue instruction 66h to enable resets on the device // Then issue instruction 99h to reset the device ospi_status = _ospi_send_general_command(0x66, OSPI_NO_ADDRESS_COMMAND, // Send reset enable instruction - NULL, 0, NULL, 0); + NULL, 0, NULL, 0); if (ospi_status == OSPI_STATUS_OK) { ospi_status = _ospi_send_general_command(0x99, OSPI_NO_ADDRESS_COMMAND, // Send reset instruction - NULL, 0, NULL, 0); + NULL, 0, NULL, 0); } status = (ospi_status == OSPI_STATUS_OK) ? OSPIF_BD_ERROR_OK : OSPIF_BD_ERROR_PARSING_FAILED; break; @@ -1394,7 +1394,7 @@ int OSPIFBlockDevice::_soft_reset() _data_width = OSPI_CFG_BUS_SINGLE; _ospi.configure_format(_inst_width, _inst_size, _address_width, _address_size, OSPI_CFG_BUS_SINGLE, - 0, _data_width, _dummy_cycles); + 0, _data_width, _dummy_cycles); if (false == _is_mem_ready()) { tr_error("Device not ready, reset failed"); diff --git a/targets/TARGET_STM/ospi_api.c b/targets/TARGET_STM/ospi_api.c index d958ce67157..2f073f1ae8d 100644 --- a/targets/TARGET_STM/ospi_api.c +++ b/targets/TARGET_STM/ospi_api.c @@ -81,7 +81,7 @@ ospi_status_t ospi_prepare_command(const ospi_command_t *command, OSPI_RegularCm #if defined(HAL_OSPI_DUALQUAD_DISABLE) st_command->FlashId = HAL_OSPI_FLASH_ID_1; #endif -#if defined(HAL_XSPI_MODULE_ENABLED) +#if defined(HAL_XSPI_MODULE_ENABLED) && !defined(TARGET_STM32U5) st_command->IOSelect = HAL_XSPI_SELECT_IO_7_0; #endif if (command->instruction.disabled == true) { @@ -325,7 +325,7 @@ static ospi_status_t _ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap, #if defined(HAL_OSPI_DUALQUAD_DISABLE) obj->handle.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE; #endif -#if defined(HAL_XSPI_MODULE_ENABLED) +#if defined(HAL_XSPI_MODULE_ENABLED) && !defined(TARGET_STM32U5) obj->handle.Init.MemoryMode = HAL_XSPI_SINGLE_MEM; #endif #if defined(TARGET_MX25LM51245G) @@ -336,7 +336,7 @@ static ospi_status_t _ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap, obj->handle.Init.ClockPrescaler = 4; // default value, will be overwritten in ospi_frequency obj->handle.Init.FifoThreshold = 4; obj->handle.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE; -#if defined(HAL_XSPI_MODULE_ENABLED) +#if defined(HAL_XSPI_MODULE_ENABLED) && !defined(TARGET_STM32U5) obj->handle.Init.DeviceSize = HAL_XSPI_SIZE_32GB; #else obj->handle.Init.DeviceSize = 32; diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c index ac5d75854bd..b6301f64f21 100644 --- a/targets/TARGET_STM/qspi_api.c +++ b/targets/TARGET_STM/qspi_api.c @@ -215,7 +215,7 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCm #if defined(HAL_OSPI_DUALQUAD_DISABLE) st_command->FlashId = HAL_OSPI_FLASH_ID_1; #endif -#if defined(HAL_XSPI_MODULE_ENABLED) +#if defined(HAL_XSPI_MODULE_ENABLED) && !defined(TARGET_STM32U5) #if defined(QSPI_OSPIM_IOPORT_HIGH) st_command->IOSelect = HAL_XSPI_SELECT_IO_7_4; #else @@ -595,7 +595,7 @@ static qspi_status_t _qspi_init_direct(qspi_t *obj, const qspi_pinmap_t *pinmap, #if defined(HAL_OSPI_DUALQUAD_DISABLE) obj->handle.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE; #endif -#if defined(HAL_XSPI_MODULE_ENABLED) +#if defined(HAL_XSPI_MODULE_ENABLED) && !defined(TARGET_STM32U5) obj->handle.Init.MemoryMode = HAL_XSPI_SINGLE_MEM; #endif #if defined(TARGET_MX25LM51245G) diff --git a/targets/TARGET_STM/xspi_compat.h b/targets/TARGET_STM/xspi_compat.h index c6c90ab6a95..20314750012 100644 --- a/targets/TARGET_STM/xspi_compat.h +++ b/targets/TARGET_STM/xspi_compat.h @@ -33,7 +33,7 @@ // XSPI compatibility layer: emulate XSPI API as OSPI API -#if defined(HAL_XSPI_MODULE_ENABLED) +#if defined(HAL_XSPI_MODULE_ENABLED) && !defined(TARGET_STM32U5) // Types #define OSPI_HandleTypeDef XSPI_HandleTypeDef From d8516fdee46953ee6d454134fcde3186c63096a9 Mon Sep 17 00:00:00 2001 From: wdx04 Date: Sun, 31 Aug 2025 13:51:19 +0800 Subject: [PATCH 10/15] add a upload method config file fix astyle errors --- .../include/OSPIF/OSPIFBlockDevice.h | 2 +- .../source/OSPIFBlockDevice.cpp | 2 +- targets/upload_method_cfg/DISCO_H573I.cmake | 45 +++++++++++++++++++ 3 files changed, 47 insertions(+), 2 deletions(-) create mode 100644 targets/upload_method_cfg/DISCO_H573I.cmake diff --git a/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h index 20d4096e8a2..d25559cd4ab 100644 --- a/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h +++ b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h @@ -479,7 +479,7 @@ class OSPIFBlockDevice : public mbed::BlockDevice { ospif_soft_reset_mode _soft_reset_mode; // Soft Reset mode - #ifdef MX_FLASH_SUPPORT_RWW +#ifdef MX_FLASH_SUPPORT_RWW enum wait_flag { NOT_STARTED, // no wait is started WRITE_WAIT_STARTED, // write wait is started diff --git a/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp b/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp index 846300e1ac8..12b595394e1 100644 --- a/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp +++ b/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp @@ -1360,7 +1360,7 @@ int OSPIFBlockDevice::_soft_reset() int status = OSPIF_BD_ERROR_OK; ospi_status_t ospi_status = OSPI_STATUS_OK; - switch(_soft_reset_mode) { + switch (_soft_reset_mode) { case OSPIF_SOFT_RESET_UNSUPPORTED: status = OSPIF_BD_ERROR_PARSING_FAILED; break; diff --git a/targets/upload_method_cfg/DISCO_H573I.cmake b/targets/upload_method_cfg/DISCO_H573I.cmake new file mode 100644 index 00000000000..8449d04c577 --- /dev/null +++ b/targets/upload_method_cfg/DISCO_H573I.cmake @@ -0,0 +1,45 @@ +# Mbed OS upload method configuration file for target DISCO_H573I +# To change any of these parameters from their default values, set them in your build script between where you +# include app.cmake and where you add mbed os as a subdirectory. + +# Notes: +# 1. Using the JLINK upload method with your dev board requires converting its ST-LINK into a J-Link. See here for details: https://www.segger.com/products/debug-probes/j-link/models/other-j-links/st-link-on-board/ + +# General config parameters +# ------------------------------------------------------------- +set(UPLOAD_METHOD_DEFAULT MBED) + +# Config options for MBED +# ------------------------------------------------------------- + +set(MBED_UPLOAD_ENABLED TRUE) +set(MBED_RESET_BAUDRATE 115200) + +# Config options for JLINK +# ------------------------------------------------------------- + +set(JLINK_UPLOAD_ENABLED TRUE) +set(JLINK_CPU_NAME STM32H573II) +set(JLINK_CLOCK_SPEED 4000) +set(JLINK_UPLOAD_INTERFACE SWD) + +# Config options for PYOCD +# ------------------------------------------------------------- + +set(PYOCD_UPLOAD_ENABLED TRUE) +set(PYOCD_TARGET_NAME stm32h573iikxq) +set(PYOCD_CLOCK_SPEED 4000k) + +# Config options for STM32Cube +# ------------------------------------------------------------- + +set(STM32CUBE_UPLOAD_ENABLED TRUE) +set(STM32CUBE_CONNECT_COMMAND -c port=SWD reset=HWrst) +set(STM32CUBE_GDBSERVER_ARGS --swd) + +# Config options for stlink +# ------------------------------------------------------------- + +set(STLINK_UPLOAD_ENABLED TRUE) +set(STLINK_LOAD_ADDRESS 0x8000000) +set(STLINK_ARGS --connect-under-reset) \ No newline at end of file From 20ca5c5018f3e82c0ad74cd112b9dcc71e85bc98 Mon Sep 17 00:00:00 2001 From: wdx04 Date: Sat, 6 Sep 2025 12:45:50 +0800 Subject: [PATCH 11/15] update linker script --- .../TOOLCHAIN_GCC_ARM/STM32H573xI.ld | 22 ++++++------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/STM32H573xI.ld b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/STM32H573xI.ld index 0418ceaba8a..0baa40c24d0 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/STM32H573xI.ld +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/STM32H573xI.ld @@ -34,15 +34,6 @@ #include "../cmsis_nvic.h" - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - M_CRASH_DATA_RAM_SIZE = 0x100; #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) @@ -51,14 +42,15 @@ M_CRASH_DATA_RAM_SIZE = 0x100; #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 #endif -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) +/* Round up MBED_VECTTABLE_RAM_SIZE to 8 bytes */ +#define MBED_VECTTABLE_RAM_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) /* Memories definition */ MEMORY { - RAM (xrw) : ORIGIN = (MBED_RAM_START + VECTORS_SIZE), LENGTH = (MBED_RAM_SIZE - VECTORS_SIZE) - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (xrw) : ORIGIN = MBED_CONFIGURED_RAM_BANK_SRAM1_2_3_START + MBED_VECTTABLE_RAM_SIZE, LENGTH = MBED_CONFIGURED_RAM_BANK_SRAM1_2_3_SIZE - MBED_VECTTABLE_RAM_SIZE + FLASH (rx) : ORIGIN = MBED_CONFIGURED_ROM_BANK_Flash_START, LENGTH = MBED_CONFIGURED_ROM_BANK_Flash_SIZE + SRAM_BKUP (rw) : ORIGIN = MBED_CONFIGURED_RAM_BANK_SRAM_BKUP_START, LENGTH = MBED_CONFIGURED_RAM_BANK_SRAM_BKUP_SIZE } /* Entry Point */ @@ -120,7 +112,7 @@ SECTIONS . = ALIGN(8); __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ } > RAM - + .data : AT (__etext) { __data_start__ = .; @@ -155,7 +147,7 @@ SECTIONS _edata = .; } > RAM - + .bss : { . = ALIGN(8); From 14b0344e51a6a958dda7eebc476948ed20cfdc88 Mon Sep 17 00:00:00 2001 From: wdx04 <25487439@qq.com> Date: Tue, 9 Sep 2025 19:34:25 +0800 Subject: [PATCH 12/15] fix issues found in the review --- .../TARGET_DISCO_H573I/stm32h5_eth_init.c | 4 +-- .../include/OSPIF/OSPIFBlockDevice.h | 16 ++++------ .../source/OSPIFBlockDevice.cpp | 5 +-- .../TARGET_STM32H573xI/cmsis_nvic.h | 31 +------------------ 4 files changed, 12 insertions(+), 44 deletions(-) diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/TARGET_DISCO_H573I/stm32h5_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/TARGET_DISCO_H573I/stm32h5_eth_init.c index 532b41e5d98..8746e869026 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/TARGET_DISCO_H573I/stm32h5_eth_init.c +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H5/TARGET_DISCO_H573I/stm32h5_eth_init.c @@ -34,8 +34,8 @@ /** * Override HAL Eth Init function. - * - * Note: This was copied from HAL_ETH_MspInit() in a project for the NUCLEO-H563ZI in STM32CubeIDE + * + * Note: This was copied from HAL_ETH_MspInit() in a project for the DISCO-H573I in STM32CubeIDE */ void EthInitPinmappings(void) { diff --git a/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h index d25559cd4ab..915267c7fb1 100644 --- a/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h +++ b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h @@ -104,16 +104,6 @@ enum ospif_polarity_mode { OSPIF_POLARITY_MODE_1 /* CPOL=1, CPHA=1 */ }; -/** Enum ospif soft reset modes - * - * @enum ospif_soft_reset_mode - */ -enum ospif_soft_reset_mode { - OSPIF_SOFT_RESET_UNSUPPORTED = 0, /* Soft reset not supported */ - OSPIF_DIERCT_SOFT_RESET, /* Direct soft reset mode */ - OSPIF_ENABLE_AND_SOFT_RESET /* Enable and soft reset mode */ -}; - #define OSPIF_MAX_ACTIVE_FLASH_DEVICES 10 /** BlockDevice for SFDP based flash devices over OSPI bus @@ -418,6 +408,12 @@ class OSPIFBlockDevice : public mbed::BlockDevice { OSPIF_BP_CLEAR_SR, // Clear protection bits in status register 1 }; + enum ospif_soft_reset_mode { + OSPIF_SOFT_RESET_UNSUPPORTED = 0, // Soft reset not supported + OSPIF_DIRECT_SOFT_RESET, // Direct soft reset mode + OSPIF_ENABLE_AND_SOFT_RESET // Enable and soft reset mode + }; + // OSPI Driver Object mbed::OSPI _ospi; diff --git a/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp b/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp index 12b595394e1..825faa0cb98 100644 --- a/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp +++ b/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp @@ -1334,7 +1334,7 @@ int OSPIFBlockDevice::_sfdp_detect_reset_protocol_and_reset(uint8_t *basic_param #endif #if !MBED_CONF_OSPIF_ENABLE_AND_RESET // i.e. direct reset, or determined from SFDP - _soft_reset_mode = OSPIF_DIERCT_SOFT_RESET; + _soft_reset_mode = OSPIF_DIRECT_SOFT_RESET; #endif #if RESET_SEQUENCE_FROM_SFDP @@ -1348,6 +1348,7 @@ int OSPIFBlockDevice::_sfdp_detect_reset_protocol_and_reset(uint8_t *basic_param #if RESET_SEQUENCE_FROM_SFDP } else { // Soft reset either is not supported or requires direct control over data lines + tr_error("Failed to determine soft reset sequence. If your device has a legacy SFDP table, please manually set enable-and-reset or direct-reset."); _soft_reset_mode = OSPIF_SOFT_RESET_UNSUPPORTED; } #endif @@ -1364,7 +1365,7 @@ int OSPIFBlockDevice::_soft_reset() case OSPIF_SOFT_RESET_UNSUPPORTED: status = OSPIF_BD_ERROR_PARSING_FAILED; break; - case OSPIF_DIERCT_SOFT_RESET: + case OSPIF_DIRECT_SOFT_RESET: // Issue instruction 0xF0 to reset the device ospi_status = _ospi_send_general_command(0xF0, OSPI_NO_ADDRESS_COMMAND, // Send reset instruction NULL, 0, NULL, 0); diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/cmsis_nvic.h index cca89047222..57e35d0f8f2 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/cmsis_nvic.h @@ -17,36 +17,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if !defined(TRUST_ZONE) -#if !defined(MBED_ROM_START) -#define MBED_ROM_START 0x8000000 -#endif -#else -#if !defined(MBED_ROM_START) -#define MBED_ROM_START 0xC000000 -#endif -#endif //TRUST_ZONE - -#if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x200000 // 2.0 MB -#endif - -#if !defined(TRUST_ZONE) -#if !defined(MBED_RAM_START) -#define MBED_RAM_START 0x20000000 -#endif -#else -#if !defined(MBED_RAM_START) -#define MBED_RAM_START 0x30000000 -#endif -#endif //TRUST_ZONE - -#if !defined(MBED_RAM_SIZE) -//256K SRAM1 + 64K SRAM2 + 320K SRAM3 = 640KB -#define MBED_RAM_SIZE 0xA0000 -#endif - #define NVIC_NUM_VECTORS 147 -#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START +#define NVIC_RAM_VECTOR_ADDRESS MBED_CONFIGURED_RAM_BANK_SRAM1_2_3_START #endif From b89e23e2790674c100c4ec1829002af10b0ad863 Mon Sep 17 00:00:00 2001 From: wdx04 <25487439@qq.com> Date: Wed, 10 Sep 2025 23:01:36 +0800 Subject: [PATCH 13/15] unified the linker script for STM32H563x and STM32H57x moved all linker scripts of STM32H5 to the linker_scripts folder fixed issues found in the review --- .../TARGET_STM/TARGET_STM32H5/CMakeLists.txt | 3 + .../TARGET_STM32H503xB/CMakeLists.txt | 2 - .../TARGET_STM32H563xI/CMakeLists.txt | 2 - .../TOOLCHAIN_GCC_ARM/STM32H563xI.ld | 197 ------------------ .../TARGET_STM32H563xI/cmsis_nvic.h | 31 +-- .../TARGET_STM32H573xI/CMakeLists.txt | 2 - .../linker_scripts/CMakeLists.txt | 5 + .../STM32H503_FAMILY/CMakeLists.txt | 5 + .../STM32H503_FAMILY}/STM32H503xB.ld | 2 +- .../CMakeLists.txt | 6 + .../STM32H56x_STM32H57x.ld} | 47 ++--- .../TARGET_STM/TARGET_STM32H5/stm_dma_info.h | 2 + targets/TARGET_STM/ospi_api.c | 2 +- targets/TARGET_STM/qspi_api.c | 2 +- targets/upload_method_cfg/DISCO_H573I.cmake | 5 +- 15 files changed, 43 insertions(+), 270 deletions(-) delete mode 100644 targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H563xI/TOOLCHAIN_GCC_ARM/STM32H563xI.ld create mode 100644 targets/TARGET_STM/TARGET_STM32H5/linker_scripts/CMakeLists.txt create mode 100644 targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H503_FAMILY/CMakeLists.txt rename targets/TARGET_STM/TARGET_STM32H5/{TARGET_STM32H503xB/TOOLCHAIN_GCC_ARM => linker_scripts/STM32H503_FAMILY}/STM32H503xB.ld (99%) create mode 100644 targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H56x_STM32H57x_FAMILIES/CMakeLists.txt rename targets/TARGET_STM/TARGET_STM32H5/{TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/STM32H573xI.ld => linker_scripts/STM32H56x_STM32H57x_FAMILIES/STM32H56x_STM32H57x.ld} (77%) diff --git a/targets/TARGET_STM/TARGET_STM32H5/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H5/CMakeLists.txt index 43280770fb0..0fb25875a95 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H5/CMakeLists.txt @@ -28,3 +28,6 @@ target_include_directories(mbed-stm32h5 ) target_link_libraries(mbed-stm32h5 INTERFACE mbed-stm mbed-stm32h5cube-fw) + +# Add linker scripts +add_subdirectory(linker_scripts) diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H503xB/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H503xB/CMakeLists.txt index 8dbfdfbffea..fe2acc282ca 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H503xB/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H503xB/CMakeLists.txt @@ -23,6 +23,4 @@ target_include_directories(mbed-stm32h503xb . ) -mbed_set_linker_script(mbed-stm32h503xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h503xb INTERFACE mbed-stm32h5) diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H563xI/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H563xI/CMakeLists.txt index c996e59f897..6a8505d4b95 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H563xI/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H563xI/CMakeLists.txt @@ -23,6 +23,4 @@ target_include_directories(mbed-stm32h563xi . ) -mbed_set_linker_script(mbed-stm32h563xi ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h563xi INTERFACE mbed-stm32h5) diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H563xI/TOOLCHAIN_GCC_ARM/STM32H563xI.ld b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H563xI/TOOLCHAIN_GCC_ARM/STM32H563xI.ld deleted file mode 100644 index 244efe00090..00000000000 --- a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H563xI/TOOLCHAIN_GCC_ARM/STM32H563xI.ld +++ /dev/null @@ -1,197 +0,0 @@ -/* -****************************************************************************** -** -** @file : LinkerScript.ld -** -** @author : Auto-generated by STM32CubeIDE -** -** @brief : Linker script for STM32H563ZITx Device from STM32H5 series -** 2Mbytes FLASH -** 640Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -****************************************************************************** -** @attention -** -** Copyright (c) 2023 STMicroelectronics. -** All rights reserved. -** -** This software is licensed under terms that can be found in the LICENSE file -** in the root directory of this software component. -** If no LICENSE file comes with this software, it is provided AS-IS. -** -****************************************************************************** -*/ - -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -M_CRASH_DATA_RAM_SIZE = 0x100; - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) - -/* Memories definition */ -MEMORY -{ - RAM (xrw) : ORIGIN = (MBED_RAM_START + VECTORS_SIZE), LENGTH = (MBED_RAM_SIZE - VECTORS_SIZE) - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE -} - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Sections */ -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - _sidata = .; - - .crash_data_ram : - { - . = ALIGN(8); - __CRASH_DATA_RAM__ = .; - __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ - KEEP(*(.keep.crash_data_ram)) - *(.m_crash_data_ram) /* This is a user defined section */ - . += M_CRASH_DATA_RAM_SIZE; - . = ALIGN(8); - __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ - } > RAM - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H563xI/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H563xI/cmsis_nvic.h index cca89047222..57e35d0f8f2 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H563xI/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H563xI/cmsis_nvic.h @@ -17,36 +17,7 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#if !defined(TRUST_ZONE) -#if !defined(MBED_ROM_START) -#define MBED_ROM_START 0x8000000 -#endif -#else -#if !defined(MBED_ROM_START) -#define MBED_ROM_START 0xC000000 -#endif -#endif //TRUST_ZONE - -#if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x200000 // 2.0 MB -#endif - -#if !defined(TRUST_ZONE) -#if !defined(MBED_RAM_START) -#define MBED_RAM_START 0x20000000 -#endif -#else -#if !defined(MBED_RAM_START) -#define MBED_RAM_START 0x30000000 -#endif -#endif //TRUST_ZONE - -#if !defined(MBED_RAM_SIZE) -//256K SRAM1 + 64K SRAM2 + 320K SRAM3 = 640KB -#define MBED_RAM_SIZE 0xA0000 -#endif - #define NVIC_NUM_VECTORS 147 -#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START +#define NVIC_RAM_VECTOR_ADDRESS MBED_CONFIGURED_RAM_BANK_SRAM1_2_3_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/CMakeLists.txt index 7409ab9d94c..c96de0df295 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/CMakeLists.txt @@ -20,6 +20,4 @@ target_include_directories(mbed-stm32h573xi . ) -mbed_set_linker_script(mbed-stm32h573xi ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) - target_link_libraries(mbed-stm32h573xi INTERFACE mbed-stm32h5) diff --git a/targets/TARGET_STM/TARGET_STM32H5/linker_scripts/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H5/linker_scripts/CMakeLists.txt new file mode 100644 index 00000000000..20e5fe23d43 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H5/linker_scripts/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Jamie Smith +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(STM32H503_FAMILY) +add_subdirectory(STM32H56x_STM32H57x_FAMILIES) \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H503_FAMILY/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H503_FAMILY/CMakeLists.txt new file mode 100644 index 00000000000..83da6b6c43e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H503_FAMILY/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Jamie Smith +# SPDX-License-Identifier: Apache-2.0 +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + mbed_set_linker_script(mbed-stm32h503xb STM32H503xB.ld) +endif() diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H503xB/TOOLCHAIN_GCC_ARM/STM32H503xB.ld b/targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H503_FAMILY/STM32H503xB.ld similarity index 99% rename from targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H503xB/TOOLCHAIN_GCC_ARM/STM32H503xB.ld rename to targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H503_FAMILY/STM32H503xB.ld index 38ab99a84dd..7ad8b4823af 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H503xB/TOOLCHAIN_GCC_ARM/STM32H503xB.ld +++ b/targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H503_FAMILY/STM32H503xB.ld @@ -32,7 +32,7 @@ ****************************************************************************** */ -#include "../cmsis_nvic.h" +#include "cmsis_nvic.h" #if !defined(MBED_APP_START) diff --git a/targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H56x_STM32H57x_FAMILIES/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H56x_STM32H57x_FAMILIES/CMakeLists.txt new file mode 100644 index 00000000000..82f35b31b59 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H56x_STM32H57x_FAMILIES/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Jamie Smith +# SPDX-License-Identifier: Apache-2.0 +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + mbed_set_linker_script(mbed-stm32h563xi STM32H56x_STM32H57x.ld) + mbed_set_linker_script(mbed-stm32h573xi STM32H56x_STM32H57x.ld) +endif() diff --git a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/STM32H573xI.ld b/targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H56x_STM32H57x_FAMILIES/STM32H56x_STM32H57x.ld similarity index 77% rename from targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/STM32H573xI.ld rename to targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H56x_STM32H57x_FAMILIES/STM32H56x_STM32H57x.ld index 0baa40c24d0..dce2884a86d 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/TARGET_STM32H573xI/TOOLCHAIN_GCC_ARM/STM32H573xI.ld +++ b/targets/TARGET_STM/TARGET_STM32H5/linker_scripts/STM32H56x_STM32H57x_FAMILIES/STM32H56x_STM32H57x.ld @@ -1,38 +1,21 @@ +/* Linker script to configure memory regions. */ /* -****************************************************************************** -** -** @file : LinkerScript.ld -** -** @author : Auto-generated by STM32CubeIDE -** -** @brief : Linker script for STM32H573ZITx Device from STM32H5 series -** 2Mbytes FLASH -** 640Kbytes RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used -** -** Target : STMicroelectronics STM32 -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -****************************************************************************** -** @attention -** -** Copyright (c) 2023 STMicroelectronics. -** All rights reserved. -** -** This software is licensed under terms that can be found in the LICENSE file -** in the root directory of this software component. -** If no LICENSE file comes with this software, it is provided AS-IS. -** -****************************************************************************** + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2025 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** */ -#include "../cmsis_nvic.h" +#include "cmsis_nvic.h" M_CRASH_DATA_RAM_SIZE = 0x100; diff --git a/targets/TARGET_STM/TARGET_STM32H5/stm_dma_info.h b/targets/TARGET_STM/TARGET_STM32H5/stm_dma_info.h index 521387dfcd6..c9c421d7fe2 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/stm_dma_info.h +++ b/targets/TARGET_STM/TARGET_STM32H5/stm_dma_info.h @@ -57,9 +57,11 @@ static const DMALinkInfo SPIRxDMALinks[] = { }; /// Mapping from OSPI index to DMA link info +#ifdef OCTOSPI1 static const DMALinkInfo OSPIDMALinks[] = { {2, 4, GPDMA2_REQUEST_OCTOSPI1}, {2, 5, GPDMA2_REQUEST_OCTOSPI1}, }; +#endif #endif //MBED_OS_STM_DMA_INFO_H diff --git a/targets/TARGET_STM/ospi_api.c b/targets/TARGET_STM/ospi_api.c index 2f073f1ae8d..0946f8e6f2d 100644 --- a/targets/TARGET_STM/ospi_api.c +++ b/targets/TARGET_STM/ospi_api.c @@ -41,7 +41,7 @@ /* Minimum number of bytes to be transferred using DMA, when DCACHE is not available */ /* When less than 32 bytes of data is transferred at a time, using DMA may actually be slower than polling */ -/* When DACHE is available, DMA will be used when the buffer contains at least one cache-aligned block */ +/* When DCACHE is available, DMA will be used when the buffer contains at least one cache-aligned block */ #define OSPI_DMA_THRESHOLD_BYTES 32 // Stored pointer inside OSPI handle is ospi_s* diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c index b6301f64f21..636d3558021 100644 --- a/targets/TARGET_STM/qspi_api.c +++ b/targets/TARGET_STM/qspi_api.c @@ -45,7 +45,7 @@ /* Minimum number of bytes to be transferred using DMA, when DCACHE is not available */ /* When less than 32 bytes of data is transferred at a time, using DMA may actually be slower than polling */ -/* When DACHE is available, DMA will be used when the buffer contains at least one cache-aligned block */ +/* When DCACHE is available, DMA will be used when the buffer contains at least one cache-aligned block */ #define QSPI_DMA_THRESHOLD_BYTES 32 #if defined(QUADSPI) diff --git a/targets/upload_method_cfg/DISCO_H573I.cmake b/targets/upload_method_cfg/DISCO_H573I.cmake index 8449d04c577..40f108254c1 100644 --- a/targets/upload_method_cfg/DISCO_H573I.cmake +++ b/targets/upload_method_cfg/DISCO_H573I.cmake @@ -3,7 +3,8 @@ # include app.cmake and where you add mbed os as a subdirectory. # Notes: -# 1. Using the JLINK upload method with your dev board requires converting its ST-LINK into a J-Link. See here for details: https://www.segger.com/products/debug-probes/j-link/models/other-j-links/st-link-on-board/ +# 1. If your target is not natively supported by the pyOCD, then you need install a keil package for family of your target by hands. Type "pyocd pack show" to console and you will see a list of already installed packages. +# - If any package for your family is not on the list, then you need install them via command "pyocd pack install stm32h5" (take long time).Then just type "pyocd pack find STM32h5" or "pyocd pack find STM32h563" and you will see the part name of your target. # General config parameters # ------------------------------------------------------------- @@ -18,7 +19,7 @@ set(MBED_RESET_BAUDRATE 115200) # Config options for JLINK # ------------------------------------------------------------- -set(JLINK_UPLOAD_ENABLED TRUE) +set(JLINK_UPLOAD_ENABLED FALSE) set(JLINK_CPU_NAME STM32H573II) set(JLINK_CLOCK_SPEED 4000) set(JLINK_UPLOAD_INTERFACE SWD) From e7b3a9b732a858c9405872aa34e922c9eccfb492 Mon Sep 17 00:00:00 2001 From: wdx04 <25487439@qq.com> Date: Thu, 11 Sep 2025 23:29:49 +0800 Subject: [PATCH 14/15] add reference to errata sheet --- targets/TARGET_STM/TARGET_STM32H5/flash_api.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H5/flash_api.c b/targets/TARGET_STM/TARGET_STM32H5/flash_api.c index 41f8c8975e0..1e70dfd8c31 100644 --- a/targets/TARGET_STM/TARGET_STM32H5/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32H5/flash_api.c @@ -107,7 +107,8 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) /* Clear error programming flags */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); - /* Increase Flash latency while programming */ + /* Increase Flash latency while programming + * Refer to STM32H562xx/563xx/573xx errata sheet, section 2.2.9 for more details */ __HAL_FLASH_SET_LATENCY(6); /* MBED HAL erases 1 page / sector at a time */ @@ -176,7 +177,8 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, /* Clear error programming flags */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); - /* Increase Flash latency while programming */ + /* Increase Flash latency while programming + * Refer to STM32H562xx/563xx/573xx errata sheet, section 2.2.9 for more details */ __HAL_FLASH_SET_LATENCY(6); /* Program the user Flash area word by word */ From 3eee003f57275b17efa78d59daca51af70e2e35b Mon Sep 17 00:00:00 2001 From: wdx04 <25487439@qq.com> Date: Tue, 16 Sep 2025 22:58:28 +0800 Subject: [PATCH 15/15] fix some comments in ospi_api.c and qspi_api.c --- targets/TARGET_STM/ospi_api.c | 2 +- targets/TARGET_STM/qspi_api.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/ospi_api.c b/targets/TARGET_STM/ospi_api.c index 0946f8e6f2d..f9dfa83b1c0 100644 --- a/targets/TARGET_STM/ospi_api.c +++ b/targets/TARGET_STM/ospi_api.c @@ -640,7 +640,7 @@ ospi_status_t ospi_write(ospi_t *obj, const ospi_command_t *command, const void NVIC_SetPriority(obj->ospiIRQ, 1); NVIC_EnableIRQ(obj->ospiIRQ); #if defined(__DCACHE_PRESENT) - // For chips with a cache (e.g. Cortex-M7), we need to evict the Tx fill data from cache to main memory. + // For chips with a cache (e.g. Cortex-M7), we need to evict the Tx data from cache to main memory. // This ensures that the DMA controller can see the most up-to-date copy of the data. SCB_CleanDCache_by_Addr((volatile void *)data, *length); #endif diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c index 636d3558021..0b3918ab6b1 100644 --- a/targets/TARGET_STM/qspi_api.c +++ b/targets/TARGET_STM/qspi_api.c @@ -1089,7 +1089,7 @@ qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void NVIC_SetPriority(obj->qspiIRQ, 1); NVIC_EnableIRQ(obj->qspiIRQ); #if defined(__DCACHE_PRESENT) - // For chips with a cache (e.g. Cortex-M7), we need to evict the Tx fill data from cache to main memory. + // For chips with a cache (e.g. Cortex-M7), we need to evict the Tx data from cache to main memory. // This ensures that the DMA controller can see the most up-to-date copy of the data. SCB_CleanDCache_by_Addr((volatile void *)data, *length); #endif @@ -1143,7 +1143,7 @@ qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void NVIC_SetPriority(QUADSPI_IRQn, 1); NVIC_EnableIRQ(QUADSPI_IRQn); #if defined(__DCACHE_PRESENT) - // For chips with a cache (e.g. Cortex-M7), we need to evict the Tx fill data from cache to main memory. + // For chips with a cache (e.g. Cortex-M7), we need to evict the Tx data from cache to main memory. // This ensures that the DMA controller can see the most up-to-date copy of the data. SCB_CleanDCache_by_Addr((volatile void *)data, *length); #endif