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[Test][GPU] Add MMA tests for RDNA3 WMMA validation (FP16/BF16)
Add WMMA tests for GPUs: - test_mma_fp16_fp32.mojo: FP16×FP16+FP32→FP32 MMA operations - test_mma_bf16_fp32.mojo: BF16×BF16+FP32→FP32 MMA operations These tests validate that the mma() intrinsic correctly lowers to hardware instructions across all GPU architectures. The BF16 tests are critical for modern LLM inference. This also allows us to easily verify an existing RDNA3 LLVM WMMA Bug: RDNA3 WMMA instructions originally worked fine when first added to LLVM (June 2022, commit 4874838a63fb), but broke in January 2024 when GFX12 WMMA support was added (commit 7fdf608cefa0). The bug has been sitting in upstream LLVM for 22 months affecting compute kernels (amdgpu_kernel calling convention). Graphics shaders (amdgpu_ps) kept working fine, which is probably why nobody noticed. AMD's ROCm LLVM fork (TheRock) does not have this bug as they use modified pattern classes to handle bare operands. ROCm users can use RDNA3 WMMA without issues. The root cause was TableGen patterns expected VOP3PMods wrappers, but compute kernel intrinsic calls are bare. LLVM commit 7fdf608cefa0 broke this while while graphics paths worked. However this also has implicications for Mojo's LLVM and RDNA support. This test confirms that Mojo 25.5.0's LLVM also has this bug. I've attempted workaround via `mojo build -o llvm` + fixed external llc, but compilation fails during IR generation, preventing IR extraction. A workaround was thus not viable and would not be upstreamable anyway. This requires an upstream LLVM fix, which has been submitted and could be evaluated to be backported onto Modular's LLVM: llvm/llvm-project#164036 The fix adds 60 high-priority patterns covering all 4 WMMA variants (FP16, BF16, INT8, INT4) for both Wave32 and Wave64 modes. Because the test does not work on RDNA3 the test is marked incompatible pending Modular's LLVM compiler also gets fixed accordingly. We can remove this incompatible constraint once we have this fixed. Once fixed, this test will work on: - NVIDIA GPUs: Uses tensor core wmma instructions (works now) - AMD CDNA GPUs: Uses v_mfma instructions (works now) - AMD RDNA3+ GPUs with ROCm: Uses v_wmma instructions (works now) - AMD RDNA3+ GPUs with upstream LLVM: Uses v_wmma instructions (requires fix) - AMD RDNA1/2: Falls back to scalar operations With the LLVM fix is merged, it should have a positive prformance impact on RDNA3: - Before: ~100 GFLOPS (scalar fallback) - After: ~1000+ GFLOPS (native WMMA) - Speedup: 10-16× for FP16/BF16 matrix operations
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‎max/kernels/test/gpu/basics/BUILD.bazel‎

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@@ -93,6 +93,12 @@ _EXTRA_CONSTRAINTS = {
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"//:apple_gpu": ["@platforms//:incompatible"],
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"//conditions:default": [],
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}), # FIXME: MOCO-2397
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# RDNA3 (GFX11) WMMA tests - Disabled due to LLVM bug
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# Bug: LLVM 15.0.0-22.0.0git cannot select WMMA intrinsics for compute kernels
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# Status: Fix ready for LLVM upstream (Oct 2025), waiting for Mojo LLVM upgrade
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# Details: See /data/modular/RDNA3_WMMA_PROJECT_STATUS.md
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"test_mma_fp16_fp32.mojo": ["@platforms//:incompatible"], # FIXME: https://github.com/llvm/llvm-project/pull/164036
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"test_mma_bf16_fp32.mojo": ["@platforms//:incompatible"], # FIXME: https://github.com/llvm/llvm-project/pull/164036
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}
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‎max/kernels/test/gpu/basics/test_mma_bf16_fp32.mojo‎

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# ===----------------------------------------------------------------------=== #
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# Copyright (c) 2025, Modular Inc. All rights reserved.
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#
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# Licensed under the Apache License v2.0 with LLVM Exceptions:
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# https://llvm.org/LICENSE.txt
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# ===----------------------------------------------------------------------=== #
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from gpu.host import DeviceContext
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from gpu.mma import mma
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from testing import assert_equal
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fn test_mma_bf16_kernel(c_ptr: UnsafePointer[Float32]):
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"""BF16×BF16+FP32→FP32 MMA test kernel.
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This test performs matrix multiply-accumulate using BF16 inputs and FP32
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accumulator. BFloat16 (BF16) is critical for modern LLM inference as it's
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used in Llama 3, Mixtral, and most contemporary transformer models.
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On different GPU architectures, this operation maps to:
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- NVIDIA: Uses tensor core wmma or mma.sync instructions
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- AMD CDNA: Uses mfma instructions
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- AMD RDNA3+: Uses v_wmma_f32_16x16x16_bf16 instructions
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- AMD RDNA1/2: Falls back to scalar operations (no WMMA support)
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IMPORTANT - RDNA3 WMMA Bug (Fixed October 2025):
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RDNA3 WMMA instructions were broken in all LLVM versions 15.0.0-22.0.0git
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for compute kernels (amdgpu_kernel calling convention). Graphics shaders
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worked, but HIP/ROCm compute kernels failed with "Cannot select intrinsic".
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Mojo 25.5.0's LLVM confirmed to have this bug - using `mojo build -o llvm`
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fails during IR generation, preventing workarounds via external llc.
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LLVM Fix Status:
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Submitted upstream: https://github.com/llvm/llvm-project/pull/164036
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Expected path: Modular will backport fix to Mojo's LLVM
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This test requires either:
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1. LLVM 23+ with upstreamed fix (after PR merges), OR
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2. Mojo's LLVM with backported fix (expected), OR
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3. ROCm's LLVM (TheRock) which already has the fix
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See RDNA3_WMMA_PROJECT_STATUS.md for complete details.
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The test validates that the mma() intrinsic correctly lowers to
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appropriate hardware instructions for the target platform.
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Why BF16 is Important:
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BF16 maintains FP32's exponent range while using half the bits, making
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it ideal for deep learning. Major models using BF16:
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- Meta Llama 3.1/3.2 (8B, 70B, 405B)
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- Mistral 7B v0.3 / Mixtral 8x7B / 8x22B
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- Google Gemma 2B/7B
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- IBM Granite 3.0 8B/20B
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Args:
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c_ptr: Output buffer for results (4 FP32 values).
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"""
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var a_reg = SIMD[DType.bfloat16, 4](1.0, 2.0, 3.0, 4.0)
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var b_reg = SIMD[DType.bfloat16, 4](1.0, 1.0, 1.0, 1.0)
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var c_reg = SIMD[DType.float32, 4](0.0, 0.0, 0.0, 0.0)
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var d_reg = SIMD[DType.float32, 4](0.0, 0.0, 0.0, 0.0)
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mma(d_reg, a_reg, b_reg, c_reg)
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c_ptr[0] = d_reg[0]
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c_ptr[1] = d_reg[1]
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c_ptr[2] = d_reg[2]
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c_ptr[3] = d_reg[3]
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def main():
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"""Test BF16 matrix multiply-accumulate operation."""
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with DeviceContext() as ctx:
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var c_device = ctx.enqueue_create_buffer[DType.float32](4)
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var c_host = UnsafePointer[Float32].alloc(4)
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for i in range(4):
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c_host[i] = -1.0
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ctx.enqueue_copy(c_device, c_host)
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alias kernel = test_mma_bf16_kernel
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ctx.enqueue_function_checked[kernel, kernel](
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c_device,
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grid_dim=1,
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block_dim=64,
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)
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ctx.enqueue_copy(c_host, c_device)
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ctx.synchronize()
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for i in range(4):
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assert_equal(c_host[i] != -1.0, True)
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_ = c_device
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c_host.free()

‎max/kernels/test/gpu/basics/test_mma_fp16_fp32.mojo‎

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# ===----------------------------------------------------------------------=== #
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# Copyright (c) 2025, Modular Inc. All rights reserved.
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#
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# Licensed under the Apache License v2.0 with LLVM Exceptions:
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# https://llvm.org/LICENSE.txt
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# ===----------------------------------------------------------------------=== #
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from gpu.host import DeviceContext
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from gpu.mma import mma
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from testing import assert_equal
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fn test_mma_fp16_kernel(c_ptr: UnsafePointer[Float32]):
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"""Simple FP16×FP16+FP32→FP32 MMA test kernel.
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This test performs a basic matrix multiply-accumulate operation using
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FP16 inputs and FP32 accumulator. On different GPU architectures, this
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operation maps to:
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- NVIDIA: Uses tensor core wmma or mma.sync instructions
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- AMD CDNA: Uses mfma instructions
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- AMD RDNA3+: Uses v_wmma_f32_16x16x16_f16 instructions
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- AMD RDNA1/2: Falls back to scalar operations (no WMMA support)
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IMPORTANT - RDNA3 WMMA Bug (Fixed October 2025):
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RDNA3 WMMA instructions were broken in all LLVM versions 15.0.0-22.0.0git
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for compute kernels (amdgpu_kernel calling convention). Graphics shaders
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worked, but HIP/ROCm compute kernels failed with "Cannot select intrinsic".
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Mojo 25.5.0's LLVM confirmed to have this bug - using `mojo build -o llvm`
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fails during IR generation, preventing workarounds via external llc.
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LLVM Fix Status:
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Submitted upstream: https://github.com/llvm/llvm-project/pull/164036
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Expected path: Modular will backport fix to Mojo's LLVM
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This test requires either:
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1. LLVM 23+ with upstreamed fix (after PR merges), OR
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2. Mojo's LLVM with backported fix (expected), OR
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3. ROCm's LLVM (TheRock) which already has the fix
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See RDNA3_WMMA_PROJECT_STATUS.md for complete details.
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The test validates that the mma() intrinsic correctly lowers to
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appropriate hardware instructions for the target platform.
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Args:
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c_ptr: Output buffer for results (4 FP32 values).
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"""
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var a_reg = SIMD[DType.float16, 4](1.0, 2.0, 3.0, 4.0)
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var b_reg = SIMD[DType.float16, 4](1.0, 1.0, 1.0, 1.0)
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var c_reg = SIMD[DType.float32, 4](0.0, 0.0, 0.0, 0.0)
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var d_reg = SIMD[DType.float32, 4](0.0, 0.0, 0.0, 0.0)
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mma(d_reg, a_reg, b_reg, c_reg)
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c_ptr[0] = d_reg[0]
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c_ptr[1] = d_reg[1]
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c_ptr[2] = d_reg[2]
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c_ptr[3] = d_reg[3]
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def main():
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"""Test FP16 matrix multiply-accumulate operation."""
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with DeviceContext() as ctx:
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var c_device = ctx.enqueue_create_buffer[DType.float32](4)
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var c_host = UnsafePointer[Float32].alloc(4)
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for i in range(4):
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c_host[i] = -1.0
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ctx.enqueue_copy(c_device, c_host)
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alias kernel = test_mma_fp16_kernel
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ctx.enqueue_function_checked[kernel, kernel](
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c_device,
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grid_dim=1,
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block_dim=64,
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)
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ctx.enqueue_copy(c_host, c_device)
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ctx.synchronize()
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for i in range(4):
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assert_equal(c_host[i] != -1.0, True)
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_ = c_device
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c_host.free()

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