rasdaemon: Add support for the CXL memory sparing events

Add support to log the CXL memory sparing events.

Recording of CXL memory sparing events is not enabled because the sparing
event record is used for start the CXL memory sparing operation.

Signed-off-by: Shiju Jose <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>

Author: shijujose4

ras-cxl-handler.c

@@ -1518,3 +1518,157 @@ int ras_cxl_memory_module_event_handler(struct trace_seq *s,
 
 	return 0;
 }
+
+/*
+ * Memory Sparing Event Record - MSER
+ *
+ * CXL rev 3.2 section 8.2.10.2.1.4; Table 8-60
+ */
+#define CXL_MSER_VALID_CHANNEL			BIT(0)
+#define CXL_MSER_VALID_RANK			BIT(1)
+#define CXL_MSER_VALID_NIBBLE			BIT(2)
+#define CXL_MSER_VALID_BANK_GROUP		BIT(3)
+#define CXL_MSER_VALID_BANK			BIT(4)
+#define CXL_MSER_VALID_ROW			BIT(5)
+#define CXL_MSER_VALID_COLUMN			BIT(6)
+#define CXL_MSER_VALID_COMPONENT_ID		BIT(7)
+#define CXL_MSER_VALID_COMPONENT_ID_FORMAT	BIT(8)
+#define CXL_MSER_VALID_SUB_CHANNEL		BIT(9)
+
+#define CXL_MSER_QUERY_RES_FLAG		BIT(0)
+#define CXL_MSER_HARD_SPARING_FLAG	BIT(1)
+#define CXL_MSER_DEV_INITIATED_FLAG	BIT(2)
+
+static const struct cxl_event_flags cxl_mser_flags[] = {
+	{ .bit = CXL_MSER_QUERY_RES_FLAG, .flag = "QUERY_RESOURCES" },
+	{ .bit = CXL_MSER_HARD_SPARING_FLAG, .flag = "HARD_SPARING" },
+	{ .bit = CXL_MSER_DEV_INITIATED_FLAG, .flag = "DEVICE_INITIATED" },
+};
+
+int ras_cxl_memory_sparing_event_handler(struct trace_seq *s,
+					 struct tep_record *record,
+					 struct tep_event *event, void *context)
+{
+	int len, i, rc;
+	unsigned long long val;
+	struct ras_cxl_memory_sparing_event ev;
+
+	memset(&ev, 0, sizeof(ev));
+	if (handle_ras_cxl_common_hdr(s, record, event, context, &ev.hdr) < 0)
+		return -1;
+
+	if (tep_get_field_val(s, event, "flags", record, &val, 1) < 0)
+		return -1;
+	ev.flags = val;
+	if (trace_seq_printf(s, "flags:0x%x ", ev.flags) <= 0)
+		return -1;
+	if (decode_cxl_event_flags(s, ev.flags, cxl_mser_flags,
+				   ARRAY_SIZE(cxl_mser_flags)) < 0)
+		return -1;
+
+	if (tep_get_field_val(s,  event, "result", record, &val, 1) < 0)
+		return -1;
+	ev.result = val;
+	if (trace_seq_printf(s, "result:0x%x ", ev.result) <= 0)
+		return -1;
+
+	if (tep_get_field_val(s,  event, "validity_flags", record, &val, 1) < 0)
+		return -1;
+	ev.validity_flags = val;
+
+	if (tep_get_field_val(s,  event, "res_avail", record, &val, 1) < 0)
+		return -1;
+	ev.res_avail = val;
+	if (trace_seq_printf(s, "spare resources available:%u ", ev.res_avail) <= 0)
+		return -1;
+
+	if (ev.validity_flags & CXL_MSER_VALID_CHANNEL) {
+		if (tep_get_field_val(s,  event, "channel", record, &val, 1) < 0)
+			return -1;
+		ev.channel = val;
+		if (trace_seq_printf(s, "channel:%u ", ev.channel) <= 0)
+			return -1;
+	}
+
+	if (ev.validity_flags & CXL_MSER_VALID_SUB_CHANNEL) {
+		if (tep_get_field_val(s,  event, "sub_channel", record, &val, 1) < 0)
+			return -1;
+		ev.sub_channel = val;
+		if (trace_seq_printf(s, "sub_channel:%u ", ev.sub_channel) <= 0)
+			return -1;
+	}
+
+	if (ev.validity_flags & CXL_MSER_VALID_RANK) {
+		if (tep_get_field_val(s,  event, "rank", record, &val, 1) < 0)
+			return -1;
+		ev.rank = val;
+		if (trace_seq_printf(s, "rank:%u ", ev.rank) <= 0)
+			return -1;
+	}
+
+	if (ev.validity_flags & CXL_MSER_VALID_NIBBLE) {
+		if (tep_get_field_val(s,  event, "nibble_mask", record, &val, 1) < 0)
+			return -1;
+		ev.nibble_mask = val;
+		if (trace_seq_printf(s, "nibble_mask:%u ", ev.nibble_mask) <= 0)
+			return -1;
+	}
+
+	if (ev.validity_flags & CXL_MSER_VALID_BANK_GROUP) {
+		if (tep_get_field_val(s,  event, "bank_group", record, &val, 1) < 0)
+			return -1;
+		ev.bank_group = val;
+		if (trace_seq_printf(s, "bank_group:%u ", ev.bank_group) <= 0)
+			return -1;
+	}
+
+	if (ev.validity_flags & CXL_MSER_VALID_BANK) {
+		if (tep_get_field_val(s,  event, "bank", record, &val, 1) < 0)
+			return -1;
+		ev.bank = val;
+		if (trace_seq_printf(s, "bank:%u ", ev.bank) <= 0)
+			return -1;
+	}
+
+	if (ev.validity_flags & CXL_MSER_VALID_ROW) {
+		if (tep_get_field_val(s,  event, "row", record, &val, 1) < 0)
+			return -1;
+		ev.row = val;
+		if (trace_seq_printf(s, "row:%u ", ev.row) <= 0)
+			return -1;
+	}
+
+	if (ev.validity_flags & CXL_MSER_VALID_COLUMN) {
+		if (tep_get_field_val(s,  event, "column", record, &val, 1) < 0)
+			return -1;
+		ev.column = val;
+		if (trace_seq_printf(s, "column:%u ", ev.column) <= 0)
+			return -1;
+	}
+
+	if (ev.validity_flags & CXL_MSER_VALID_COMPONENT_ID) {
+		ev.comp_id = tep_get_field_raw(s, event, "comp_id", record, &len, 1);
+		if (!ev.comp_id)
+			return -1;
+		if (trace_seq_printf(s, "comp_id:") <= 0)
+			return -1;
+		for (i = 0; i < CXL_EVENT_GEN_MED_COMP_ID_SIZE; i++) {
+			if (trace_seq_printf(s, "%02x ", ev.comp_id[i]) <= 0)
+				break;
+		}
+
+		if (ev.validity_flags & CXL_MSER_VALID_COMPONENT_ID_FORMAT) {
+			if (trace_seq_printf(s, "comp_id_pldm_valid_flags:") <= 0)
+				return -1;
+			if (decode_cxl_event_flags(s, ev.comp_id[0], cxl_pldm_comp_id_flags,
+						   ARRAY_SIZE(cxl_pldm_comp_id_flags)) < 0)
+				return -1;
+
+			rc = ras_cxl_print_component_id(s, ev.comp_id, ev.entity_id, ev.res_id);
+			if (rc)
+				return rc;
+		}
+	}
+
+	return 0;
+}

ras-cxl-handler.h

@@ -37,4 +37,7 @@ int ras_cxl_dram_event_handler(struct trace_seq *s,
 int ras_cxl_memory_module_event_handler(struct trace_seq *s,
 					struct tep_record *record,
 					struct tep_event *event, void *context);
+int ras_cxl_memory_sparing_event_handler(struct trace_seq *s,
+					 struct tep_record *record,
+					 struct tep_event *event, void *context);
 #endif

ras-events.c

@@ -318,6 +318,7 @@ int toggle_ras_mc_event(int enable)
 	rc |= __toggle_ras_mc_event(ras, "cxl", "cxl_general_media", enable);
 	rc |= __toggle_ras_mc_event(ras, "cxl", "cxl_dram", enable);
 	rc |= __toggle_ras_mc_event(ras, "cxl", "cxl_memory_module", enable);
+	rc |= __toggle_ras_mc_event(ras, "cxl", "cxl_memory_sparing", enable);
 #endif
 
 #ifdef HAVE_SIGNAL
@@ -1215,6 +1216,14 @@ int handle_ras_events(int record_events, int enable_ipmitool)
 	else if (rc != EVENT_DISABLED)
 		log(ALL, LOG_ERR, "Can't get traces from %s:%s\n",
 		    "cxl", "memory_module");
+
+	rc = add_event_handler(ras, pevent, page_size, "cxl", "cxl_memory_sparing",
+			       ras_cxl_memory_sparing_event_handler, NULL, CXL_MEMORY_SPARING_EVENT);
+	if (!rc)
+		num_events++;
+	else if (rc != EVENT_DISABLED)
+		log(ALL, LOG_ERR, "Can't get traces from %s:%s\n",
+		    "cxl", "cxl_memory_sparing");
 #endif
 
 #ifdef HAVE_SIGNAL

ras-events.h

@@ -27,6 +27,7 @@ enum {
 	DEVLINK_EVENT,
 	DISKERROR_EVENT,
 	MF_EVENT,
+	SIGNAL_EVENT,
 	CXL_POISON_EVENT,
 	CXL_AER_UE_EVENT,
 	CXL_AER_CE_EVENT,
@@ -35,7 +36,7 @@ enum {
 	CXL_GENERAL_MEDIA_EVENT,
 	CXL_DRAM_EVENT,
 	CXL_MEMORY_MODULE_EVENT,
-	SIGNAL_EVENT,
+	CXL_MEMORY_SPARING_EVENT,
 	NR_EVENTS
 };
 

ras-record.h

@@ -279,6 +279,25 @@ struct ras_signal_event {
 	int result;
 };
 
+struct ras_cxl_memory_sparing_event {
+	struct ras_cxl_event_common_hdr hdr;
+	uint8_t flags;
+	uint8_t result;
+	uint16_t validity_flags;
+	uint16_t res_avail;
+	uint8_t channel;
+	uint8_t rank;
+	uint32_t nibble_mask;
+	uint8_t bank_group;
+	uint8_t bank;
+	uint32_t row;
+	uint16_t column;
+	uint8_t sub_channel;
+	uint8_t *comp_id;
+	uint8_t entity_id[CXL_PLDM_ENTITY_ID_LEN];
+	uint8_t res_id[CXL_PLDM_RES_ID_LEN];
+};
+
 struct ras_mc_event;
 struct ras_aer_event;
 struct ras_extlog_event;
@@ -297,6 +316,7 @@ struct ras_cxl_general_media_event;
 struct ras_cxl_dram_event;
 struct ras_cxl_memory_module_event;
 struct ras_signal_event;
+struct ras_cxl_memory_sparing_event;
 
 #ifdef HAVE_SQLITE3