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[RISCV] Reorder ins/outs of atomic instruction to match their assembly order. NFC (llvm#162411)
I think it is more intuitive for the operand order to match the assembly order than to be sorted by operand name. I also changed some isel patterns to always use XLenVT for pointer operands. This shouldn't be a functional change.
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8 files changed

+83
-80
lines changed

8 files changed

+83
-80
lines changed

‎llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -287,8 +287,8 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
287287
break;
288288
}
289289
BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)), ScratchReg)
290-
.addReg(AddrReg)
291-
.addReg(ScratchReg);
290+
.addReg(ScratchReg)
291+
.addReg(AddrReg);
292292
BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
293293
.addReg(ScratchReg)
294294
.addReg(RISCV::X0)
@@ -375,8 +375,8 @@ static void doMaskedAtomicBinOpExpansion(const RISCVInstrInfo *TII,
375375
ScratchReg);
376376

377377
BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering, STI)), ScratchReg)
378-
.addReg(AddrReg)
379-
.addReg(ScratchReg);
378+
.addReg(ScratchReg)
379+
.addReg(AddrReg);
380380
BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
381381
.addReg(ScratchReg)
382382
.addReg(RISCV::X0)
@@ -535,8 +535,8 @@ bool RISCVExpandAtomicPseudo::expandAtomicMinMaxOp(
535535
// sc.w scratch1, scratch1, (addr)
536536
// bnez scratch1, loop
537537
BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering, STI)), Scratch1Reg)
538-
.addReg(AddrReg)
539-
.addReg(Scratch1Reg);
538+
.addReg(Scratch1Reg)
539+
.addReg(AddrReg);
540540
BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
541541
.addReg(Scratch1Reg)
542542
.addReg(RISCV::X0)
@@ -674,8 +674,8 @@ bool RISCVExpandAtomicPseudo::expandAtomicCmpXchg(
674674
// bnez scratch, loophead
675675
BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)),
676676
ScratchReg)
677-
.addReg(AddrReg)
678-
.addReg(NewValReg);
677+
.addReg(NewValReg)
678+
.addReg(AddrReg);
679679
BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
680680
.addReg(ScratchReg)
681681
.addReg(RISCV::X0)
@@ -707,8 +707,8 @@ bool RISCVExpandAtomicPseudo::expandAtomicCmpXchg(
707707
MaskReg, ScratchReg);
708708
BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)),
709709
ScratchReg)
710-
.addReg(AddrReg)
711-
.addReg(ScratchReg);
710+
.addReg(ScratchReg)
711+
.addReg(AddrReg);
712712
BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
713713
.addReg(ScratchReg)
714714
.addReg(RISCV::X0)

‎llvm/lib/Target/RISCV/RISCVInstrInfoA.td‎

Lines changed: 25 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {
3333
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
3434
class SC_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
3535
: RVInstRAtomic<0b00011, aq, rl, funct3, OPC_AMO,
36-
(outs GPR:$rd), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
36+
(outs GPR:$rd), (ins GPR:$rs2, GPRMemZeroOffset:$rs1),
3737
opcodestr, "$rd, $rs2, $rs1">;
3838

3939
multiclass SC_r_aq_rl<bits<3> funct3, string opcodestr> {
@@ -46,7 +46,7 @@ multiclass SC_r_aq_rl<bits<3> funct3, string opcodestr> {
4646
let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
4747
class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr>
4848
: RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
49-
(outs GPR:$rd), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
49+
(outs GPR:$rd), (ins GPR:$rs2, GPRMemZeroOffset:$rs1),
5050
opcodestr, "$rd, $rs2, $rs1">;
5151

5252
multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
@@ -189,31 +189,34 @@ let Predicates = [HasAtomicLdSt, IsRV64] in {
189189

190190
/// AMOs
191191

192+
class PatAMO<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
193+
: Pat<(vt (OpNode (XLenVT GPR:$rs1), (vt GPR:$rs2))), (Inst GPR:$rs2, GPR:$rs1)>;
194+
192195
multiclass AMOPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
193196
list<Predicate> ExtraPreds = []> {
194197
let Predicates = !listconcat([HasStdExtA, NoStdExtZtso], ExtraPreds) in {
195-
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_monotonic"),
196-
!cast<RVInst>(BaseInst), vt>;
197-
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acquire"),
198-
!cast<RVInst>(BaseInst#"_AQ"), vt>;
199-
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_release"),
200-
!cast<RVInst>(BaseInst#"_RL"), vt>;
201-
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acq_rel"),
202-
!cast<RVInst>(BaseInst#"_AQRL"), vt>;
203-
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_seq_cst"),
204-
!cast<RVInst>(BaseInst#"_AQRL"), vt>;
198+
def : PatAMO<!cast<PatFrag>(AtomicOp#"_monotonic"),
199+
!cast<RVInst>(BaseInst), vt>;
200+
def : PatAMO<!cast<PatFrag>(AtomicOp#"_acquire"),
201+
!cast<RVInst>(BaseInst#"_AQ"), vt>;
202+
def : PatAMO<!cast<PatFrag>(AtomicOp#"_release"),
203+
!cast<RVInst>(BaseInst#"_RL"), vt>;
204+
def : PatAMO<!cast<PatFrag>(AtomicOp#"_acq_rel"),
205+
!cast<RVInst>(BaseInst#"_AQRL"), vt>;
206+
def : PatAMO<!cast<PatFrag>(AtomicOp#"_seq_cst"),
207+
!cast<RVInst>(BaseInst#"_AQRL"), vt>;
205208
}
206209
let Predicates = !listconcat([HasStdExtA, HasStdExtZtso], ExtraPreds) in {
207-
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_monotonic"),
208-
!cast<RVInst>(BaseInst), vt>;
209-
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acquire"),
210-
!cast<RVInst>(BaseInst), vt>;
211-
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_release"),
212-
!cast<RVInst>(BaseInst), vt>;
213-
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acq_rel"),
214-
!cast<RVInst>(BaseInst), vt>;
215-
def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_seq_cst"),
216-
!cast<RVInst>(BaseInst), vt>;
210+
def : PatAMO<!cast<PatFrag>(AtomicOp#"_monotonic"),
211+
!cast<RVInst>(BaseInst), vt>;
212+
def : PatAMO<!cast<PatFrag>(AtomicOp#"_acquire"),
213+
!cast<RVInst>(BaseInst), vt>;
214+
def : PatAMO<!cast<PatFrag>(AtomicOp#"_release"),
215+
!cast<RVInst>(BaseInst), vt>;
216+
def : PatAMO<!cast<PatFrag>(AtomicOp#"_acq_rel"),
217+
!cast<RVInst>(BaseInst), vt>;
218+
def : PatAMO<!cast<PatFrag>(AtomicOp#"_seq_cst"),
219+
!cast<RVInst>(BaseInst), vt>;
217220
}
218221
}
219222

‎llvm/lib/Target/RISCV/RISCVInstrInfoZa.td‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 1, Constraints = "$rd = $rd_wb"
4444
class AMO_cas<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr,
4545
DAGOperand RC>
4646
: RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
47-
(outs RC:$rd_wb), (ins RC:$rd, GPRMemZeroOffset:$rs1, RC:$rs2),
47+
(outs RC:$rd_wb), (ins RC:$rd, RC:$rs2, GPRMemZeroOffset:$rs1),
4848
opcodestr, "$rd, $rs2, $rs1">;
4949

5050
multiclass AMO_cas_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr,
@@ -71,48 +71,48 @@ defm AMOCAS_Q : AMO_cas_aq_rl<0b00101, 0b100, "amocas.q", GPRPairRV64>;
7171
multiclass AMOCASPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
7272
list<Predicate> ExtraPreds = []> {
7373
let Predicates = !listconcat([HasStdExtZacas, NoStdExtZtso], ExtraPreds) in {
74-
def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (vt GPR:$addr),
74+
def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (XLenVT GPR:$addr),
7575
(vt GPR:$cmp),
7676
(vt GPR:$new)),
77-
(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
78-
def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") (vt GPR:$addr),
77+
(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$new, GPR:$addr)>;
78+
def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") (XLenVT GPR:$addr),
7979
(vt GPR:$cmp),
8080
(vt GPR:$new)),
81-
(!cast<RVInst>(BaseInst#"_AQ") GPR:$cmp, GPR:$addr, GPR:$new)>;
82-
def : Pat<(!cast<PatFrag>(AtomicOp#"_release") (vt GPR:$addr),
81+
(!cast<RVInst>(BaseInst#"_AQ") GPR:$cmp, GPR:$new, GPR:$addr)>;
82+
def : Pat<(!cast<PatFrag>(AtomicOp#"_release") (XLenVT GPR:$addr),
8383
(vt GPR:$cmp),
8484
(vt GPR:$new)),
85-
(!cast<RVInst>(BaseInst#"_RL") GPR:$cmp, GPR:$addr, GPR:$new)>;
86-
def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") (vt GPR:$addr),
85+
(!cast<RVInst>(BaseInst#"_RL") GPR:$cmp, GPR:$new, GPR:$addr)>;
86+
def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") (XLenVT GPR:$addr),
8787
(vt GPR:$cmp),
8888
(vt GPR:$new)),
89-
(!cast<RVInst>(BaseInst#"_AQRL") GPR:$cmp, GPR:$addr, GPR:$new)>;
89+
(!cast<RVInst>(BaseInst#"_AQRL") GPR:$cmp, GPR:$new, GPR:$addr)>;
9090
def : Pat<(!cast<PatFrag>(AtomicOp#"_seq_cst") (vt GPR:$addr),
9191
(vt GPR:$cmp),
9292
(vt GPR:$new)),
93-
(!cast<RVInst>(BaseInst#"_AQRL") GPR:$cmp, GPR:$addr, GPR:$new)>;
93+
(!cast<RVInst>(BaseInst#"_AQRL") GPR:$cmp, GPR:$new, GPR:$addr)>;
9494
} // Predicates = !listconcat([HasStdExtZacas, NoStdExtZtso], ExtraPreds)
9595
let Predicates = !listconcat([HasStdExtZacas, HasStdExtZtso], ExtraPreds) in {
96-
def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (vt GPR:$addr),
96+
def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (XLenVT GPR:$addr),
9797
(vt GPR:$cmp),
9898
(vt GPR:$new)),
99-
(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
100-
def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") (vt GPR:$addr),
99+
(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$new, GPR:$addr)>;
100+
def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") (XLenVT GPR:$addr),
101101
(vt GPR:$cmp),
102102
(vt GPR:$new)),
103-
(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
104-
def : Pat<(!cast<PatFrag>(AtomicOp#"_release") (vt GPR:$addr),
103+
(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$new, GPR:$addr)>;
104+
def : Pat<(!cast<PatFrag>(AtomicOp#"_release") (XLenVT GPR:$addr),
105105
(vt GPR:$cmp),
106106
(vt GPR:$new)),
107-
(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
108-
def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") (vt GPR:$addr),
107+
(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$new, GPR:$addr)>;
108+
def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") (XLenVT GPR:$addr),
109109
(vt GPR:$cmp),
110110
(vt GPR:$new)),
111-
(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
112-
def : Pat<(!cast<PatFrag>(AtomicOp#"_seq_cst") (vt GPR:$addr),
111+
(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$new, GPR:$addr)>;
112+
def : Pat<(!cast<PatFrag>(AtomicOp#"_seq_cst") (XLenVT GPR:$addr),
113113
(vt GPR:$cmp),
114114
(vt GPR:$new)),
115-
(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$addr, GPR:$new)>;
115+
(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$new, GPR:$addr)>;
116116
} // Predicates = !listconcat([HasStdExtZacas, HasStdExtZtso], ExtraPreds)
117117
}
118118

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv32.mir‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ body: |
1717
; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
1818
; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
1919
; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
20-
; RV32IA-ZABHA-NEXT: [[AMOCAS_B:%[0-9]+]]:gpr = AMOCAS_B [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s8))
20+
; RV32IA-ZABHA-NEXT: [[AMOCAS_B:%[0-9]+]]:gpr = AMOCAS_B [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s8))
2121
; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_B]]
2222
; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10
2323
%0:gpr(p0) = COPY $x10
@@ -42,7 +42,7 @@ body: |
4242
; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
4343
; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
4444
; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
45-
; RV32IA-ZABHA-NEXT: [[AMOCAS_H:%[0-9]+]]:gpr = AMOCAS_H [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s16))
45+
; RV32IA-ZABHA-NEXT: [[AMOCAS_H:%[0-9]+]]:gpr = AMOCAS_H [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s16))
4646
; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_H]]
4747
; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10
4848
%0:gpr(p0) = COPY $x10
@@ -67,7 +67,7 @@ body: |
6767
; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
6868
; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
6969
; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
70-
; RV32IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s32))
70+
; RV32IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s32))
7171
; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_W]]
7272
; RV32IA-ZABHA-NEXT: PseudoRET implicit $x10
7373
%0:gpr(p0) = COPY $x10
@@ -92,7 +92,7 @@ body: |
9292
; RV32IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
9393
; RV32IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
9494
; RV32IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
95-
; RV32IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s32))
95+
; RV32IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s32))
9696
; RV32IA-ZABHA-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[AMOCAS_W]], 1
9797
; RV32IA-ZABHA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
9898
; RV32IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_W]]

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv64.mir‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ body: |
1717
; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
1818
; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
1919
; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
20-
; RV64IA-ZABHA-NEXT: [[AMOCAS_B:%[0-9]+]]:gpr = AMOCAS_B [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s8))
20+
; RV64IA-ZABHA-NEXT: [[AMOCAS_B:%[0-9]+]]:gpr = AMOCAS_B [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s8))
2121
; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_B]]
2222
; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10
2323
%0:gpr(p0) = COPY $x10
@@ -42,7 +42,7 @@ body: |
4242
; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
4343
; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
4444
; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
45-
; RV64IA-ZABHA-NEXT: [[AMOCAS_H:%[0-9]+]]:gpr = AMOCAS_H [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s16))
45+
; RV64IA-ZABHA-NEXT: [[AMOCAS_H:%[0-9]+]]:gpr = AMOCAS_H [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s16))
4646
; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_H]]
4747
; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10
4848
%0:gpr(p0) = COPY $x10
@@ -67,7 +67,7 @@ body: |
6767
; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
6868
; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
6969
; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
70-
; RV64IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s32))
70+
; RV64IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s32))
7171
; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_W]]
7272
; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10
7373
%0:gpr(p0) = COPY $x10
@@ -92,7 +92,7 @@ body: |
9292
; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
9393
; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
9494
; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
95-
; RV64IA-ZABHA-NEXT: [[AMOCAS_D_RV64_:%[0-9]+]]:gpr = AMOCAS_D_RV64 [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s64))
95+
; RV64IA-ZABHA-NEXT: [[AMOCAS_D_RV64_:%[0-9]+]]:gpr = AMOCAS_D_RV64 [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s64))
9696
; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_D_RV64_]]
9797
; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10
9898
%0:gpr(p0) = COPY $x10
@@ -116,7 +116,7 @@ body: |
116116
; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
117117
; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
118118
; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
119-
; RV64IA-ZABHA-NEXT: [[AMOCAS_D_RV64_:%[0-9]+]]:gpr = AMOCAS_D_RV64 [[COPY1]], [[COPY]], [[ADDI]] :: (load store monotonic (s64))
119+
; RV64IA-ZABHA-NEXT: [[AMOCAS_D_RV64_:%[0-9]+]]:gpr = AMOCAS_D_RV64 [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s64))
120120
; RV64IA-ZABHA-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[AMOCAS_D_RV64_]], 1
121121
; RV64IA-ZABHA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
122122
; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_D_RV64_]]

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ body: |
1515
; CHECK-NEXT: {{ $}}
1616
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
1717
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
18-
; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY]], [[COPY1]] :: (load store monotonic (s8))
18+
; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY1]], [[COPY]] :: (load store monotonic (s8))
1919
; CHECK-NEXT: $x10 = COPY [[AMOADD_B]]
2020
; CHECK-NEXT: PseudoRET implicit $x10
2121
%0:gprb(p0) = COPY $x10
@@ -38,7 +38,7 @@ body: |
3838
; CHECK-NEXT: {{ $}}
3939
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
4040
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
41-
; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[COPY]], [[COPY1]] :: (load store monotonic (s16))
41+
; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[COPY1]], [[COPY]] :: (load store monotonic (s16))
4242
; CHECK-NEXT: $x10 = COPY [[AMOADD_H]]
4343
; CHECK-NEXT: PseudoRET implicit $x10
4444
%0:gprb(p0) = COPY $x10
@@ -61,7 +61,7 @@ body: |
6161
; CHECK-NEXT: {{ $}}
6262
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
6363
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
64-
; CHECK-NEXT: [[AMOADD_W:%[0-9]+]]:gpr = AMOADD_W [[COPY]], [[COPY1]] :: (load store monotonic (s32))
64+
; CHECK-NEXT: [[AMOADD_W:%[0-9]+]]:gpr = AMOADD_W [[COPY1]], [[COPY]] :: (load store monotonic (s32))
6565
; CHECK-NEXT: $x10 = COPY [[AMOADD_W]]
6666
; CHECK-NEXT: PseudoRET implicit $x10
6767
%0:gprb(p0) = COPY $x10
@@ -86,7 +86,7 @@ body: |
8686
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
8787
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
8888
; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]]
89-
; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY]], [[SUB]] :: (load store monotonic (s8))
89+
; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[SUB]], [[COPY]] :: (load store monotonic (s8))
9090
; CHECK-NEXT: $x10 = COPY [[AMOADD_B]]
9191
; CHECK-NEXT: PseudoRET implicit $x10
9292
%0:gprb(p0) = COPY $x10
@@ -113,7 +113,7 @@ body: |
113113
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
114114
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
115115
; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]]
116-
; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[COPY]], [[SUB]] :: (load store monotonic (s16))
116+
; CHECK-NEXT: [[AMOADD_H:%[0-9]+]]:gpr = AMOADD_H [[SUB]], [[COPY]] :: (load store monotonic (s16))
117117
; CHECK-NEXT: $x10 = COPY [[AMOADD_H]]
118118
; CHECK-NEXT: PseudoRET implicit $x10
119119
%0:gprb(p0) = COPY $x10
@@ -140,7 +140,7 @@ body: |
140140
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
141141
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
142142
; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY2]], [[COPY1]]
143-
; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[COPY]], [[SUB]] :: (load store monotonic (s8))
143+
; CHECK-NEXT: [[AMOADD_B:%[0-9]+]]:gpr = AMOADD_B [[SUB]], [[COPY]] :: (load store monotonic (s8))
144144
; CHECK-NEXT: $x10 = COPY [[AMOADD_B]]
145145
; CHECK-NEXT: PseudoRET implicit $x10
146146
%0:gprb(p0) = COPY $x10

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