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Shared: Remove omittable exists variables
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3 files changed

+10
-10
lines changed

3 files changed

+10
-10
lines changed

shared/regex/codeql/regex/nfa/RegexpMatching.qll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ module Make<RegexTreeViewSig TreeImpl> {
115115
// The `getAnInputSymbolMatching` relation specialized to the chars that exists in strings tested by a `MatchedRegExp`.
116116
pragma[noinline]
117117
private InputSymbol specializedGetAnInputSymbolMatching(string char) {
118-
exists(string s, RootTerm r | isCandidate(r, s, _, _) | char = s.charAt(_)) and
118+
exists(string s | isCandidate(_, s, _, _) | char = s.charAt(_)) and
119119
result = getAnInputSymbolMatching(char)
120120
}
121121

shared/regex/codeql/regex/nfa/SuperlinearBackTracking.qll

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -288,13 +288,11 @@ module Make<RegexTreeViewSig TreeImpl> {
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StateTuple tuple, int dist
289289
) {
290290
// base case.
291-
exists(State q1, State q2, State q3 |
292-
isStartLoops(pivot, succ) and
293-
step(MkStateTuple(pivot, pivot, succ), s1, s2, s3, tuple) and
294-
tuple = MkStateTuple(q1, q2, q3) and
295-
trace = Nil() and
296-
dist = distBackFromEnd(tuple, MkStateTuple(pivot, succ, succ))
297-
)
291+
isStartLoops(pivot, succ) and
292+
step(MkStateTuple(pivot, pivot, succ), s1, s2, s3, tuple) and
293+
tuple = MkStateTuple(_, _, _) and
294+
trace = Nil() and
295+
dist = distBackFromEnd(tuple, MkStateTuple(pivot, succ, succ))
298296
or
299297
// recursive case
300298
exists(StateTuple p |

shared/ssa/codeql/ssa/Ssa.qll

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -870,7 +870,8 @@ module Make<InputSig Input> {
870870
// Can reach another definition
871871
lastRefRedefExt(def, _, bb, i, _)
872872
or
873-
exists(SourceVariable v | lastSsaRefExt(def, v, bb, i) |
873+
lastSsaRefExt(def, _, bb, i) and
874+
(
874875
// Can reach exit directly
875876
bb instanceof ExitBasicBlock
876877
or
@@ -889,7 +890,8 @@ module Make<InputSig Input> {
889890
// Can reach another definition
890891
lastRefRedef(def, bb, i, _)
891892
or
892-
exists(SourceVariable v | lastSsaRef(def, v, bb, i) |
893+
lastSsaRef(def, _, bb, i) and
894+
(
893895
// Can reach exit directly
894896
bb instanceof ExitBasicBlock
895897
or

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