Skip to content

Commit 069ad23

Browse files
dakersnardakersnar
authored
[NVPTXLowerArgs] Add align attribute to return value of addrspace.wrap intrinsic (llvm#153889)
If alignment inference happens after NVPTXLowerArgs these addrspace wrap intrinsics can prevent computeKnownBits from deriving alignment of loads/stores from parameters. To solve this, we can insert an alignment annotation on the generated intrinsic so that computeKnownBits does not need to traverse through it to find the alignment.
1 parent 67ca5da commit 069ad23

File tree

6 files changed

+96
-44
lines changed

6 files changed

+96
-44
lines changed

‎llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1027,9 +1027,16 @@ static inline bool isAddLike(const SDValue V) {
10271027
(V->getOpcode() == ISD::OR && V->getFlags().hasDisjoint());
10281028
}
10291029

1030+
static SDValue stripAssertAlign(SDValue N) {
1031+
if (N.getOpcode() == ISD::AssertAlign)
1032+
N = N.getOperand(0);
1033+
return N;
1034+
}
1035+
10301036
// selectBaseADDR - Match a dag node which will serve as the base address for an
10311037
// ADDR operand pair.
10321038
static SDValue selectBaseADDR(SDValue N, SelectionDAG *DAG) {
1039+
N = stripAssertAlign(N);
10331040
if (const auto *GA = dyn_cast<GlobalAddressSDNode>(N))
10341041
return DAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(N),
10351042
GA->getValueType(0), GA->getOffset(),
@@ -1044,6 +1051,7 @@ static SDValue selectBaseADDR(SDValue N, SelectionDAG *DAG) {
10441051
}
10451052

10461053
static SDValue accumulateOffset(SDValue &Addr, SDLoc DL, SelectionDAG *DAG) {
1054+
Addr = stripAssertAlign(Addr);
10471055
APInt AccumulatedOffset(64u, 0);
10481056
while (isAddLike(Addr)) {
10491057
const auto *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
@@ -1055,7 +1063,7 @@ static SDValue accumulateOffset(SDValue &Addr, SDLoc DL, SelectionDAG *DAG) {
10551063
break;
10561064

10571065
AccumulatedOffset += CI;
1058-
Addr = Addr->getOperand(0);
1066+
Addr = stripAssertAlign(Addr->getOperand(0));
10591067
}
10601068
return DAG->getSignedTargetConstant(AccumulatedOffset.getSExtValue(), DL,
10611069
MVT::i32);

‎llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp‎

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -412,6 +412,22 @@ static void adjustByValArgAlignment(Argument *Arg, Value *ArgInParamAS,
412412
}
413413
}
414414

415+
// Create a call to the nvvm_internal_addrspace_wrap intrinsic and set the
416+
// alignment of the return value based on the alignment of the argument.
417+
static CallInst *createNVVMInternalAddrspaceWrap(IRBuilder<> &IRB,
418+
Argument &Arg) {
419+
CallInst *ArgInParam =
420+
IRB.CreateIntrinsic(Intrinsic::nvvm_internal_addrspace_wrap,
421+
{IRB.getPtrTy(ADDRESS_SPACE_PARAM), Arg.getType()},
422+
&Arg, {}, Arg.getName() + ".param");
423+
424+
if (MaybeAlign ParamAlign = Arg.getParamAlign())
425+
ArgInParam->addRetAttr(
426+
Attribute::getWithAlignment(ArgInParam->getContext(), *ParamAlign));
427+
428+
return ArgInParam;
429+
}
430+
415431
namespace {
416432
struct ArgUseChecker : PtrUseVisitor<ArgUseChecker> {
417433
using Base = PtrUseVisitor<ArgUseChecker>;
@@ -515,10 +531,7 @@ void copyByValParam(Function &F, Argument &Arg) {
515531
Arg.getParamAlign().value_or(DL.getPrefTypeAlign(StructType)));
516532
Arg.replaceAllUsesWith(AllocA);
517533

518-
Value *ArgInParam =
519-
IRB.CreateIntrinsic(Intrinsic::nvvm_internal_addrspace_wrap,
520-
{IRB.getPtrTy(ADDRESS_SPACE_PARAM), Arg.getType()},
521-
&Arg, {}, Arg.getName());
534+
CallInst *ArgInParam = createNVVMInternalAddrspaceWrap(IRB, Arg);
522535

523536
// Be sure to propagate alignment to this load; LLVM doesn't know that NVPTX
524537
// addrspacecast preserves alignment. Since params are constant, this load
@@ -549,9 +562,7 @@ static void handleByValParam(const NVPTXTargetMachine &TM, Argument *Arg) {
549562
SmallVector<Use *, 16> UsesToUpdate(llvm::make_pointer_range(Arg->uses()));
550563

551564
IRBuilder<> IRB(&*FirstInst);
552-
Value *ArgInParamAS = IRB.CreateIntrinsic(
553-
Intrinsic::nvvm_internal_addrspace_wrap,
554-
{IRB.getPtrTy(ADDRESS_SPACE_PARAM), Arg->getType()}, {Arg});
565+
CallInst *ArgInParamAS = createNVVMInternalAddrspaceWrap(IRB, *Arg);
555566

556567
for (Use *U : UsesToUpdate)
557568
convertToParamAS(U, ArgInParamAS, HasCvtaParam, IsGridConstant);
@@ -581,10 +592,7 @@ static void handleByValParam(const NVPTXTargetMachine &TM, Argument *Arg) {
581592
// argument already in the param address space, we need to use the noop
582593
// intrinsic, this had the added benefit of preventing other optimizations
583594
// from folding away this pair of addrspacecasts.
584-
auto *ParamSpaceArg =
585-
IRB.CreateIntrinsic(Intrinsic::nvvm_internal_addrspace_wrap,
586-
{IRB.getPtrTy(ADDRESS_SPACE_PARAM), Arg->getType()},
587-
Arg, {}, Arg->getName() + ".param");
595+
auto *ParamSpaceArg = createNVVMInternalAddrspaceWrap(IRB, *Arg);
588596

589597
// Cast param address to generic address space.
590598
Value *GenericArg = IRB.CreateAddrSpaceCast(

‎llvm/test/CodeGen/NVPTX/lower-args-alignment.ll‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt < %s -passes=nvptx-lower-args,infer-alignment -S | FileCheck %s
3+
4+
target triple = "nvptx64-nvidia-cuda"
5+
6+
; ------------------------------------------------------------------------------
7+
; Test that alignment can be inferred through llvm.nvvm.internal.addrspace.wrap.p101.p0 intrinsics
8+
; thanks to the alignment attribute on the intrinsic
9+
; ------------------------------------------------------------------------------
10+
11+
%struct.S1 = type { i32, i32, i32, i32 }
12+
define ptx_kernel i32 @test_align8(ptr noundef readonly byval(%struct.S1) align 8 captures(none) %params) {
13+
; CHECK-LABEL: define ptx_kernel i32 @test_align8(
14+
; CHECK-SAME: ptr noundef readonly byval([[STRUCT_S1:%.*]]) align 8 captures(none) [[PARAMS:%.*]]) {
15+
; CHECK-NEXT: [[ENTRY:.*:]]
16+
; CHECK-NEXT: [[TMP0:%.*]] = call align 8 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[PARAMS]])
17+
; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(101) [[TMP0]], align 8
18+
; CHECK-NEXT: ret i32 [[LOAD]]
19+
;
20+
entry:
21+
%load = load i32, ptr %params, align 4
22+
ret i32 %load
23+
}
24+
25+
define ptx_kernel i32 @test_align1(ptr noundef readonly byval(%struct.S1) align 1 captures(none) %params) {
26+
; CHECK-LABEL: define ptx_kernel i32 @test_align1(
27+
; CHECK-SAME: ptr noundef readonly byval([[STRUCT_S1:%.*]]) align 4 captures(none) [[PARAMS:%.*]]) {
28+
; CHECK-NEXT: [[ENTRY:.*:]]
29+
; CHECK-NEXT: [[TMP0:%.*]] = call align 1 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[PARAMS]])
30+
; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(101) [[TMP0]], align 4
31+
; CHECK-NEXT: ret i32 [[LOAD]]
32+
;
33+
entry:
34+
%load = load i32, ptr %params, align 4
35+
ret i32 %load
36+
}

‎llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ define ptx_kernel void @grid_const_int(ptr byval(i32) align 4 %input1, i32 %inpu
7272
; PTX-NEXT: ret;
7373
; OPT-LABEL: define ptx_kernel void @grid_const_int(
7474
; OPT-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], i32 [[INPUT2:%.*]], ptr [[OUT:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
75-
; OPT-NEXT: [[INPUT11:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT1]])
75+
; OPT-NEXT: [[INPUT11:%.*]] = call align 4 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT1]])
7676
; OPT-NEXT: [[TMP:%.*]] = load i32, ptr addrspace(101) [[INPUT11]], align 4
7777
; OPT-NEXT: [[ADD:%.*]] = add i32 [[TMP]], [[INPUT2]]
7878
; OPT-NEXT: store i32 [[ADD]], ptr [[OUT]], align 4
@@ -101,7 +101,7 @@ define ptx_kernel void @grid_const_struct(ptr byval(%struct.s) align 4 %input, p
101101
; PTX-NEXT: ret;
102102
; OPT-LABEL: define ptx_kernel void @grid_const_struct(
103103
; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]], ptr [[OUT:%.*]]) #[[ATTR0]] {
104-
; OPT-NEXT: [[INPUT1:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT]])
104+
; OPT-NEXT: [[INPUT1:%.*]] = call align 4 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT]])
105105
; OPT-NEXT: [[GEP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr addrspace(101) [[INPUT1]], i32 0, i32 0
106106
; OPT-NEXT: [[GEP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr addrspace(101) [[INPUT1]], i32 0, i32 1
107107
; OPT-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(101) [[GEP13]], align 4
@@ -137,7 +137,7 @@ define ptx_kernel void @grid_const_escape(ptr byval(%struct.s) align 4 %input) {
137137
; PTX-NEXT: ret;
138138
; OPT-LABEL: define ptx_kernel void @grid_const_escape(
139139
; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]]) #[[ATTR0]] {
140-
; OPT-NEXT: [[TMP1:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT]])
140+
; OPT-NEXT: [[TMP1:%.*]] = call align 4 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT]])
141141
; OPT-NEXT: [[INPUT_PARAM_GEN:%.*]] = addrspacecast ptr addrspace(101) [[TMP1]] to ptr
142142
; OPT-NEXT: [[CALL:%.*]] = call i32 @escape(ptr [[INPUT_PARAM_GEN]])
143143
; OPT-NEXT: ret void
@@ -180,9 +180,9 @@ define ptx_kernel void @multiple_grid_const_escape(ptr byval(%struct.s) align 4
180180
; PTX-NEXT: ret;
181181
; OPT-LABEL: define ptx_kernel void @multiple_grid_const_escape(
182182
; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]], i32 [[A:%.*]], ptr byval(i32) align 4 [[B:%.*]]) #[[ATTR0]] {
183-
; OPT-NEXT: [[TMP1:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[B]])
183+
; OPT-NEXT: [[TMP1:%.*]] = call align 4 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[B]])
184184
; OPT-NEXT: [[B_PARAM_GEN:%.*]] = addrspacecast ptr addrspace(101) [[TMP1]] to ptr
185-
; OPT-NEXT: [[TMP2:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT]])
185+
; OPT-NEXT: [[TMP2:%.*]] = call align 4 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT]])
186186
; OPT-NEXT: [[INPUT_PARAM_GEN:%.*]] = addrspacecast ptr addrspace(101) [[TMP2]] to ptr
187187
; OPT-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
188188
; OPT-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
@@ -208,7 +208,7 @@ define ptx_kernel void @grid_const_memory_escape(ptr byval(%struct.s) align 4 %i
208208
; PTX-NEXT: ret;
209209
; OPT-LABEL: define ptx_kernel void @grid_const_memory_escape(
210210
; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]], ptr [[ADDR:%.*]]) #[[ATTR0]] {
211-
; OPT-NEXT: [[TMP1:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT]])
211+
; OPT-NEXT: [[TMP1:%.*]] = call align 4 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT]])
212212
; OPT-NEXT: [[INPUT1:%.*]] = addrspacecast ptr addrspace(101) [[TMP1]] to ptr
213213
; OPT-NEXT: store ptr [[INPUT1]], ptr [[ADDR]], align 8
214214
; OPT-NEXT: ret void
@@ -235,7 +235,7 @@ define ptx_kernel void @grid_const_inlineasm_escape(ptr byval(%struct.s) align 4
235235
; PTX-NOT .local
236236
; OPT-LABEL: define ptx_kernel void @grid_const_inlineasm_escape(
237237
; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]], ptr [[RESULT:%.*]]) #[[ATTR0]] {
238-
; OPT-NEXT: [[TMP1:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT]])
238+
; OPT-NEXT: [[TMP1:%.*]] = call align 4 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT]])
239239
; OPT-NEXT: [[INPUT1:%.*]] = addrspacecast ptr addrspace(101) [[TMP1]] to ptr
240240
; OPT-NEXT: [[TMPPTR1:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[INPUT1]], i32 0, i32 0
241241
; OPT-NEXT: [[TMPPTR2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[INPUT1]], i32 0, i32 1
@@ -357,7 +357,7 @@ define ptx_kernel void @grid_const_phi(ptr byval(%struct.s) align 4 %input1, ptr
357357
; PTX-NEXT: ret;
358358
; OPT-LABEL: define ptx_kernel void @grid_const_phi(
359359
; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr [[INOUT:%.*]]) #[[ATTR0]] {
360-
; OPT-NEXT: [[TMP1:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT1]])
360+
; OPT-NEXT: [[TMP1:%.*]] = call align 4 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT1]])
361361
; OPT-NEXT: [[INPUT1_PARAM_GEN:%.*]] = addrspacecast ptr addrspace(101) [[TMP1]] to ptr
362362
; OPT-NEXT: [[VAL:%.*]] = load i32, ptr [[INOUT]], align 4
363363
; OPT-NEXT: [[LESS:%.*]] = icmp slt i32 [[VAL]], 0
@@ -416,7 +416,7 @@ define ptx_kernel void @grid_const_phi_ngc(ptr byval(%struct.s) align 4 %input1,
416416
; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr byval([[STRUCT_S]]) [[INPUT2:%.*]], ptr [[INOUT:%.*]]) #[[ATTR0]] {
417417
; OPT-NEXT: [[TMP1:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT2]])
418418
; OPT-NEXT: [[INPUT2_PARAM_GEN:%.*]] = addrspacecast ptr addrspace(101) [[TMP1]] to ptr
419-
; OPT-NEXT: [[TMP2:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT1]])
419+
; OPT-NEXT: [[TMP2:%.*]] = call align 4 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT1]])
420420
; OPT-NEXT: [[INPUT1_PARAM_GEN:%.*]] = addrspacecast ptr addrspace(101) [[TMP2]] to ptr
421421
; OPT-NEXT: [[VAL:%.*]] = load i32, ptr [[INOUT]], align 4
422422
; OPT-NEXT: [[LESS:%.*]] = icmp slt i32 [[VAL]], 0
@@ -471,7 +471,7 @@ define ptx_kernel void @grid_const_select(ptr byval(i32) align 4 %input1, ptr by
471471
; OPT-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[INOUT:%.*]]) #[[ATTR0]] {
472472
; OPT-NEXT: [[TMP1:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT2]])
473473
; OPT-NEXT: [[INPUT2_PARAM_GEN:%.*]] = addrspacecast ptr addrspace(101) [[TMP1]] to ptr
474-
; OPT-NEXT: [[TMP2:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT1]])
474+
; OPT-NEXT: [[TMP2:%.*]] = call align 4 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT1]])
475475
; OPT-NEXT: [[INPUT1_PARAM_GEN:%.*]] = addrspacecast ptr addrspace(101) [[TMP2]] to ptr
476476
; OPT-NEXT: [[VAL:%.*]] = load i32, ptr [[INOUT]], align 4
477477
; OPT-NEXT: [[LESS:%.*]] = icmp slt i32 [[VAL]], 0
@@ -520,7 +520,7 @@ declare void @device_func(ptr byval(i32) align 4)
520520
define ptx_kernel void @test_forward_byval_arg(ptr byval(i32) align 4 %input) {
521521
; OPT-LABEL: define ptx_kernel void @test_forward_byval_arg(
522522
; OPT-SAME: ptr byval(i32) align 4 [[INPUT:%.*]]) #[[ATTR0]] {
523-
; OPT-NEXT: [[INPUT_PARAM:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT]])
523+
; OPT-NEXT: [[INPUT_PARAM:%.*]] = call align 4 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[INPUT]])
524524
; OPT-NEXT: [[INPUT_PARAM_GEN:%.*]] = addrspacecast ptr addrspace(101) [[INPUT_PARAM]] to ptr
525525
; OPT-NEXT: call void @device_func(ptr byval(i32) align 4 [[INPUT_PARAM_GEN]])
526526
; OPT-NEXT: ret void

‎llvm/test/CodeGen/NVPTX/lower-args.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -200,7 +200,7 @@ define ptx_kernel void @ptr_as_int(i64 noundef %i, i32 noundef %v) {
200200
define ptx_kernel void @ptr_as_int_aggr(ptr nocapture noundef readonly byval(%struct.S) align 8 %s, i32 noundef %v) {
201201
; IRC-LABEL: define ptx_kernel void @ptr_as_int_aggr(
202202
; IRC-SAME: ptr noundef readonly byval([[STRUCT_S:%.*]]) align 8 captures(none) [[S:%.*]], i32 noundef [[V:%.*]]) {
203-
; IRC-NEXT: [[S3:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[S]])
203+
; IRC-NEXT: [[S3:%.*]] = call align 8 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[S]])
204204
; IRC-NEXT: [[I:%.*]] = load i64, ptr addrspace(101) [[S3]], align 8
205205
; IRC-NEXT: [[P:%.*]] = inttoptr i64 [[I]] to ptr
206206
; IRC-NEXT: [[P1:%.*]] = addrspacecast ptr [[P]] to ptr addrspace(1)
@@ -210,7 +210,7 @@ define ptx_kernel void @ptr_as_int_aggr(ptr nocapture noundef readonly byval(%st
210210
;
211211
; IRO-LABEL: define ptx_kernel void @ptr_as_int_aggr(
212212
; IRO-SAME: ptr noundef readonly byval([[STRUCT_S:%.*]]) align 8 captures(none) [[S:%.*]], i32 noundef [[V:%.*]]) {
213-
; IRO-NEXT: [[S1:%.*]] = call ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[S]])
213+
; IRO-NEXT: [[S1:%.*]] = call align 8 ptr addrspace(101) @llvm.nvvm.internal.addrspace.wrap.p101.p0(ptr [[S]])
214214
; IRO-NEXT: [[I:%.*]] = load i64, ptr addrspace(101) [[S1]], align 8
215215
; IRO-NEXT: [[P:%.*]] = inttoptr i64 [[I]] to ptr
216216
; IRO-NEXT: store i32 [[V]], ptr [[P]], align 4

0 commit comments

Comments
 (0)