Skip to content

Commit 2b5b57c

Browse files
cdevadascdevadas
authored
[AMDGPU] Skip non-wwm reg implicit-def from bb prolog (llvm#115834)
Currently all implicit-def instructions are part of bb prolog. We should only include the wwm-register's implicit definitions into the BB prolog. The other vector class registers' implicit defs when exist at the bb top might cause interference when pushed the LR_split copy insertion downwards. The SplitKit is very strict on altering the insertion points and will assert such instances.
1 parent 1791b25 commit 2b5b57c

10 files changed

+76
-66
lines changed

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8909,16 +8909,19 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,
89098909
// needed by the prolog. However, the insertions for scalar registers can
89108910
// always be placed at the BB top as they are independent of the exec mask
89118911
// value.
8912+
const MachineFunction *MF = MI.getParent()->getParent();
89128913
bool IsNullOrVectorRegister = true;
89138914
if (Reg) {
8914-
const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
8915+
const MachineRegisterInfo &MRI = MF->getRegInfo();
89158916
IsNullOrVectorRegister = !RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg));
89168917
}
89178918

89188919
uint16_t Opcode = MI.getOpcode();
8920+
const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
89198921
return IsNullOrVectorRegister &&
89208922
(isSGPRSpill(Opcode) || isWWMRegSpillOpcode(Opcode) ||
8921-
Opcode == AMDGPU::IMPLICIT_DEF ||
8923+
(Opcode == AMDGPU::IMPLICIT_DEF &&
8924+
MFI->isWWMReg(MI.getOperand(0).getReg())) ||
89228925
(!MI.isTerminator() && Opcode != AMDGPU::COPY &&
89238926
MI.modifiesRegister(AMDGPU::EXEC, &RI)));
89248927
}

‎llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -596,6 +596,10 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction,
596596
SMDiagnostic &Error, SMRange &SourceRange);
597597

598598
void reserveWWMRegister(Register Reg) { WWMReservedRegs.insert(Reg); }
599+
bool isWWMReg(Register Reg) const {
600+
return Reg.isVirtual() ? checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)
601+
: WWMReservedRegs.contains(Reg);
602+
}
599603

600604
void updateNonWWMRegMask(BitVector &RegMask) { NonWWMRegMask = RegMask; }
601605
BitVector getNonWWMRegMask() const { return NonWWMRegMask; }

‎llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,8 @@ body: |
1919
; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
2020
; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
2121
; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY1]](s32), [[C1]]
22-
; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
2322
; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[FCMP]](s1)
23+
; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
2424
; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[DEF]](s1)
2525
; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY5]](s1), $exec_lo, implicit-def $scc
2626
; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY4]](s1), implicit-def $scc
@@ -122,8 +122,8 @@ body: |
122122
; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
123123
; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
124124
; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
125-
; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF
126125
; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[C1]](s1)
126+
; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF
127127
; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[DEF]](s1)
128128
; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY5]](s1), $exec_lo, implicit-def $scc
129129
; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY4]](s1), implicit-def $scc
@@ -790,8 +790,8 @@ body: |
790790
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)
791791
; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
792792
; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C3]]
793-
; GFX10-NEXT: [[DEF2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF
794793
; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)
794+
; GFX10-NEXT: [[DEF2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF
795795
; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc
796796
; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc
797797
; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc

‎llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -170,8 +170,8 @@ define <4 x float> @waterfall_loop(<8 x i32> %vgpr_srd) {
170170
; CHECK-NEXT: v_readlane_b32 s4, v16, 4
171171
; CHECK-NEXT: s_mov_b32 exec_lo, s4
172172
; CHECK-NEXT: ; %bb.4:
173-
; CHECK-NEXT: ; implicit-def: $sgpr4
174173
; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
174+
; CHECK-NEXT: ; implicit-def: $sgpr4
175175
; CHECK-NEXT: v_mov_b32_e32 v1, s4
176176
; CHECK-NEXT: v_mov_b32_e32 v2, s4
177177
; CHECK-NEXT: v_mov_b32_e32 v3, s4

‎llvm/test/CodeGen/AMDGPU/collapse-endcf.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1135,11 +1135,11 @@ define void @scc_liveness(i32 %arg) local_unnamed_addr #0 {
11351135
; GCN-O0-NEXT: s_cbranch_execz .LBB5_5
11361136
; GCN-O0-NEXT: ; %bb.3: ; %bb4
11371137
; GCN-O0-NEXT: ; in Loop: Header=BB5_1 Depth=1
1138-
; GCN-O0-NEXT: ; implicit-def: $sgpr4
11391138
; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
11401139
; GCN-O0-NEXT: s_waitcnt expcnt(0)
11411140
; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload
11421141
; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
1142+
; GCN-O0-NEXT: ; implicit-def: $sgpr4
11431143
; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
11441144
; GCN-O0-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
11451145
; GCN-O0-NEXT: s_mov_b32 s4, 0

‎llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5370,9 +5370,9 @@ define amdgpu_kernel void @extract_vgpr_offset_multiple_in_block(ptr addrspace(1
53705370
; NOOPT-NEXT: s_waitcnt expcnt(0)
53715371
; NOOPT-NEXT: buffer_load_dword v18, off, s[36:39], 0 ; 4-byte Folded Reload
53725372
; NOOPT-NEXT: s_mov_b64 exec, s[28:29]
5373-
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
53745373
; NOOPT-NEXT: s_waitcnt vmcnt(0)
53755374
; NOOPT-NEXT: v_readlane_b32 s4, v18, 25
5375+
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
53765376
; NOOPT-NEXT: s_mov_b32 s7, s1
53775377
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
53785378
; NOOPT-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
@@ -6223,8 +6223,8 @@ define amdgpu_kernel void @insert_vgpr_offset_multiple_in_block(ptr addrspace(1)
62236223
; NOOPT-NEXT: s_mov_b64 exec, s[0:1]
62246224
; NOOPT-NEXT: s_cbranch_execz .LBB17_8
62256225
; NOOPT-NEXT: ; %bb.7: ; %bb1
6226-
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
62276226
; NOOPT-NEXT: buffer_load_dword v0, off, s[28:31], 0 offset:68 ; 4-byte Folded Reload
6227+
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
62286228
; NOOPT-NEXT: s_mov_b32 s6, s1
62296229
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
62306230
; NOOPT-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
@@ -7286,10 +7286,10 @@ define amdgpu_kernel void @extract_adjacent_blocks(i32 %arg) {
72867286
; NOOPT-NEXT: s_waitcnt expcnt(0)
72877287
; NOOPT-NEXT: buffer_load_dword v4, off, s[12:15], 0 ; 4-byte Folded Reload
72887288
; NOOPT-NEXT: s_mov_b64 exec, s[8:9]
7289-
; NOOPT-NEXT: ; implicit-def: $sgpr2
72907289
; NOOPT-NEXT: s_waitcnt vmcnt(0)
72917290
; NOOPT-NEXT: v_readlane_b32 s0, v4, 0
72927291
; NOOPT-NEXT: v_readlane_b32 s1, v4, 1
7292+
; NOOPT-NEXT: ; implicit-def: $sgpr2
72937293
; NOOPT-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
72947294
; NOOPT-NEXT: s_mov_b32 s0, 1
72957295
; NOOPT-NEXT: ; implicit-def: $sgpr1
@@ -7316,11 +7316,11 @@ define amdgpu_kernel void @extract_adjacent_blocks(i32 %arg) {
73167316
; NOOPT-NEXT: ;;#ASMEND
73177317
; NOOPT-NEXT: s_branch .LBB19_4
73187318
; NOOPT-NEXT: .LBB19_3: ; %bb4
7319-
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
73207319
; NOOPT-NEXT: s_or_saveexec_b64 s[8:9], -1
73217320
; NOOPT-NEXT: s_waitcnt expcnt(0)
73227321
; NOOPT-NEXT: buffer_load_dword v4, off, s[12:15], 0 ; 4-byte Folded Reload
73237322
; NOOPT-NEXT: s_mov_b64 exec, s[8:9]
7323+
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
73247324
; NOOPT-NEXT: s_mov_b32 s6, s1
73257325
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
73267326
; NOOPT-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
@@ -7345,8 +7345,8 @@ define amdgpu_kernel void @extract_adjacent_blocks(i32 %arg) {
73457345
; NOOPT-NEXT: s_mov_b64 exec, s[8:9]
73467346
; NOOPT-NEXT: s_branch .LBB19_1
73477347
; NOOPT-NEXT: .LBB19_4: ; %bb7
7348-
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
73497348
; NOOPT-NEXT: ; implicit-def: $sgpr4
7349+
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
73507350
; NOOPT-NEXT: s_mov_b32 s7, s1
73517351
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
73527352
; NOOPT-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
@@ -7529,10 +7529,10 @@ define amdgpu_kernel void @insert_adjacent_blocks(i32 %arg, float %val0) {
75297529
; NOOPT-NEXT: s_waitcnt expcnt(0)
75307530
; NOOPT-NEXT: buffer_load_dword v4, off, s[16:19], 0 ; 4-byte Folded Reload
75317531
; NOOPT-NEXT: s_mov_b64 exec, s[12:13]
7532-
; NOOPT-NEXT: ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7
75337532
; NOOPT-NEXT: s_waitcnt vmcnt(0)
75347533
; NOOPT-NEXT: v_readlane_b32 s0, v4, 0
75357534
; NOOPT-NEXT: v_readlane_b32 s1, v4, 1
7535+
; NOOPT-NEXT: ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7
75367536
; NOOPT-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
75377537
; NOOPT-NEXT: s_mov_b32 s0, 1
75387538
; NOOPT-NEXT: ; implicit-def: $sgpr1
@@ -7560,11 +7560,11 @@ define amdgpu_kernel void @insert_adjacent_blocks(i32 %arg, float %val0) {
75607560
; NOOPT-NEXT: ;;#ASMEND
75617561
; NOOPT-NEXT: s_branch .LBB20_4
75627562
; NOOPT-NEXT: .LBB20_3: ; %bb4
7563-
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
75647563
; NOOPT-NEXT: s_or_saveexec_b64 s[12:13], -1
75657564
; NOOPT-NEXT: s_waitcnt expcnt(0)
75667565
; NOOPT-NEXT: buffer_load_dword v4, off, s[16:19], 0 ; 4-byte Folded Reload
75677566
; NOOPT-NEXT: s_mov_b64 exec, s[12:13]
7567+
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
75687568
; NOOPT-NEXT: s_mov_b32 s6, s1
75697569
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
75707570
; NOOPT-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
@@ -7590,8 +7590,8 @@ define amdgpu_kernel void @insert_adjacent_blocks(i32 %arg, float %val0) {
75907590
; NOOPT-NEXT: s_mov_b64 exec, s[12:13]
75917591
; NOOPT-NEXT: s_branch .LBB20_1
75927592
; NOOPT-NEXT: .LBB20_4: ; %bb7
7593-
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
75947593
; NOOPT-NEXT: ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7
7594+
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
75957595
; NOOPT-NEXT: s_mov_b32 s10, s1
75967596
; NOOPT-NEXT: ; implicit-def: $sgpr0_sgpr1
75977597
; NOOPT-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
@@ -9105,9 +9105,9 @@ define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) {
91059105
; NOOPT-NEXT: s_waitcnt expcnt(0)
91069106
; NOOPT-NEXT: buffer_load_dword v18, off, s[24:27], 0 ; 4-byte Folded Reload
91079107
; NOOPT-NEXT: s_mov_b64 exec, s[20:21]
9108-
; NOOPT-NEXT: ; implicit-def: $sgpr2_sgpr3
91099108
; NOOPT-NEXT: s_waitcnt vmcnt(0)
91109109
; NOOPT-NEXT: v_readlane_b32 s0, v18, 1
9110+
; NOOPT-NEXT: ; implicit-def: $sgpr2_sgpr3
91119111
; NOOPT-NEXT: ; kill: def $sgpr3 killed $sgpr3 killed $sgpr2_sgpr3
91129112
; NOOPT-NEXT: ; implicit-def: $sgpr4_sgpr5
91139113
; NOOPT-NEXT: ; kill: def $sgpr4 killed $sgpr4 killed $sgpr4_sgpr5

0 commit comments

Comments
 (0)