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[RegisterCoalescer] Prune live range of early-clobber from live-in (llvm#157628)
Fixes llvm#134424 Fixes llvm#71023 Refer to the context of llvm#71024, when RegisterCoalescer tries to merge `early-clobber %1:vr = PseudoVRGATHER_VI_M1 undef %1, ...`, JoinVals reports `CR_Replace` as the conflict with `undef` can be ignored. However, when pruning values, we need to remove any live ranges that overlap a `CR_Replace` resolution. `LiveIntervals::pruneValue` missed pruning the early-clobber part of the live ranges. This patch implements it by removing the ranges from live-in. I am not familiar with the RegisterCoalescer component. Any advice is appreciated. llvm#156249 seems to be related, but not resolved with this patch. I am still investigating.
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‎llvm/lib/CodeGen/LiveIntervals.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -661,7 +661,10 @@ void LiveIntervals::extendToIndices(LiveRange &LR,
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void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill,
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SmallVectorImpl<SlotIndex> *EndPoints) {
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LiveQueryResult LRQ = LR.Query(Kill);
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VNInfo *VNI = LRQ.valueOutOrDead();
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// LR may have liveness reachable from early clobber slot, which may be
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// only live-in instead of live-out of the instruction.
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// For example, LR =[1r, 3r), Kill = 3e, we have to prune [3e, 3r) of LR.
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VNInfo *VNI = LRQ.valueOutOrDead() ? LRQ.valueOutOrDead() : LRQ.valueIn();
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if (!VNI)
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return;
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‎llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.ll‎

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -O1 -mtriple=riscv64 -mattr=+v < %s | FileCheck %s
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define i32 @pr134424(i64 %input_value, i32 %base_value, i1 %cond_flag1, i1 %cond_flag2, i1 %cond_flag3) {
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; CHECK-LABEL: pr134424:
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; CHECK: # %bb.0: # %for.body.us.preheader.i
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; CHECK-NEXT: andi a3, a3, 1
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; CHECK-NEXT: andi a5, a2, 1
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vmv.v.x v8, a0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, ma
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
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; CHECK-NEXT: vmv.v.i v0, 14
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; CHECK-NEXT: mv a2, a1
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; CHECK-NEXT: bnez a5, .LBB0_2
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; CHECK-NEXT: # %bb.1: # %for.body.us.preheader.i
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; CHECK-NEXT: li a2, 1
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; CHECK-NEXT: .LBB0_2: # %for.body.us.preheader.i
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
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; CHECK-NEXT: andi a4, a4, 1
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; CHECK-NEXT: mv a0, a1
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; CHECK-NEXT: bnez a3, .LBB0_4
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; CHECK-NEXT: # %bb.3: # %for.body.us.preheader.i
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; CHECK-NEXT: li a0, 1
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; CHECK-NEXT: .LBB0_4: # %for.body.us.preheader.i
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; CHECK-NEXT: vmsle.vi v0, v8, 0
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; CHECK-NEXT: sext.w a2, a2
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; CHECK-NEXT: bnez a4, .LBB0_6
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; CHECK-NEXT: # %bb.5: # %for.body.us.preheader.i
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; CHECK-NEXT: li a1, 1
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; CHECK-NEXT: .LBB0_6: # %for.body.us.preheader.i
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; CHECK-NEXT: sext.w a0, a0
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vredmin.vs v8, v8, v8
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; CHECK-NEXT: vmv.x.s a3, v8
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; CHECK-NEXT: sext.w a1, a1
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; CHECK-NEXT: bge a3, a2, .LBB0_11
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; CHECK-NEXT: # %bb.7: # %for.body.us.preheader.i
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; CHECK-NEXT: bge a0, a1, .LBB0_12
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; CHECK-NEXT: .LBB0_8: # %for.body.us.preheader.i
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; CHECK-NEXT: blt a3, a0, .LBB0_10
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; CHECK-NEXT: .LBB0_9: # %for.body.us.preheader.i
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; CHECK-NEXT: mv a3, a0
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; CHECK-NEXT: .LBB0_10: # %for.body.us.preheader.i
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; CHECK-NEXT: sw a3, 0(zero)
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; CHECK-NEXT: li a0, 0
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_11: # %for.body.us.preheader.i
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; CHECK-NEXT: mv a3, a2
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; CHECK-NEXT: blt a0, a1, .LBB0_8
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; CHECK-NEXT: .LBB0_12: # %for.body.us.preheader.i
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; CHECK-NEXT: mv a0, a1
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; CHECK-NEXT: bge a3, a0, .LBB0_9
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; CHECK-NEXT: j .LBB0_10
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for.body.us.preheader.i:
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%partial_vector = insertelement <4 x i64> zeroinitializer, i64 %input_value, i64 1
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%comparison_vector = shufflevector <4 x i64> %partial_vector, <4 x i64> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
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%comparison_result = icmp sle <4 x i64> %comparison_vector, zeroinitializer
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%selected_value1 = select i1 %cond_flag1, i32 %base_value, i32 1
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%selected_value2 = select i1 %cond_flag2, i32 %base_value, i32 1
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%selected_value3 = select i1 %cond_flag3, i32 %base_value, i32 1
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%bool_to_int = zext <4 x i1> %comparison_result to <4 x i32>
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%extended_vector = shufflevector <4 x i32> %bool_to_int, <4 x i32> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
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%vector_min = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %extended_vector)
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%min1 = call i32 @llvm.smin.i32(i32 %vector_min, i32 %selected_value1)
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%min2 = call i32 @llvm.smin.i32(i32 %selected_value2, i32 %selected_value3)
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%final_min = call i32 @llvm.smin.i32(i32 %min1, i32 %min2)
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store i32 %final_min, ptr null, align 4
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ret i32 0
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}
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‎llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.mir‎

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=register-coalescer -o - %s | FileCheck %s
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---
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name: pr71023
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: pr71023
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x10, $v8, $v10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
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; CHECK-NEXT: undef [[PseudoVMV_V_I_M1_:%[0-9]+]].sub_vrm1_2:vrn8m1 = PseudoVMV_V_I_M1 undef [[PseudoVMV_V_I_M1_]].sub_vrm1_2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]].sub_vrm1_6:vrn8m1 = COPY undef [[PseudoVMV_V_I_M1_]].sub_vrm1_2
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; CHECK-NEXT: BNE undef [[DEF]], $x0, %bb.3
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; CHECK-NEXT: PseudoBR %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: BNE undef [[DEF]], $x0, %bb.3
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; CHECK-NEXT: PseudoBR %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: dead [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
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; CHECK-NEXT: early-clobber [[PseudoVMV_V_I_M1_]].sub_vrm1_0:vrn8m1 = PseudoVRGATHER_VI_M1 undef [[PseudoVMV_V_I_M1_]].sub_vrm1_0, [[PseudoVMV_V_I_M1_]].sub_vrm1_2, 0, 0, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: PseudoVSSEG6E8_V_M1_MASK [[PseudoVMV_V_I_M1_]].sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, undef [[DEF]], killed undef $v0, 0, 3 /* e8 */, implicit $vl, implicit $vtype :: (store unknown-size, align 1)
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; CHECK-NEXT: PseudoRET
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bb.0:
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successors: %bb.3(0x40000000), %bb.1(0x40000000)
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liveins: $x10, $v8, $v10
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%0:gpr = IMPLICIT_DEF
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%1:vrnov0 = PseudoVMV_V_I_M1 undef %1, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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%2:vrnov0 = IMPLICIT_DEF
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undef %3.sub_vrm1_0:vrn6m1nov0 = COPY undef %1
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%3.sub_vrm1_3:vrn6m1nov0 = COPY %2
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%3.sub_vrm1_4:vrn6m1nov0 = COPY undef %1
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BNE undef %0, $x0, %bb.3
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PseudoBR %bb.1
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bb.1:
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successors: %bb.3(0x40000000), %bb.2(0x40000000)
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BNE killed undef %0, $x0, %bb.3
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PseudoBR %bb.2
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bb.2:
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successors: %bb.3(0x80000000)
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bb.3:
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%4:vr = IMPLICIT_DEF
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early-clobber %4:vr = PseudoVRGATHER_VI_M1 undef %4, killed %1, 0, 0, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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undef %5.sub_vrm1_0:vrn6m1 = COPY killed %4
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%5.sub_vrm1_5:vrn6m1 = COPY killed %2
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PseudoVSSEG6E8_V_M1_MASK killed %5, undef %0, killed undef $v0, 0, 3 /* e8 */, implicit $vl, implicit $vtype :: (store unknown-size, align 1)
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PseudoRET
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...

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